1 /*
2 * Driver for Allwinner A10 PS2 host controller
3 *
4 * Author: Vishnu Patekar <vishnupatekar0510@gmail.com>
5 * Aaron.maoye <leafy.myeh@newbietech.com>
6 */
7
8 #include <linux/module.h>
9 #include <linux/serio.h>
10 #include <linux/interrupt.h>
11 #include <linux/errno.h>
12 #include <linux/slab.h>
13 #include <linux/io.h>
14 #include <linux/clk.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/platform_device.h>
17
18 #define DRIVER_NAME "sun4i-ps2"
19
20 /* register offset definitions */
21 #define PS2_REG_GCTL 0x00 /* PS2 Module Global Control Reg */
22 #define PS2_REG_DATA 0x04 /* PS2 Module Data Reg */
23 #define PS2_REG_LCTL 0x08 /* PS2 Module Line Control Reg */
24 #define PS2_REG_LSTS 0x0C /* PS2 Module Line Status Reg */
25 #define PS2_REG_FCTL 0x10 /* PS2 Module FIFO Control Reg */
26 #define PS2_REG_FSTS 0x14 /* PS2 Module FIFO Status Reg */
27 #define PS2_REG_CLKDR 0x18 /* PS2 Module Clock Divider Reg*/
28
29 /* PS2 GLOBAL CONTROL REGISTER PS2_GCTL */
30 #define PS2_GCTL_INTFLAG BIT(4)
31 #define PS2_GCTL_INTEN BIT(3)
32 #define PS2_GCTL_RESET BIT(2)
33 #define PS2_GCTL_MASTER BIT(1)
34 #define PS2_GCTL_BUSEN BIT(0)
35
36 /* PS2 LINE CONTROL REGISTER */
37 #define PS2_LCTL_NOACK BIT(18)
38 #define PS2_LCTL_TXDTOEN BIT(8)
39 #define PS2_LCTL_STOPERREN BIT(3)
40 #define PS2_LCTL_ACKERREN BIT(2)
41 #define PS2_LCTL_PARERREN BIT(1)
42 #define PS2_LCTL_RXDTOEN BIT(0)
43
44 /* PS2 LINE STATUS REGISTER */
45 #define PS2_LSTS_TXTDO BIT(8)
46 #define PS2_LSTS_STOPERR BIT(3)
47 #define PS2_LSTS_ACKERR BIT(2)
48 #define PS2_LSTS_PARERR BIT(1)
49 #define PS2_LSTS_RXTDO BIT(0)
50
51 #define PS2_LINE_ERROR_BIT \
52 (PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \
53 PS2_LSTS_PARERR | PS2_LSTS_RXTDO)
54
55 /* PS2 FIFO CONTROL REGISTER */
56 #define PS2_FCTL_TXRST BIT(17)
57 #define PS2_FCTL_RXRST BIT(16)
58 #define PS2_FCTL_TXUFIEN BIT(10)
59 #define PS2_FCTL_TXOFIEN BIT(9)
60 #define PS2_FCTL_TXRDYIEN BIT(8)
61 #define PS2_FCTL_RXUFIEN BIT(2)
62 #define PS2_FCTL_RXOFIEN BIT(1)
63 #define PS2_FCTL_RXRDYIEN BIT(0)
64
65 /* PS2 FIFO STATUS REGISTER */
66 #define PS2_FSTS_TXUF BIT(10)
67 #define PS2_FSTS_TXOF BIT(9)
68 #define PS2_FSTS_TXRDY BIT(8)
69 #define PS2_FSTS_RXUF BIT(2)
70 #define PS2_FSTS_RXOF BIT(1)
71 #define PS2_FSTS_RXRDY BIT(0)
72
73 #define PS2_FIFO_ERROR_BIT \
74 (PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF)
75
76 #define PS2_SAMPLE_CLK 1000000
77 #define PS2_SCLK 125000
78
79 struct sun4i_ps2data {
80 struct serio *serio;
81 struct device *dev;
82
83 /* IO mapping base */
84 void __iomem *reg_base;
85
86 /* clock management */
87 struct clk *clk;
88
89 /* irq */
90 spinlock_t lock;
91 int irq;
92 };
93
sun4i_ps2_interrupt(int irq,void * dev_id)94 static irqreturn_t sun4i_ps2_interrupt(int irq, void *dev_id)
95 {
96 struct sun4i_ps2data *drvdata = dev_id;
97 u32 intr_status;
98 u32 fifo_status;
99 unsigned char byte;
100 unsigned int rxflags = 0;
101 u32 rval;
102
103 spin_lock(&drvdata->lock);
104
105 /* Get the PS/2 interrupts and clear them */
106 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS);
107 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS);
108
109 /* Check line status register */
110 if (intr_status & PS2_LINE_ERROR_BIT) {
111 rxflags = (intr_status & PS2_LINE_ERROR_BIT) ? SERIO_FRAME : 0;
112 rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_PARITY : 0;
113 rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_TIMEOUT : 0;
114
115 rval = PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR |
116 PS2_LSTS_PARERR | PS2_LSTS_RXTDO;
117 writel(rval, drvdata->reg_base + PS2_REG_LSTS);
118 }
119
120 /* Check FIFO status register */
121 if (fifo_status & PS2_FIFO_ERROR_BIT) {
122 rval = PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_TXRDY |
123 PS2_FSTS_RXUF | PS2_FSTS_RXOF | PS2_FSTS_RXRDY;
124 writel(rval, drvdata->reg_base + PS2_REG_FSTS);
125 }
126
127 rval = (fifo_status >> 16) & 0x3;
128 while (rval--) {
129 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff;
130 serio_interrupt(drvdata->serio, byte, rxflags);
131 }
132
133 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
134 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
135
136 spin_unlock(&drvdata->lock);
137
138 return IRQ_HANDLED;
139 }
140
sun4i_ps2_open(struct serio * serio)141 static int sun4i_ps2_open(struct serio *serio)
142 {
143 struct sun4i_ps2data *drvdata = serio->port_data;
144 u32 src_clk = 0;
145 u32 clk_scdf;
146 u32 clk_pcdf;
147 u32 rval;
148 unsigned long flags;
149
150 /* Set line control and enable interrupt */
151 rval = PS2_LCTL_STOPERREN | PS2_LCTL_ACKERREN
152 | PS2_LCTL_PARERREN | PS2_LCTL_RXDTOEN;
153 writel(rval, drvdata->reg_base + PS2_REG_LCTL);
154
155 /* Reset FIFO */
156 rval = PS2_FCTL_TXRST | PS2_FCTL_RXRST | PS2_FCTL_TXUFIEN
157 | PS2_FCTL_TXOFIEN | PS2_FCTL_RXUFIEN
158 | PS2_FCTL_RXOFIEN | PS2_FCTL_RXRDYIEN;
159
160 writel(rval, drvdata->reg_base + PS2_REG_FCTL);
161
162 src_clk = clk_get_rate(drvdata->clk);
163 /* Set clock divider register */
164 clk_scdf = src_clk / PS2_SAMPLE_CLK - 1;
165 clk_pcdf = PS2_SAMPLE_CLK / PS2_SCLK - 1;
166 rval = (clk_scdf << 8) | clk_pcdf;
167 writel(rval, drvdata->reg_base + PS2_REG_CLKDR);
168
169 /* Set global control register */
170 rval = PS2_GCTL_RESET | PS2_GCTL_INTEN | PS2_GCTL_MASTER
171 | PS2_GCTL_BUSEN;
172
173 spin_lock_irqsave(&drvdata->lock, flags);
174 writel(rval, drvdata->reg_base + PS2_REG_GCTL);
175 spin_unlock_irqrestore(&drvdata->lock, flags);
176
177 return 0;
178 }
179
sun4i_ps2_close(struct serio * serio)180 static void sun4i_ps2_close(struct serio *serio)
181 {
182 struct sun4i_ps2data *drvdata = serio->port_data;
183 u32 rval;
184
185 /* Shut off the interrupt */
186 rval = readl(drvdata->reg_base + PS2_REG_GCTL);
187 writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL);
188
189 synchronize_irq(drvdata->irq);
190 }
191
sun4i_ps2_write(struct serio * serio,unsigned char val)192 static int sun4i_ps2_write(struct serio *serio, unsigned char val)
193 {
194 unsigned long expire = jiffies + msecs_to_jiffies(10000);
195 struct sun4i_ps2data *drvdata = serio->port_data;
196
197 do {
198 if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) {
199 writel(val, drvdata->reg_base + PS2_REG_DATA);
200 return 0;
201 }
202 } while (time_before(jiffies, expire));
203
204 return SERIO_TIMEOUT;
205 }
206
sun4i_ps2_probe(struct platform_device * pdev)207 static int sun4i_ps2_probe(struct platform_device *pdev)
208 {
209 struct resource *res; /* IO mem resources */
210 struct sun4i_ps2data *drvdata;
211 struct serio *serio;
212 struct device *dev = &pdev->dev;
213 int error;
214
215 drvdata = kzalloc(sizeof(struct sun4i_ps2data), GFP_KERNEL);
216 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
217 if (!drvdata || !serio) {
218 error = -ENOMEM;
219 goto err_free_mem;
220 }
221
222 spin_lock_init(&drvdata->lock);
223
224 /* IO */
225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226 if (!res) {
227 dev_err(dev, "failed to locate registers\n");
228 error = -ENXIO;
229 goto err_free_mem;
230 }
231
232 drvdata->reg_base = ioremap(res->start, resource_size(res));
233 if (!drvdata->reg_base) {
234 dev_err(dev, "failed to map registers\n");
235 error = -ENOMEM;
236 goto err_free_mem;
237 }
238
239 drvdata->clk = clk_get(dev, NULL);
240 if (IS_ERR(drvdata->clk)) {
241 error = PTR_ERR(drvdata->clk);
242 dev_err(dev, "couldn't get clock %d\n", error);
243 goto err_ioremap;
244 }
245
246 error = clk_prepare_enable(drvdata->clk);
247 if (error) {
248 dev_err(dev, "failed to enable clock %d\n", error);
249 goto err_clk;
250 }
251
252 serio->id.type = SERIO_8042;
253 serio->write = sun4i_ps2_write;
254 serio->open = sun4i_ps2_open;
255 serio->close = sun4i_ps2_close;
256 serio->port_data = drvdata;
257 serio->dev.parent = dev;
258 strlcpy(serio->name, dev_name(dev), sizeof(serio->name));
259 strlcpy(serio->phys, dev_name(dev), sizeof(serio->phys));
260
261 /* shutoff interrupt */
262 writel(0, drvdata->reg_base + PS2_REG_GCTL);
263
264 /* Get IRQ for the device */
265 drvdata->irq = platform_get_irq(pdev, 0);
266 if (drvdata->irq < 0) {
267 error = drvdata->irq;
268 goto err_disable_clk;
269 }
270
271 drvdata->serio = serio;
272 drvdata->dev = dev;
273
274 error = request_irq(drvdata->irq, sun4i_ps2_interrupt, 0,
275 DRIVER_NAME, drvdata);
276 if (error) {
277 dev_err(drvdata->dev, "failed to allocate interrupt %d: %d\n",
278 drvdata->irq, error);
279 goto err_disable_clk;
280 }
281
282 serio_register_port(serio);
283 platform_set_drvdata(pdev, drvdata);
284
285 return 0; /* success */
286
287 err_disable_clk:
288 clk_disable_unprepare(drvdata->clk);
289 err_clk:
290 clk_put(drvdata->clk);
291 err_ioremap:
292 iounmap(drvdata->reg_base);
293 err_free_mem:
294 kfree(serio);
295 kfree(drvdata);
296 return error;
297 }
298
sun4i_ps2_remove(struct platform_device * pdev)299 static int sun4i_ps2_remove(struct platform_device *pdev)
300 {
301 struct sun4i_ps2data *drvdata = platform_get_drvdata(pdev);
302
303 serio_unregister_port(drvdata->serio);
304
305 free_irq(drvdata->irq, drvdata);
306
307 clk_disable_unprepare(drvdata->clk);
308 clk_put(drvdata->clk);
309
310 iounmap(drvdata->reg_base);
311
312 kfree(drvdata);
313
314 return 0;
315 }
316
317 static const struct of_device_id sun4i_ps2_match[] = {
318 { .compatible = "allwinner,sun4i-a10-ps2", },
319 { },
320 };
321
322 MODULE_DEVICE_TABLE(of, sun4i_ps2_match);
323
324 static struct platform_driver sun4i_ps2_driver = {
325 .probe = sun4i_ps2_probe,
326 .remove = sun4i_ps2_remove,
327 .driver = {
328 .name = DRIVER_NAME,
329 .of_match_table = sun4i_ps2_match,
330 },
331 };
332 module_platform_driver(sun4i_ps2_driver);
333
334 MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
335 MODULE_AUTHOR("Aaron.maoye <leafy.myeh@newbietech.com>");
336 MODULE_DESCRIPTION("Allwinner A10/Sun4i PS/2 driver");
337 MODULE_LICENSE("GPL v2");
338