1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author: Jacob Chen <jacob-chen@iotwrt.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #ifndef __RGA_HW_H__ 15 #define __RGA_HW_H__ 16 17 #define RGA_CMDBUF_SIZE 0x20 18 19 /* Hardware limits */ 20 #define MAX_WIDTH 8192 21 #define MAX_HEIGHT 8192 22 23 #define MIN_WIDTH 34 24 #define MIN_HEIGHT 34 25 26 #define DEFAULT_WIDTH 100 27 #define DEFAULT_HEIGHT 100 28 29 #define RGA_TIMEOUT 500 30 31 /* Registers address */ 32 #define RGA_SYS_CTRL 0x0000 33 #define RGA_CMD_CTRL 0x0004 34 #define RGA_CMD_BASE 0x0008 35 #define RGA_INT 0x0010 36 #define RGA_MMU_CTRL0 0x0014 37 #define RGA_VERSION_INFO 0x0028 38 39 #define RGA_MODE_BASE_REG 0x0100 40 #define RGA_MODE_MAX_REG 0x017C 41 42 #define RGA_MODE_CTRL 0x0100 43 #define RGA_SRC_INFO 0x0104 44 #define RGA_SRC_Y_RGB_BASE_ADDR 0x0108 45 #define RGA_SRC_CB_BASE_ADDR 0x010c 46 #define RGA_SRC_CR_BASE_ADDR 0x0110 47 #define RGA_SRC1_RGB_BASE_ADDR 0x0114 48 #define RGA_SRC_VIR_INFO 0x0118 49 #define RGA_SRC_ACT_INFO 0x011c 50 #define RGA_SRC_X_FACTOR 0x0120 51 #define RGA_SRC_Y_FACTOR 0x0124 52 #define RGA_SRC_BG_COLOR 0x0128 53 #define RGA_SRC_FG_COLOR 0x012c 54 #define RGA_SRC_TR_COLOR0 0x0130 55 #define RGA_SRC_TR_COLOR1 0x0134 56 57 #define RGA_DST_INFO 0x0138 58 #define RGA_DST_Y_RGB_BASE_ADDR 0x013c 59 #define RGA_DST_CB_BASE_ADDR 0x0140 60 #define RGA_DST_CR_BASE_ADDR 0x0144 61 #define RGA_DST_VIR_INFO 0x0148 62 #define RGA_DST_ACT_INFO 0x014c 63 64 #define RGA_ALPHA_CTRL0 0x0150 65 #define RGA_ALPHA_CTRL1 0x0154 66 #define RGA_FADING_CTRL 0x0158 67 #define RGA_PAT_CON 0x015c 68 #define RGA_ROP_CON0 0x0160 69 #define RGA_ROP_CON1 0x0164 70 #define RGA_MASK_BASE 0x0168 71 72 #define RGA_MMU_CTRL1 0x016C 73 #define RGA_MMU_SRC_BASE 0x0170 74 #define RGA_MMU_SRC1_BASE 0x0174 75 #define RGA_MMU_DST_BASE 0x0178 76 77 /* Registers value */ 78 #define RGA_MODE_RENDER_BITBLT 0 79 #define RGA_MODE_RENDER_COLOR_PALETTE 1 80 #define RGA_MODE_RENDER_RECTANGLE_FILL 2 81 #define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3 82 83 #define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0 84 #define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1 85 86 #define RGA_MODE_CF_ROP4_SOLID 0 87 #define RGA_MODE_CF_ROP4_PATTERN 1 88 89 #define RGA_COLOR_FMT_ABGR8888 0 90 #define RGA_COLOR_FMT_XBGR8888 1 91 #define RGA_COLOR_FMT_RGB888 2 92 #define RGA_COLOR_FMT_BGR565 4 93 #define RGA_COLOR_FMT_ABGR1555 5 94 #define RGA_COLOR_FMT_ABGR4444 6 95 #define RGA_COLOR_FMT_YUV422SP 8 96 #define RGA_COLOR_FMT_YUV422P 9 97 #define RGA_COLOR_FMT_YUV420SP 10 98 #define RGA_COLOR_FMT_YUV420P 11 99 /* SRC_COLOR Palette */ 100 #define RGA_COLOR_FMT_CP_1BPP 12 101 #define RGA_COLOR_FMT_CP_2BPP 13 102 #define RGA_COLOR_FMT_CP_4BPP 14 103 #define RGA_COLOR_FMT_CP_8BPP 15 104 #define RGA_COLOR_FMT_MASK 15 105 106 #define RGA_COLOR_FMT_IS_YUV(fmt) \ 107 (((fmt) >= RGA_COLOR_FMT_YUV422SP) && ((fmt) < RGA_COLOR_FMT_CP_1BPP)) 108 #define RGA_COLOR_FMT_IS_RGB(fmt) \ 109 ((fmt) < RGA_COLOR_FMT_YUV422SP) 110 111 #define RGA_COLOR_NONE_SWAP 0 112 #define RGA_COLOR_RB_SWAP 1 113 #define RGA_COLOR_ALPHA_SWAP 2 114 #define RGA_COLOR_UV_SWAP 4 115 116 #define RGA_SRC_CSC_MODE_BYPASS 0 117 #define RGA_SRC_CSC_MODE_BT601_R0 1 118 #define RGA_SRC_CSC_MODE_BT601_R1 2 119 #define RGA_SRC_CSC_MODE_BT709_R0 3 120 #define RGA_SRC_CSC_MODE_BT709_R1 4 121 122 #define RGA_SRC_ROT_MODE_0_DEGREE 0 123 #define RGA_SRC_ROT_MODE_90_DEGREE 1 124 #define RGA_SRC_ROT_MODE_180_DEGREE 2 125 #define RGA_SRC_ROT_MODE_270_DEGREE 3 126 127 #define RGA_SRC_MIRR_MODE_NO 0 128 #define RGA_SRC_MIRR_MODE_X 1 129 #define RGA_SRC_MIRR_MODE_Y 2 130 #define RGA_SRC_MIRR_MODE_X_Y 3 131 132 #define RGA_SRC_HSCL_MODE_NO 0 133 #define RGA_SRC_HSCL_MODE_DOWN 1 134 #define RGA_SRC_HSCL_MODE_UP 2 135 136 #define RGA_SRC_VSCL_MODE_NO 0 137 #define RGA_SRC_VSCL_MODE_DOWN 1 138 #define RGA_SRC_VSCL_MODE_UP 2 139 140 #define RGA_SRC_TRANS_ENABLE_R 1 141 #define RGA_SRC_TRANS_ENABLE_G 2 142 #define RGA_SRC_TRANS_ENABLE_B 4 143 #define RGA_SRC_TRANS_ENABLE_A 8 144 145 #define RGA_SRC_BIC_COE_SELEC_CATROM 0 146 #define RGA_SRC_BIC_COE_SELEC_MITCHELL 1 147 #define RGA_SRC_BIC_COE_SELEC_HERMITE 2 148 #define RGA_SRC_BIC_COE_SELEC_BSPLINE 3 149 150 #define RGA_DST_DITHER_MODE_888_TO_666 0 151 #define RGA_DST_DITHER_MODE_888_TO_565 1 152 #define RGA_DST_DITHER_MODE_888_TO_555 2 153 #define RGA_DST_DITHER_MODE_888_TO_444 3 154 155 #define RGA_DST_CSC_MODE_BYPASS 0 156 #define RGA_DST_CSC_MODE_BT601_R0 1 157 #define RGA_DST_CSC_MODE_BT601_R1 2 158 #define RGA_DST_CSC_MODE_BT709_R0 3 159 160 #define RGA_ALPHA_ROP_MODE_2 0 161 #define RGA_ALPHA_ROP_MODE_3 1 162 #define RGA_ALPHA_ROP_MODE_4 2 163 164 #define RGA_ALPHA_SELECT_ALPHA 0 165 #define RGA_ALPHA_SELECT_ROP 1 166 167 #define RGA_ALPHA_MASK_BIG_ENDIAN 0 168 #define RGA_ALPHA_MASK_LITTLE_ENDIAN 1 169 170 #define RGA_ALPHA_NORMAL 0 171 #define RGA_ALPHA_REVERSE 1 172 173 #define RGA_ALPHA_BLEND_GLOBAL 0 174 #define RGA_ALPHA_BLEND_NORMAL 1 175 #define RGA_ALPHA_BLEND_MULTIPLY 2 176 177 #define RGA_ALPHA_CAL_CUT 0 178 #define RGA_ALPHA_CAL_NORMAL 1 179 180 #define RGA_ALPHA_FACTOR_ZERO 0 181 #define RGA_ALPHA_FACTOR_ONE 1 182 #define RGA_ALPHA_FACTOR_OTHER 2 183 #define RGA_ALPHA_FACTOR_OTHER_REVERSE 3 184 #define RGA_ALPHA_FACTOR_SELF 4 185 186 #define RGA_ALPHA_COLOR_NORMAL 0 187 #define RGA_ALPHA_COLOR_MULTIPLY_CAL 1 188 189 /* Registers union */ 190 union rga_mode_ctrl { 191 unsigned int val; 192 struct { 193 /* [0:2] */ 194 unsigned int render:3; 195 /* [3:6] */ 196 unsigned int bitblt:1; 197 unsigned int cf_rop4_pat:1; 198 unsigned int alpha_zero_key:1; 199 unsigned int gradient_sat:1; 200 /* [7:31] */ 201 unsigned int reserved:25; 202 } data; 203 }; 204 205 union rga_src_info { 206 unsigned int val; 207 struct { 208 /* [0:3] */ 209 unsigned int format:4; 210 /* [4:7] */ 211 unsigned int swap:3; 212 unsigned int cp_endian:1; 213 /* [8:17] */ 214 unsigned int csc_mode:2; 215 unsigned int rot_mode:2; 216 unsigned int mir_mode:2; 217 unsigned int hscl_mode:2; 218 unsigned int vscl_mode:2; 219 /* [18:22] */ 220 unsigned int trans_mode:1; 221 unsigned int trans_enable:4; 222 /* [23:25] */ 223 unsigned int dither_up_en:1; 224 unsigned int bic_coe_sel:2; 225 /* [26:31] */ 226 unsigned int reserved:6; 227 } data; 228 }; 229 230 union rga_src_vir_info { 231 unsigned int val; 232 struct { 233 /* [0:15] */ 234 unsigned int vir_width:15; 235 unsigned int reserved:1; 236 /* [16:25] */ 237 unsigned int vir_stride:10; 238 /* [26:31] */ 239 unsigned int reserved1:6; 240 } data; 241 }; 242 243 union rga_src_act_info { 244 unsigned int val; 245 struct { 246 /* [0:15] */ 247 unsigned int act_width:13; 248 unsigned int reserved:3; 249 /* [16:31] */ 250 unsigned int act_height:13; 251 unsigned int reserved1:3; 252 } data; 253 }; 254 255 union rga_src_x_factor { 256 unsigned int val; 257 struct { 258 /* [0:15] */ 259 unsigned int down_scale_factor:16; 260 /* [16:31] */ 261 unsigned int up_scale_factor:16; 262 } data; 263 }; 264 265 union rga_src_y_factor { 266 unsigned int val; 267 struct { 268 /* [0:15] */ 269 unsigned int down_scale_factor:16; 270 /* [16:31] */ 271 unsigned int up_scale_factor:16; 272 } data; 273 }; 274 275 /* Alpha / Red / Green / Blue */ 276 union rga_src_cp_gr_color { 277 unsigned int val; 278 struct { 279 /* [0:15] */ 280 unsigned int gradient_x:16; 281 /* [16:31] */ 282 unsigned int gradient_y:16; 283 } data; 284 }; 285 286 union rga_src_transparency_color0 { 287 unsigned int val; 288 struct { 289 /* [0:7] */ 290 unsigned int trans_rmin:8; 291 /* [8:15] */ 292 unsigned int trans_gmin:8; 293 /* [16:23] */ 294 unsigned int trans_bmin:8; 295 /* [24:31] */ 296 unsigned int trans_amin:8; 297 } data; 298 }; 299 300 union rga_src_transparency_color1 { 301 unsigned int val; 302 struct { 303 /* [0:7] */ 304 unsigned int trans_rmax:8; 305 /* [8:15] */ 306 unsigned int trans_gmax:8; 307 /* [16:23] */ 308 unsigned int trans_bmax:8; 309 /* [24:31] */ 310 unsigned int trans_amax:8; 311 } data; 312 }; 313 314 union rga_dst_info { 315 unsigned int val; 316 struct { 317 /* [0:3] */ 318 unsigned int format:4; 319 /* [4:6] */ 320 unsigned int swap:3; 321 /* [7:9] */ 322 unsigned int src1_format:3; 323 /* [10:11] */ 324 unsigned int src1_swap:2; 325 /* [12:15] */ 326 unsigned int dither_up_en:1; 327 unsigned int dither_down_en:1; 328 unsigned int dither_down_mode:2; 329 /* [16:18] */ 330 unsigned int csc_mode:2; 331 unsigned int csc_clip:1; 332 /* [19:31] */ 333 unsigned int reserved:13; 334 } data; 335 }; 336 337 union rga_dst_vir_info { 338 unsigned int val; 339 struct { 340 /* [0:15] */ 341 unsigned int vir_stride:15; 342 unsigned int reserved:1; 343 /* [16:31] */ 344 unsigned int src1_vir_stride:15; 345 unsigned int reserved1:1; 346 } data; 347 }; 348 349 union rga_dst_act_info { 350 unsigned int val; 351 struct { 352 /* [0:15] */ 353 unsigned int act_width:12; 354 unsigned int reserved:4; 355 /* [16:31] */ 356 unsigned int act_height:12; 357 unsigned int reserved1:4; 358 } data; 359 }; 360 361 union rga_alpha_ctrl0 { 362 unsigned int val; 363 struct { 364 /* [0:3] */ 365 unsigned int rop_en:1; 366 unsigned int rop_select:1; 367 unsigned int rop_mode:2; 368 /* [4:11] */ 369 unsigned int src_fading_val:8; 370 /* [12:20] */ 371 unsigned int dst_fading_val:8; 372 unsigned int mask_endian:1; 373 /* [21:31] */ 374 unsigned int reserved:11; 375 } data; 376 }; 377 378 union rga_alpha_ctrl1 { 379 unsigned int val; 380 struct { 381 /* [0:1] */ 382 unsigned int dst_color_m0:1; 383 unsigned int src_color_m0:1; 384 /* [2:7] */ 385 unsigned int dst_factor_m0:3; 386 unsigned int src_factor_m0:3; 387 /* [8:9] */ 388 unsigned int dst_alpha_cal_m0:1; 389 unsigned int src_alpha_cal_m0:1; 390 /* [10:13] */ 391 unsigned int dst_blend_m0:2; 392 unsigned int src_blend_m0:2; 393 /* [14:15] */ 394 unsigned int dst_alpha_m0:1; 395 unsigned int src_alpha_m0:1; 396 /* [16:21] */ 397 unsigned int dst_factor_m1:3; 398 unsigned int src_factor_m1:3; 399 /* [22:23] */ 400 unsigned int dst_alpha_cal_m1:1; 401 unsigned int src_alpha_cal_m1:1; 402 /* [24:27] */ 403 unsigned int dst_blend_m1:2; 404 unsigned int src_blend_m1:2; 405 /* [28:29] */ 406 unsigned int dst_alpha_m1:1; 407 unsigned int src_alpha_m1:1; 408 /* [30:31] */ 409 unsigned int reserved:2; 410 } data; 411 }; 412 413 union rga_fading_ctrl { 414 unsigned int val; 415 struct { 416 /* [0:7] */ 417 unsigned int fading_offset_r:8; 418 /* [8:15] */ 419 unsigned int fading_offset_g:8; 420 /* [16:23] */ 421 unsigned int fading_offset_b:8; 422 /* [24:31] */ 423 unsigned int fading_en:1; 424 unsigned int reserved:7; 425 } data; 426 }; 427 428 union rga_pat_con { 429 unsigned int val; 430 struct { 431 /* [0:7] */ 432 unsigned int width:8; 433 /* [8:15] */ 434 unsigned int height:8; 435 /* [16:23] */ 436 unsigned int offset_x:8; 437 /* [24:31] */ 438 unsigned int offset_y:8; 439 } data; 440 }; 441 442 #endif 443