1 /*
2 * Copyright © 2010-2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/version.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/err.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/ioport.h>
27 #include <linux/bug.h>
28 #include <linux/kernel.h>
29 #include <linux/bitops.h>
30 #include <linux/mm.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/rawnand.h>
33 #include <linux/mtd/partitions.h>
34 #include <linux/of.h>
35 #include <linux/of_platform.h>
36 #include <linux/slab.h>
37 #include <linux/list.h>
38 #include <linux/log2.h>
39
40 #include "brcmnand.h"
41
42 /*
43 * This flag controls if WP stays on between erase/write commands to mitigate
44 * flash corruption due to power glitches. Values:
45 * 0: NAND_WP is not used or not available
46 * 1: NAND_WP is set by default, cleared for erase/write operations
47 * 2: NAND_WP is always cleared
48 */
49 static int wp_on = 1;
50 module_param(wp_on, int, 0444);
51
52 /***********************************************************************
53 * Definitions
54 ***********************************************************************/
55
56 #define DRV_NAME "brcmnand"
57
58 #define CMD_NULL 0x00
59 #define CMD_PAGE_READ 0x01
60 #define CMD_SPARE_AREA_READ 0x02
61 #define CMD_STATUS_READ 0x03
62 #define CMD_PROGRAM_PAGE 0x04
63 #define CMD_PROGRAM_SPARE_AREA 0x05
64 #define CMD_COPY_BACK 0x06
65 #define CMD_DEVICE_ID_READ 0x07
66 #define CMD_BLOCK_ERASE 0x08
67 #define CMD_FLASH_RESET 0x09
68 #define CMD_BLOCKS_LOCK 0x0a
69 #define CMD_BLOCKS_LOCK_DOWN 0x0b
70 #define CMD_BLOCKS_UNLOCK 0x0c
71 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
72 #define CMD_PARAMETER_READ 0x0e
73 #define CMD_PARAMETER_CHANGE_COL 0x0f
74 #define CMD_LOW_LEVEL_OP 0x10
75
76 struct brcm_nand_dma_desc {
77 u32 next_desc;
78 u32 next_desc_ext;
79 u32 cmd_irq;
80 u32 dram_addr;
81 u32 dram_addr_ext;
82 u32 tfr_len;
83 u32 total_len;
84 u32 flash_addr;
85 u32 flash_addr_ext;
86 u32 cs;
87 u32 pad2[5];
88 u32 status_valid;
89 } __packed;
90
91 /* Bitfields for brcm_nand_dma_desc::status_valid */
92 #define FLASH_DMA_ECC_ERROR (1 << 8)
93 #define FLASH_DMA_CORR_ERROR (1 << 9)
94
95 /* 512B flash cache in the NAND controller HW */
96 #define FC_SHIFT 9U
97 #define FC_BYTES 512U
98 #define FC_WORDS (FC_BYTES >> 2)
99
100 #define BRCMNAND_MIN_PAGESIZE 512
101 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
102 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
103
104 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
105 #define NAND_POLL_STATUS_TIMEOUT_MS 100
106
107 /* Controller feature flags */
108 enum {
109 BRCMNAND_HAS_1K_SECTORS = BIT(0),
110 BRCMNAND_HAS_PREFETCH = BIT(1),
111 BRCMNAND_HAS_CACHE_MODE = BIT(2),
112 BRCMNAND_HAS_WP = BIT(3),
113 };
114
115 struct brcmnand_controller {
116 struct device *dev;
117 struct nand_controller controller;
118 void __iomem *nand_base;
119 void __iomem *nand_fc; /* flash cache */
120 void __iomem *flash_dma_base;
121 unsigned int irq;
122 unsigned int dma_irq;
123 int nand_version;
124
125 /* Some SoCs provide custom interrupt status register(s) */
126 struct brcmnand_soc *soc;
127
128 /* Some SoCs have a gateable clock for the controller */
129 struct clk *clk;
130
131 int cmd_pending;
132 bool dma_pending;
133 struct completion done;
134 struct completion dma_done;
135
136 /* List of NAND hosts (one for each chip-select) */
137 struct list_head host_list;
138
139 struct brcm_nand_dma_desc *dma_desc;
140 dma_addr_t dma_pa;
141
142 /* in-memory cache of the FLASH_CACHE, used only for some commands */
143 u8 flash_cache[FC_BYTES];
144
145 /* Controller revision details */
146 const u16 *reg_offsets;
147 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
148 const u8 *cs_offsets; /* within each chip-select */
149 const u8 *cs0_offsets; /* within CS0, if different */
150 unsigned int max_block_size;
151 const unsigned int *block_sizes;
152 unsigned int max_page_size;
153 const unsigned int *page_sizes;
154 unsigned int max_oob;
155 u32 features;
156
157 /* for low-power standby/resume only */
158 u32 nand_cs_nand_select;
159 u32 nand_cs_nand_xor;
160 u32 corr_stat_threshold;
161 u32 flash_dma_mode;
162 };
163
164 struct brcmnand_cfg {
165 u64 device_size;
166 unsigned int block_size;
167 unsigned int page_size;
168 unsigned int spare_area_size;
169 unsigned int device_width;
170 unsigned int col_adr_bytes;
171 unsigned int blk_adr_bytes;
172 unsigned int ful_adr_bytes;
173 unsigned int sector_size_1k;
174 unsigned int ecc_level;
175 /* use for low-power standby/resume only */
176 u32 acc_control;
177 u32 config;
178 u32 config_ext;
179 u32 timing_1;
180 u32 timing_2;
181 };
182
183 struct brcmnand_host {
184 struct list_head node;
185
186 struct nand_chip chip;
187 struct platform_device *pdev;
188 int cs;
189
190 unsigned int last_cmd;
191 unsigned int last_byte;
192 u64 last_addr;
193 struct brcmnand_cfg hwcfg;
194 struct brcmnand_controller *ctrl;
195 };
196
197 enum brcmnand_reg {
198 BRCMNAND_CMD_START = 0,
199 BRCMNAND_CMD_EXT_ADDRESS,
200 BRCMNAND_CMD_ADDRESS,
201 BRCMNAND_INTFC_STATUS,
202 BRCMNAND_CS_SELECT,
203 BRCMNAND_CS_XOR,
204 BRCMNAND_LL_OP,
205 BRCMNAND_CS0_BASE,
206 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
207 BRCMNAND_CORR_THRESHOLD,
208 BRCMNAND_CORR_THRESHOLD_EXT,
209 BRCMNAND_UNCORR_COUNT,
210 BRCMNAND_CORR_COUNT,
211 BRCMNAND_CORR_EXT_ADDR,
212 BRCMNAND_CORR_ADDR,
213 BRCMNAND_UNCORR_EXT_ADDR,
214 BRCMNAND_UNCORR_ADDR,
215 BRCMNAND_SEMAPHORE,
216 BRCMNAND_ID,
217 BRCMNAND_ID_EXT,
218 BRCMNAND_LL_RDATA,
219 BRCMNAND_OOB_READ_BASE,
220 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
221 BRCMNAND_OOB_WRITE_BASE,
222 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
223 BRCMNAND_FC_BASE,
224 };
225
226 /* BRCMNAND v4.0 */
227 static const u16 brcmnand_regs_v40[] = {
228 [BRCMNAND_CMD_START] = 0x04,
229 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
230 [BRCMNAND_CMD_ADDRESS] = 0x0c,
231 [BRCMNAND_INTFC_STATUS] = 0x6c,
232 [BRCMNAND_CS_SELECT] = 0x14,
233 [BRCMNAND_CS_XOR] = 0x18,
234 [BRCMNAND_LL_OP] = 0x178,
235 [BRCMNAND_CS0_BASE] = 0x40,
236 [BRCMNAND_CS1_BASE] = 0xd0,
237 [BRCMNAND_CORR_THRESHOLD] = 0x84,
238 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
239 [BRCMNAND_UNCORR_COUNT] = 0,
240 [BRCMNAND_CORR_COUNT] = 0,
241 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
242 [BRCMNAND_CORR_ADDR] = 0x74,
243 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
244 [BRCMNAND_UNCORR_ADDR] = 0x7c,
245 [BRCMNAND_SEMAPHORE] = 0x58,
246 [BRCMNAND_ID] = 0x60,
247 [BRCMNAND_ID_EXT] = 0x64,
248 [BRCMNAND_LL_RDATA] = 0x17c,
249 [BRCMNAND_OOB_READ_BASE] = 0x20,
250 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
251 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
252 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
253 [BRCMNAND_FC_BASE] = 0x200,
254 };
255
256 /* BRCMNAND v5.0 */
257 static const u16 brcmnand_regs_v50[] = {
258 [BRCMNAND_CMD_START] = 0x04,
259 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
260 [BRCMNAND_CMD_ADDRESS] = 0x0c,
261 [BRCMNAND_INTFC_STATUS] = 0x6c,
262 [BRCMNAND_CS_SELECT] = 0x14,
263 [BRCMNAND_CS_XOR] = 0x18,
264 [BRCMNAND_LL_OP] = 0x178,
265 [BRCMNAND_CS0_BASE] = 0x40,
266 [BRCMNAND_CS1_BASE] = 0xd0,
267 [BRCMNAND_CORR_THRESHOLD] = 0x84,
268 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
269 [BRCMNAND_UNCORR_COUNT] = 0,
270 [BRCMNAND_CORR_COUNT] = 0,
271 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
272 [BRCMNAND_CORR_ADDR] = 0x74,
273 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
274 [BRCMNAND_UNCORR_ADDR] = 0x7c,
275 [BRCMNAND_SEMAPHORE] = 0x58,
276 [BRCMNAND_ID] = 0x60,
277 [BRCMNAND_ID_EXT] = 0x64,
278 [BRCMNAND_LL_RDATA] = 0x17c,
279 [BRCMNAND_OOB_READ_BASE] = 0x20,
280 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
281 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
282 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
283 [BRCMNAND_FC_BASE] = 0x200,
284 };
285
286 /* BRCMNAND v6.0 - v7.1 */
287 static const u16 brcmnand_regs_v60[] = {
288 [BRCMNAND_CMD_START] = 0x04,
289 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
290 [BRCMNAND_CMD_ADDRESS] = 0x0c,
291 [BRCMNAND_INTFC_STATUS] = 0x14,
292 [BRCMNAND_CS_SELECT] = 0x18,
293 [BRCMNAND_CS_XOR] = 0x1c,
294 [BRCMNAND_LL_OP] = 0x20,
295 [BRCMNAND_CS0_BASE] = 0x50,
296 [BRCMNAND_CS1_BASE] = 0,
297 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
298 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
299 [BRCMNAND_UNCORR_COUNT] = 0xfc,
300 [BRCMNAND_CORR_COUNT] = 0x100,
301 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
302 [BRCMNAND_CORR_ADDR] = 0x110,
303 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
304 [BRCMNAND_UNCORR_ADDR] = 0x118,
305 [BRCMNAND_SEMAPHORE] = 0x150,
306 [BRCMNAND_ID] = 0x194,
307 [BRCMNAND_ID_EXT] = 0x198,
308 [BRCMNAND_LL_RDATA] = 0x19c,
309 [BRCMNAND_OOB_READ_BASE] = 0x200,
310 [BRCMNAND_OOB_READ_10_BASE] = 0,
311 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
312 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
313 [BRCMNAND_FC_BASE] = 0x400,
314 };
315
316 /* BRCMNAND v7.1 */
317 static const u16 brcmnand_regs_v71[] = {
318 [BRCMNAND_CMD_START] = 0x04,
319 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
320 [BRCMNAND_CMD_ADDRESS] = 0x0c,
321 [BRCMNAND_INTFC_STATUS] = 0x14,
322 [BRCMNAND_CS_SELECT] = 0x18,
323 [BRCMNAND_CS_XOR] = 0x1c,
324 [BRCMNAND_LL_OP] = 0x20,
325 [BRCMNAND_CS0_BASE] = 0x50,
326 [BRCMNAND_CS1_BASE] = 0,
327 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
328 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
329 [BRCMNAND_UNCORR_COUNT] = 0xfc,
330 [BRCMNAND_CORR_COUNT] = 0x100,
331 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
332 [BRCMNAND_CORR_ADDR] = 0x110,
333 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
334 [BRCMNAND_UNCORR_ADDR] = 0x118,
335 [BRCMNAND_SEMAPHORE] = 0x150,
336 [BRCMNAND_ID] = 0x194,
337 [BRCMNAND_ID_EXT] = 0x198,
338 [BRCMNAND_LL_RDATA] = 0x19c,
339 [BRCMNAND_OOB_READ_BASE] = 0x200,
340 [BRCMNAND_OOB_READ_10_BASE] = 0,
341 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
342 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
343 [BRCMNAND_FC_BASE] = 0x400,
344 };
345
346 /* BRCMNAND v7.2 */
347 static const u16 brcmnand_regs_v72[] = {
348 [BRCMNAND_CMD_START] = 0x04,
349 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
350 [BRCMNAND_CMD_ADDRESS] = 0x0c,
351 [BRCMNAND_INTFC_STATUS] = 0x14,
352 [BRCMNAND_CS_SELECT] = 0x18,
353 [BRCMNAND_CS_XOR] = 0x1c,
354 [BRCMNAND_LL_OP] = 0x20,
355 [BRCMNAND_CS0_BASE] = 0x50,
356 [BRCMNAND_CS1_BASE] = 0,
357 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
358 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
359 [BRCMNAND_UNCORR_COUNT] = 0xfc,
360 [BRCMNAND_CORR_COUNT] = 0x100,
361 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
362 [BRCMNAND_CORR_ADDR] = 0x110,
363 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
364 [BRCMNAND_UNCORR_ADDR] = 0x118,
365 [BRCMNAND_SEMAPHORE] = 0x150,
366 [BRCMNAND_ID] = 0x194,
367 [BRCMNAND_ID_EXT] = 0x198,
368 [BRCMNAND_LL_RDATA] = 0x19c,
369 [BRCMNAND_OOB_READ_BASE] = 0x200,
370 [BRCMNAND_OOB_READ_10_BASE] = 0,
371 [BRCMNAND_OOB_WRITE_BASE] = 0x400,
372 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
373 [BRCMNAND_FC_BASE] = 0x600,
374 };
375
376 enum brcmnand_cs_reg {
377 BRCMNAND_CS_CFG_EXT = 0,
378 BRCMNAND_CS_CFG,
379 BRCMNAND_CS_ACC_CONTROL,
380 BRCMNAND_CS_TIMING1,
381 BRCMNAND_CS_TIMING2,
382 };
383
384 /* Per chip-select offsets for v7.1 */
385 static const u8 brcmnand_cs_offsets_v71[] = {
386 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
387 [BRCMNAND_CS_CFG_EXT] = 0x04,
388 [BRCMNAND_CS_CFG] = 0x08,
389 [BRCMNAND_CS_TIMING1] = 0x0c,
390 [BRCMNAND_CS_TIMING2] = 0x10,
391 };
392
393 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
394 static const u8 brcmnand_cs_offsets[] = {
395 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
396 [BRCMNAND_CS_CFG_EXT] = 0x04,
397 [BRCMNAND_CS_CFG] = 0x04,
398 [BRCMNAND_CS_TIMING1] = 0x08,
399 [BRCMNAND_CS_TIMING2] = 0x0c,
400 };
401
402 /* Per chip-select offset for <= v5.0 on CS0 only */
403 static const u8 brcmnand_cs_offsets_cs0[] = {
404 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
405 [BRCMNAND_CS_CFG_EXT] = 0x08,
406 [BRCMNAND_CS_CFG] = 0x08,
407 [BRCMNAND_CS_TIMING1] = 0x10,
408 [BRCMNAND_CS_TIMING2] = 0x14,
409 };
410
411 /*
412 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
413 * one config register, but once the bitfields overflowed, newer controllers
414 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
415 */
416 enum {
417 CFG_BLK_ADR_BYTES_SHIFT = 8,
418 CFG_COL_ADR_BYTES_SHIFT = 12,
419 CFG_FUL_ADR_BYTES_SHIFT = 16,
420 CFG_BUS_WIDTH_SHIFT = 23,
421 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
422 CFG_DEVICE_SIZE_SHIFT = 24,
423
424 /* Only for pre-v7.1 (with no CFG_EXT register) */
425 CFG_PAGE_SIZE_SHIFT = 20,
426 CFG_BLK_SIZE_SHIFT = 28,
427
428 /* Only for v7.1+ (with CFG_EXT register) */
429 CFG_EXT_PAGE_SIZE_SHIFT = 0,
430 CFG_EXT_BLK_SIZE_SHIFT = 4,
431 };
432
433 /* BRCMNAND_INTFC_STATUS */
434 enum {
435 INTFC_FLASH_STATUS = GENMASK(7, 0),
436
437 INTFC_ERASED = BIT(27),
438 INTFC_OOB_VALID = BIT(28),
439 INTFC_CACHE_VALID = BIT(29),
440 INTFC_FLASH_READY = BIT(30),
441 INTFC_CTLR_READY = BIT(31),
442 };
443
nand_readreg(struct brcmnand_controller * ctrl,u32 offs)444 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
445 {
446 return brcmnand_readl(ctrl->nand_base + offs);
447 }
448
nand_writereg(struct brcmnand_controller * ctrl,u32 offs,u32 val)449 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
450 u32 val)
451 {
452 brcmnand_writel(val, ctrl->nand_base + offs);
453 }
454
brcmnand_revision_init(struct brcmnand_controller * ctrl)455 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
456 {
457 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
458 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
459 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
460
461 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
462
463 /* Only support v4.0+? */
464 if (ctrl->nand_version < 0x0400) {
465 dev_err(ctrl->dev, "version %#x not supported\n",
466 ctrl->nand_version);
467 return -ENODEV;
468 }
469
470 /* Register offsets */
471 if (ctrl->nand_version >= 0x0702)
472 ctrl->reg_offsets = brcmnand_regs_v72;
473 else if (ctrl->nand_version >= 0x0701)
474 ctrl->reg_offsets = brcmnand_regs_v71;
475 else if (ctrl->nand_version >= 0x0600)
476 ctrl->reg_offsets = brcmnand_regs_v60;
477 else if (ctrl->nand_version >= 0x0500)
478 ctrl->reg_offsets = brcmnand_regs_v50;
479 else if (ctrl->nand_version >= 0x0400)
480 ctrl->reg_offsets = brcmnand_regs_v40;
481
482 /* Chip-select stride */
483 if (ctrl->nand_version >= 0x0701)
484 ctrl->reg_spacing = 0x14;
485 else
486 ctrl->reg_spacing = 0x10;
487
488 /* Per chip-select registers */
489 if (ctrl->nand_version >= 0x0701) {
490 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
491 } else {
492 ctrl->cs_offsets = brcmnand_cs_offsets;
493
494 /* v3.3-5.0 have a different CS0 offset layout */
495 if (ctrl->nand_version >= 0x0303 &&
496 ctrl->nand_version <= 0x0500)
497 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
498 }
499
500 /* Page / block sizes */
501 if (ctrl->nand_version >= 0x0701) {
502 /* >= v7.1 use nice power-of-2 values! */
503 ctrl->max_page_size = 16 * 1024;
504 ctrl->max_block_size = 2 * 1024 * 1024;
505 } else {
506 ctrl->page_sizes = page_sizes;
507 if (ctrl->nand_version >= 0x0600)
508 ctrl->block_sizes = block_sizes_v6;
509 else
510 ctrl->block_sizes = block_sizes_v4;
511
512 if (ctrl->nand_version < 0x0400) {
513 ctrl->max_page_size = 4096;
514 ctrl->max_block_size = 512 * 1024;
515 }
516 }
517
518 /* Maximum spare area sector size (per 512B) */
519 if (ctrl->nand_version >= 0x0702)
520 ctrl->max_oob = 128;
521 else if (ctrl->nand_version >= 0x0600)
522 ctrl->max_oob = 64;
523 else if (ctrl->nand_version >= 0x0500)
524 ctrl->max_oob = 32;
525 else
526 ctrl->max_oob = 16;
527
528 /* v6.0 and newer (except v6.1) have prefetch support */
529 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
530 ctrl->features |= BRCMNAND_HAS_PREFETCH;
531
532 /*
533 * v6.x has cache mode, but it's implemented differently. Ignore it for
534 * now.
535 */
536 if (ctrl->nand_version >= 0x0700)
537 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
538
539 if (ctrl->nand_version >= 0x0500)
540 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
541
542 if (ctrl->nand_version >= 0x0700)
543 ctrl->features |= BRCMNAND_HAS_WP;
544 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
545 ctrl->features |= BRCMNAND_HAS_WP;
546
547 return 0;
548 }
549
brcmnand_read_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg)550 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
551 enum brcmnand_reg reg)
552 {
553 u16 offs = ctrl->reg_offsets[reg];
554
555 if (offs)
556 return nand_readreg(ctrl, offs);
557 else
558 return 0;
559 }
560
brcmnand_write_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 val)561 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
562 enum brcmnand_reg reg, u32 val)
563 {
564 u16 offs = ctrl->reg_offsets[reg];
565
566 if (offs)
567 nand_writereg(ctrl, offs, val);
568 }
569
brcmnand_rmw_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 mask,unsigned int shift,u32 val)570 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
571 enum brcmnand_reg reg, u32 mask, unsigned
572 int shift, u32 val)
573 {
574 u32 tmp = brcmnand_read_reg(ctrl, reg);
575
576 tmp &= ~mask;
577 tmp |= val << shift;
578 brcmnand_write_reg(ctrl, reg, tmp);
579 }
580
brcmnand_read_fc(struct brcmnand_controller * ctrl,int word)581 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
582 {
583 return __raw_readl(ctrl->nand_fc + word * 4);
584 }
585
brcmnand_write_fc(struct brcmnand_controller * ctrl,int word,u32 val)586 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
587 int word, u32 val)
588 {
589 __raw_writel(val, ctrl->nand_fc + word * 4);
590 }
591
brcmnand_cs_offset(struct brcmnand_controller * ctrl,int cs,enum brcmnand_cs_reg reg)592 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
593 enum brcmnand_cs_reg reg)
594 {
595 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
596 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
597 u8 cs_offs;
598
599 if (cs == 0 && ctrl->cs0_offsets)
600 cs_offs = ctrl->cs0_offsets[reg];
601 else
602 cs_offs = ctrl->cs_offsets[reg];
603
604 if (cs && offs_cs1)
605 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
606
607 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
608 }
609
brcmnand_count_corrected(struct brcmnand_controller * ctrl)610 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
611 {
612 if (ctrl->nand_version < 0x0600)
613 return 1;
614 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
615 }
616
brcmnand_wr_corr_thresh(struct brcmnand_host * host,u8 val)617 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
618 {
619 struct brcmnand_controller *ctrl = host->ctrl;
620 unsigned int shift = 0, bits;
621 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
622 int cs = host->cs;
623
624 if (ctrl->nand_version >= 0x0702)
625 bits = 7;
626 else if (ctrl->nand_version >= 0x0600)
627 bits = 6;
628 else if (ctrl->nand_version >= 0x0500)
629 bits = 5;
630 else
631 bits = 4;
632
633 if (ctrl->nand_version >= 0x0702) {
634 if (cs >= 4)
635 reg = BRCMNAND_CORR_THRESHOLD_EXT;
636 shift = (cs % 4) * bits;
637 } else if (ctrl->nand_version >= 0x0600) {
638 if (cs >= 5)
639 reg = BRCMNAND_CORR_THRESHOLD_EXT;
640 shift = (cs % 5) * bits;
641 }
642 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
643 }
644
brcmnand_cmd_shift(struct brcmnand_controller * ctrl)645 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
646 {
647 if (ctrl->nand_version < 0x0602)
648 return 24;
649 return 0;
650 }
651
652 /***********************************************************************
653 * NAND ACC CONTROL bitfield
654 *
655 * Some bits have remained constant throughout hardware revision, while
656 * others have shifted around.
657 ***********************************************************************/
658
659 /* Constant for all versions (where supported) */
660 enum {
661 /* See BRCMNAND_HAS_CACHE_MODE */
662 ACC_CONTROL_CACHE_MODE = BIT(22),
663
664 /* See BRCMNAND_HAS_PREFETCH */
665 ACC_CONTROL_PREFETCH = BIT(23),
666
667 ACC_CONTROL_PAGE_HIT = BIT(24),
668 ACC_CONTROL_WR_PREEMPT = BIT(25),
669 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
670 ACC_CONTROL_RD_ERASED = BIT(27),
671 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
672 ACC_CONTROL_WR_ECC = BIT(30),
673 ACC_CONTROL_RD_ECC = BIT(31),
674 };
675
brcmnand_spare_area_mask(struct brcmnand_controller * ctrl)676 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
677 {
678 if (ctrl->nand_version >= 0x0702)
679 return GENMASK(7, 0);
680 else if (ctrl->nand_version >= 0x0600)
681 return GENMASK(6, 0);
682 else
683 return GENMASK(5, 0);
684 }
685
686 #define NAND_ACC_CONTROL_ECC_SHIFT 16
687 #define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
688
brcmnand_ecc_level_mask(struct brcmnand_controller * ctrl)689 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
690 {
691 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
692
693 mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
694
695 /* v7.2 includes additional ECC levels */
696 if (ctrl->nand_version >= 0x0702)
697 mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
698
699 return mask;
700 }
701
brcmnand_set_ecc_enabled(struct brcmnand_host * host,int en)702 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
703 {
704 struct brcmnand_controller *ctrl = host->ctrl;
705 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
706 u32 acc_control = nand_readreg(ctrl, offs);
707 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
708
709 if (en) {
710 acc_control |= ecc_flags; /* enable RD/WR ECC */
711 acc_control |= host->hwcfg.ecc_level
712 << NAND_ACC_CONTROL_ECC_SHIFT;
713 } else {
714 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
715 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
716 }
717
718 nand_writereg(ctrl, offs, acc_control);
719 }
720
brcmnand_sector_1k_shift(struct brcmnand_controller * ctrl)721 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
722 {
723 if (ctrl->nand_version >= 0x0702)
724 return 9;
725 else if (ctrl->nand_version >= 0x0600)
726 return 7;
727 else if (ctrl->nand_version >= 0x0500)
728 return 6;
729 else
730 return -1;
731 }
732
brcmnand_get_sector_size_1k(struct brcmnand_host * host)733 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
734 {
735 struct brcmnand_controller *ctrl = host->ctrl;
736 int shift = brcmnand_sector_1k_shift(ctrl);
737 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
738 BRCMNAND_CS_ACC_CONTROL);
739
740 if (shift < 0)
741 return 0;
742
743 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
744 }
745
brcmnand_set_sector_size_1k(struct brcmnand_host * host,int val)746 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
747 {
748 struct brcmnand_controller *ctrl = host->ctrl;
749 int shift = brcmnand_sector_1k_shift(ctrl);
750 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
751 BRCMNAND_CS_ACC_CONTROL);
752 u32 tmp;
753
754 if (shift < 0)
755 return;
756
757 tmp = nand_readreg(ctrl, acc_control_offs);
758 tmp &= ~(1 << shift);
759 tmp |= (!!val) << shift;
760 nand_writereg(ctrl, acc_control_offs, tmp);
761 }
762
763 /***********************************************************************
764 * CS_NAND_SELECT
765 ***********************************************************************/
766
767 enum {
768 CS_SELECT_NAND_WP = BIT(29),
769 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
770 };
771
bcmnand_ctrl_poll_status(struct brcmnand_controller * ctrl,u32 mask,u32 expected_val,unsigned long timeout_ms)772 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
773 u32 mask, u32 expected_val,
774 unsigned long timeout_ms)
775 {
776 unsigned long limit;
777 u32 val;
778
779 if (!timeout_ms)
780 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
781
782 limit = jiffies + msecs_to_jiffies(timeout_ms);
783 do {
784 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
785 if ((val & mask) == expected_val)
786 return 0;
787
788 cpu_relax();
789 } while (time_after(limit, jiffies));
790
791 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
792 expected_val, val & mask);
793
794 return -ETIMEDOUT;
795 }
796
brcmnand_set_wp(struct brcmnand_controller * ctrl,bool en)797 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
798 {
799 u32 val = en ? CS_SELECT_NAND_WP : 0;
800
801 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
802 }
803
804 /***********************************************************************
805 * Flash DMA
806 ***********************************************************************/
807
808 enum flash_dma_reg {
809 FLASH_DMA_REVISION = 0x00,
810 FLASH_DMA_FIRST_DESC = 0x04,
811 FLASH_DMA_FIRST_DESC_EXT = 0x08,
812 FLASH_DMA_CTRL = 0x0c,
813 FLASH_DMA_MODE = 0x10,
814 FLASH_DMA_STATUS = 0x14,
815 FLASH_DMA_INTERRUPT_DESC = 0x18,
816 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
817 FLASH_DMA_ERROR_STATUS = 0x20,
818 FLASH_DMA_CURRENT_DESC = 0x24,
819 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
820 };
821
has_flash_dma(struct brcmnand_controller * ctrl)822 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
823 {
824 return ctrl->flash_dma_base;
825 }
826
flash_dma_buf_ok(const void * buf)827 static inline bool flash_dma_buf_ok(const void *buf)
828 {
829 return buf && !is_vmalloc_addr(buf) &&
830 likely(IS_ALIGNED((uintptr_t)buf, 4));
831 }
832
flash_dma_writel(struct brcmnand_controller * ctrl,u8 offs,u32 val)833 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
834 u32 val)
835 {
836 brcmnand_writel(val, ctrl->flash_dma_base + offs);
837 }
838
flash_dma_readl(struct brcmnand_controller * ctrl,u8 offs)839 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
840 {
841 return brcmnand_readl(ctrl->flash_dma_base + offs);
842 }
843
844 /* Low-level operation types: command, address, write, or read */
845 enum brcmnand_llop_type {
846 LL_OP_CMD,
847 LL_OP_ADDR,
848 LL_OP_WR,
849 LL_OP_RD,
850 };
851
852 /***********************************************************************
853 * Internal support functions
854 ***********************************************************************/
855
is_hamming_ecc(struct brcmnand_controller * ctrl,struct brcmnand_cfg * cfg)856 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
857 struct brcmnand_cfg *cfg)
858 {
859 if (ctrl->nand_version <= 0x0701)
860 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
861 cfg->ecc_level == 15;
862 else
863 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
864 cfg->ecc_level == 15) ||
865 (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
866 }
867
868 /*
869 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
870 * the layout/configuration.
871 * Returns -ERRCODE on failure.
872 */
brcmnand_hamming_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)873 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
874 struct mtd_oob_region *oobregion)
875 {
876 struct nand_chip *chip = mtd_to_nand(mtd);
877 struct brcmnand_host *host = nand_get_controller_data(chip);
878 struct brcmnand_cfg *cfg = &host->hwcfg;
879 int sas = cfg->spare_area_size << cfg->sector_size_1k;
880 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
881
882 if (section >= sectors)
883 return -ERANGE;
884
885 oobregion->offset = (section * sas) + 6;
886 oobregion->length = 3;
887
888 return 0;
889 }
890
brcmnand_hamming_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)891 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
892 struct mtd_oob_region *oobregion)
893 {
894 struct nand_chip *chip = mtd_to_nand(mtd);
895 struct brcmnand_host *host = nand_get_controller_data(chip);
896 struct brcmnand_cfg *cfg = &host->hwcfg;
897 int sas = cfg->spare_area_size << cfg->sector_size_1k;
898 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
899
900 if (section >= sectors * 2)
901 return -ERANGE;
902
903 oobregion->offset = (section / 2) * sas;
904
905 if (section & 1) {
906 oobregion->offset += 9;
907 oobregion->length = 7;
908 } else {
909 oobregion->length = 6;
910
911 /* First sector of each page may have BBI */
912 if (!section) {
913 /*
914 * Small-page NAND use byte 6 for BBI while large-page
915 * NAND use bytes 0 and 1.
916 */
917 if (cfg->page_size > 512) {
918 oobregion->offset += 2;
919 oobregion->length -= 2;
920 } else {
921 oobregion->length--;
922 }
923 }
924 }
925
926 return 0;
927 }
928
929 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
930 .ecc = brcmnand_hamming_ooblayout_ecc,
931 .free = brcmnand_hamming_ooblayout_free,
932 };
933
brcmnand_bch_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)934 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
935 struct mtd_oob_region *oobregion)
936 {
937 struct nand_chip *chip = mtd_to_nand(mtd);
938 struct brcmnand_host *host = nand_get_controller_data(chip);
939 struct brcmnand_cfg *cfg = &host->hwcfg;
940 int sas = cfg->spare_area_size << cfg->sector_size_1k;
941 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
942
943 if (section >= sectors)
944 return -ERANGE;
945
946 oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
947 oobregion->length = chip->ecc.bytes;
948
949 return 0;
950 }
951
brcmnand_bch_ooblayout_free_lp(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)952 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
953 struct mtd_oob_region *oobregion)
954 {
955 struct nand_chip *chip = mtd_to_nand(mtd);
956 struct brcmnand_host *host = nand_get_controller_data(chip);
957 struct brcmnand_cfg *cfg = &host->hwcfg;
958 int sas = cfg->spare_area_size << cfg->sector_size_1k;
959 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
960
961 if (section >= sectors)
962 return -ERANGE;
963
964 if (sas <= chip->ecc.bytes)
965 return 0;
966
967 oobregion->offset = section * sas;
968 oobregion->length = sas - chip->ecc.bytes;
969
970 if (!section) {
971 oobregion->offset++;
972 oobregion->length--;
973 }
974
975 return 0;
976 }
977
brcmnand_bch_ooblayout_free_sp(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)978 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
979 struct mtd_oob_region *oobregion)
980 {
981 struct nand_chip *chip = mtd_to_nand(mtd);
982 struct brcmnand_host *host = nand_get_controller_data(chip);
983 struct brcmnand_cfg *cfg = &host->hwcfg;
984 int sas = cfg->spare_area_size << cfg->sector_size_1k;
985
986 if (section > 1 || sas - chip->ecc.bytes < 6 ||
987 (section && sas - chip->ecc.bytes == 6))
988 return -ERANGE;
989
990 if (!section) {
991 oobregion->offset = 0;
992 oobregion->length = 5;
993 } else {
994 oobregion->offset = 6;
995 oobregion->length = sas - chip->ecc.bytes - 6;
996 }
997
998 return 0;
999 }
1000
1001 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
1002 .ecc = brcmnand_bch_ooblayout_ecc,
1003 .free = brcmnand_bch_ooblayout_free_lp,
1004 };
1005
1006 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
1007 .ecc = brcmnand_bch_ooblayout_ecc,
1008 .free = brcmnand_bch_ooblayout_free_sp,
1009 };
1010
brcmstb_choose_ecc_layout(struct brcmnand_host * host)1011 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
1012 {
1013 struct brcmnand_cfg *p = &host->hwcfg;
1014 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1015 struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1016 unsigned int ecc_level = p->ecc_level;
1017 int sas = p->spare_area_size << p->sector_size_1k;
1018 int sectors = p->page_size / (512 << p->sector_size_1k);
1019
1020 if (p->sector_size_1k)
1021 ecc_level <<= 1;
1022
1023 if (is_hamming_ecc(host->ctrl, p)) {
1024 ecc->bytes = 3 * sectors;
1025 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
1026 return 0;
1027 }
1028
1029 /*
1030 * CONTROLLER_VERSION:
1031 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1032 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1033 * But we will just be conservative.
1034 */
1035 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1036 if (p->page_size == 512)
1037 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
1038 else
1039 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
1040
1041 if (ecc->bytes >= sas) {
1042 dev_err(&host->pdev->dev,
1043 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1044 ecc->bytes, sas);
1045 return -EINVAL;
1046 }
1047
1048 return 0;
1049 }
1050
brcmnand_wp(struct mtd_info * mtd,int wp)1051 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1052 {
1053 struct nand_chip *chip = mtd_to_nand(mtd);
1054 struct brcmnand_host *host = nand_get_controller_data(chip);
1055 struct brcmnand_controller *ctrl = host->ctrl;
1056
1057 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1058 static int old_wp = -1;
1059 int ret;
1060
1061 if (old_wp != wp) {
1062 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1063 old_wp = wp;
1064 }
1065
1066 /*
1067 * make sure ctrl/flash ready before and after
1068 * changing state of #WP pin
1069 */
1070 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |
1071 NAND_STATUS_READY,
1072 NAND_CTRL_RDY |
1073 NAND_STATUS_READY, 0);
1074 if (ret)
1075 return;
1076
1077 brcmnand_set_wp(ctrl, wp);
1078 nand_status_op(chip, NULL);
1079 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1080 ret = bcmnand_ctrl_poll_status(ctrl,
1081 NAND_CTRL_RDY |
1082 NAND_STATUS_READY |
1083 NAND_STATUS_WP,
1084 NAND_CTRL_RDY |
1085 NAND_STATUS_READY |
1086 (wp ? 0 : NAND_STATUS_WP), 0);
1087
1088 if (ret)
1089 dev_err_ratelimited(&host->pdev->dev,
1090 "nand #WP expected %s\n",
1091 wp ? "on" : "off");
1092 }
1093 }
1094
1095 /* Helper functions for reading and writing OOB registers */
oob_reg_read(struct brcmnand_controller * ctrl,u32 offs)1096 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1097 {
1098 u16 offset0, offset10, reg_offs;
1099
1100 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1101 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1102
1103 if (offs >= ctrl->max_oob)
1104 return 0x77;
1105
1106 if (offs >= 16 && offset10)
1107 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1108 else
1109 reg_offs = offset0 + (offs & ~0x03);
1110
1111 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1112 }
1113
oob_reg_write(struct brcmnand_controller * ctrl,u32 offs,u32 data)1114 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1115 u32 data)
1116 {
1117 u16 offset0, offset10, reg_offs;
1118
1119 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1120 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1121
1122 if (offs >= ctrl->max_oob)
1123 return;
1124
1125 if (offs >= 16 && offset10)
1126 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1127 else
1128 reg_offs = offset0 + (offs & ~0x03);
1129
1130 nand_writereg(ctrl, reg_offs, data);
1131 }
1132
1133 /*
1134 * read_oob_from_regs - read data from OOB registers
1135 * @ctrl: NAND controller
1136 * @i: sub-page sector index
1137 * @oob: buffer to read to
1138 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1139 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1140 */
read_oob_from_regs(struct brcmnand_controller * ctrl,int i,u8 * oob,int sas,int sector_1k)1141 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1142 int sas, int sector_1k)
1143 {
1144 int tbytes = sas << sector_1k;
1145 int j;
1146
1147 /* Adjust OOB values for 1K sector size */
1148 if (sector_1k && (i & 0x01))
1149 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1150 tbytes = min_t(int, tbytes, ctrl->max_oob);
1151
1152 for (j = 0; j < tbytes; j++)
1153 oob[j] = oob_reg_read(ctrl, j);
1154 return tbytes;
1155 }
1156
1157 /*
1158 * write_oob_to_regs - write data to OOB registers
1159 * @i: sub-page sector index
1160 * @oob: buffer to write from
1161 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1162 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1163 */
write_oob_to_regs(struct brcmnand_controller * ctrl,int i,const u8 * oob,int sas,int sector_1k)1164 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1165 const u8 *oob, int sas, int sector_1k)
1166 {
1167 int tbytes = sas << sector_1k;
1168 int j;
1169
1170 /* Adjust OOB values for 1K sector size */
1171 if (sector_1k && (i & 0x01))
1172 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1173 tbytes = min_t(int, tbytes, ctrl->max_oob);
1174
1175 for (j = 0; j < tbytes; j += 4)
1176 oob_reg_write(ctrl, j,
1177 (oob[j + 0] << 24) |
1178 (oob[j + 1] << 16) |
1179 (oob[j + 2] << 8) |
1180 (oob[j + 3] << 0));
1181 return tbytes;
1182 }
1183
brcmnand_ctlrdy_irq(int irq,void * data)1184 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1185 {
1186 struct brcmnand_controller *ctrl = data;
1187
1188 /* Discard all NAND_CTLRDY interrupts during DMA */
1189 if (ctrl->dma_pending)
1190 return IRQ_HANDLED;
1191
1192 complete(&ctrl->done);
1193 return IRQ_HANDLED;
1194 }
1195
1196 /* Handle SoC-specific interrupt hardware */
brcmnand_irq(int irq,void * data)1197 static irqreturn_t brcmnand_irq(int irq, void *data)
1198 {
1199 struct brcmnand_controller *ctrl = data;
1200
1201 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1202 return brcmnand_ctlrdy_irq(irq, data);
1203
1204 return IRQ_NONE;
1205 }
1206
brcmnand_dma_irq(int irq,void * data)1207 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1208 {
1209 struct brcmnand_controller *ctrl = data;
1210
1211 complete(&ctrl->dma_done);
1212
1213 return IRQ_HANDLED;
1214 }
1215
brcmnand_send_cmd(struct brcmnand_host * host,int cmd)1216 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1217 {
1218 struct brcmnand_controller *ctrl = host->ctrl;
1219 int ret;
1220
1221 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1222 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1223 BUG_ON(ctrl->cmd_pending != 0);
1224 ctrl->cmd_pending = cmd;
1225
1226 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1227 WARN_ON(ret);
1228
1229 mb(); /* flush previous writes */
1230 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1231 cmd << brcmnand_cmd_shift(ctrl));
1232 }
1233
1234 /***********************************************************************
1235 * NAND MTD API: read/program/erase
1236 ***********************************************************************/
1237
brcmnand_cmd_ctrl(struct mtd_info * mtd,int dat,unsigned int ctrl)1238 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1239 unsigned int ctrl)
1240 {
1241 /* intentionally left blank */
1242 }
1243
brcmnand_waitfunc(struct mtd_info * mtd,struct nand_chip * this)1244 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1245 {
1246 struct nand_chip *chip = mtd_to_nand(mtd);
1247 struct brcmnand_host *host = nand_get_controller_data(chip);
1248 struct brcmnand_controller *ctrl = host->ctrl;
1249 unsigned long timeo = msecs_to_jiffies(100);
1250
1251 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1252 if (ctrl->cmd_pending &&
1253 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1254 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1255 >> brcmnand_cmd_shift(ctrl);
1256
1257 dev_err_ratelimited(ctrl->dev,
1258 "timeout waiting for command %#02x\n", cmd);
1259 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1260 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1261 }
1262 ctrl->cmd_pending = 0;
1263 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1264 INTFC_FLASH_STATUS;
1265 }
1266
1267 enum {
1268 LLOP_RE = BIT(16),
1269 LLOP_WE = BIT(17),
1270 LLOP_ALE = BIT(18),
1271 LLOP_CLE = BIT(19),
1272 LLOP_RETURN_IDLE = BIT(31),
1273
1274 LLOP_DATA_MASK = GENMASK(15, 0),
1275 };
1276
brcmnand_low_level_op(struct brcmnand_host * host,enum brcmnand_llop_type type,u32 data,bool last_op)1277 static int brcmnand_low_level_op(struct brcmnand_host *host,
1278 enum brcmnand_llop_type type, u32 data,
1279 bool last_op)
1280 {
1281 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1282 struct nand_chip *chip = &host->chip;
1283 struct brcmnand_controller *ctrl = host->ctrl;
1284 u32 tmp;
1285
1286 tmp = data & LLOP_DATA_MASK;
1287 switch (type) {
1288 case LL_OP_CMD:
1289 tmp |= LLOP_WE | LLOP_CLE;
1290 break;
1291 case LL_OP_ADDR:
1292 /* WE | ALE */
1293 tmp |= LLOP_WE | LLOP_ALE;
1294 break;
1295 case LL_OP_WR:
1296 /* WE */
1297 tmp |= LLOP_WE;
1298 break;
1299 case LL_OP_RD:
1300 /* RE */
1301 tmp |= LLOP_RE;
1302 break;
1303 }
1304 if (last_op)
1305 /* RETURN_IDLE */
1306 tmp |= LLOP_RETURN_IDLE;
1307
1308 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1309
1310 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1311 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1312
1313 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1314 return brcmnand_waitfunc(mtd, chip);
1315 }
1316
brcmnand_cmdfunc(struct mtd_info * mtd,unsigned command,int column,int page_addr)1317 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1318 int column, int page_addr)
1319 {
1320 struct nand_chip *chip = mtd_to_nand(mtd);
1321 struct brcmnand_host *host = nand_get_controller_data(chip);
1322 struct brcmnand_controller *ctrl = host->ctrl;
1323 u64 addr = (u64)page_addr << chip->page_shift;
1324 int native_cmd = 0;
1325
1326 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1327 command == NAND_CMD_RNDOUT)
1328 addr = (u64)column;
1329 /* Avoid propagating a negative, don't-care address */
1330 else if (page_addr < 0)
1331 addr = 0;
1332
1333 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1334 (unsigned long long)addr);
1335
1336 host->last_cmd = command;
1337 host->last_byte = 0;
1338 host->last_addr = addr;
1339
1340 switch (command) {
1341 case NAND_CMD_RESET:
1342 native_cmd = CMD_FLASH_RESET;
1343 break;
1344 case NAND_CMD_STATUS:
1345 native_cmd = CMD_STATUS_READ;
1346 break;
1347 case NAND_CMD_READID:
1348 native_cmd = CMD_DEVICE_ID_READ;
1349 break;
1350 case NAND_CMD_READOOB:
1351 native_cmd = CMD_SPARE_AREA_READ;
1352 break;
1353 case NAND_CMD_ERASE1:
1354 native_cmd = CMD_BLOCK_ERASE;
1355 brcmnand_wp(mtd, 0);
1356 break;
1357 case NAND_CMD_PARAM:
1358 native_cmd = CMD_PARAMETER_READ;
1359 break;
1360 case NAND_CMD_SET_FEATURES:
1361 case NAND_CMD_GET_FEATURES:
1362 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1363 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1364 break;
1365 case NAND_CMD_RNDOUT:
1366 native_cmd = CMD_PARAMETER_CHANGE_COL;
1367 addr &= ~((u64)(FC_BYTES - 1));
1368 /*
1369 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1370 * NB: hwcfg.sector_size_1k may not be initialized yet
1371 */
1372 if (brcmnand_get_sector_size_1k(host)) {
1373 host->hwcfg.sector_size_1k =
1374 brcmnand_get_sector_size_1k(host);
1375 brcmnand_set_sector_size_1k(host, 0);
1376 }
1377 break;
1378 }
1379
1380 if (!native_cmd)
1381 return;
1382
1383 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1384 (host->cs << 16) | ((addr >> 32) & 0xffff));
1385 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1386 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1387 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1388
1389 brcmnand_send_cmd(host, native_cmd);
1390 brcmnand_waitfunc(mtd, chip);
1391
1392 if (native_cmd == CMD_PARAMETER_READ ||
1393 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1394 /* Copy flash cache word-wise */
1395 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1396 int i;
1397
1398 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
1399
1400 /*
1401 * Must cache the FLASH_CACHE now, since changes in
1402 * SECTOR_SIZE_1K may invalidate it
1403 */
1404 for (i = 0; i < FC_WORDS; i++)
1405 /*
1406 * Flash cache is big endian for parameter pages, at
1407 * least on STB SoCs
1408 */
1409 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1410
1411 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
1412
1413 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1414 if (host->hwcfg.sector_size_1k)
1415 brcmnand_set_sector_size_1k(host,
1416 host->hwcfg.sector_size_1k);
1417 }
1418
1419 /* Re-enable protection is necessary only after erase */
1420 if (command == NAND_CMD_ERASE1)
1421 brcmnand_wp(mtd, 1);
1422 }
1423
brcmnand_read_byte(struct mtd_info * mtd)1424 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1425 {
1426 struct nand_chip *chip = mtd_to_nand(mtd);
1427 struct brcmnand_host *host = nand_get_controller_data(chip);
1428 struct brcmnand_controller *ctrl = host->ctrl;
1429 uint8_t ret = 0;
1430 int addr, offs;
1431
1432 switch (host->last_cmd) {
1433 case NAND_CMD_READID:
1434 if (host->last_byte < 4)
1435 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1436 (24 - (host->last_byte << 3));
1437 else if (host->last_byte < 8)
1438 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1439 (56 - (host->last_byte << 3));
1440 break;
1441
1442 case NAND_CMD_READOOB:
1443 ret = oob_reg_read(ctrl, host->last_byte);
1444 break;
1445
1446 case NAND_CMD_STATUS:
1447 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1448 INTFC_FLASH_STATUS;
1449 if (wp_on) /* hide WP status */
1450 ret |= NAND_STATUS_WP;
1451 break;
1452
1453 case NAND_CMD_PARAM:
1454 case NAND_CMD_RNDOUT:
1455 addr = host->last_addr + host->last_byte;
1456 offs = addr & (FC_BYTES - 1);
1457
1458 /* At FC_BYTES boundary, switch to next column */
1459 if (host->last_byte > 0 && offs == 0)
1460 nand_change_read_column_op(chip, addr, NULL, 0, false);
1461
1462 ret = ctrl->flash_cache[offs];
1463 break;
1464 case NAND_CMD_GET_FEATURES:
1465 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1466 ret = 0;
1467 } else {
1468 bool last = host->last_byte ==
1469 ONFI_SUBFEATURE_PARAM_LEN - 1;
1470 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1471 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1472 }
1473 }
1474
1475 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1476 host->last_byte++;
1477
1478 return ret;
1479 }
1480
brcmnand_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)1481 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1482 {
1483 int i;
1484
1485 for (i = 0; i < len; i++, buf++)
1486 *buf = brcmnand_read_byte(mtd);
1487 }
1488
brcmnand_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)1489 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1490 int len)
1491 {
1492 int i;
1493 struct nand_chip *chip = mtd_to_nand(mtd);
1494 struct brcmnand_host *host = nand_get_controller_data(chip);
1495
1496 switch (host->last_cmd) {
1497 case NAND_CMD_SET_FEATURES:
1498 for (i = 0; i < len; i++)
1499 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1500 (i + 1) == len);
1501 break;
1502 default:
1503 BUG();
1504 break;
1505 }
1506 }
1507
1508 /**
1509 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1510 * following ahead of time:
1511 * - Is this descriptor the beginning or end of a linked list?
1512 * - What is the (DMA) address of the next descriptor in the linked list?
1513 */
brcmnand_fill_dma_desc(struct brcmnand_host * host,struct brcm_nand_dma_desc * desc,u64 addr,dma_addr_t buf,u32 len,u8 dma_cmd,bool begin,bool end,dma_addr_t next_desc)1514 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1515 struct brcm_nand_dma_desc *desc, u64 addr,
1516 dma_addr_t buf, u32 len, u8 dma_cmd,
1517 bool begin, bool end,
1518 dma_addr_t next_desc)
1519 {
1520 memset(desc, 0, sizeof(*desc));
1521 /* Descriptors are written in native byte order (wordwise) */
1522 desc->next_desc = lower_32_bits(next_desc);
1523 desc->next_desc_ext = upper_32_bits(next_desc);
1524 desc->cmd_irq = (dma_cmd << 24) |
1525 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1526 (!!begin) | ((!!end) << 1); /* head, tail */
1527 #ifdef CONFIG_CPU_BIG_ENDIAN
1528 desc->cmd_irq |= 0x01 << 12;
1529 #endif
1530 desc->dram_addr = lower_32_bits(buf);
1531 desc->dram_addr_ext = upper_32_bits(buf);
1532 desc->tfr_len = len;
1533 desc->total_len = len;
1534 desc->flash_addr = lower_32_bits(addr);
1535 desc->flash_addr_ext = upper_32_bits(addr);
1536 desc->cs = host->cs;
1537 desc->status_valid = 0x01;
1538 return 0;
1539 }
1540
1541 /**
1542 * Kick the FLASH_DMA engine, with a given DMA descriptor
1543 */
brcmnand_dma_run(struct brcmnand_host * host,dma_addr_t desc)1544 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1545 {
1546 struct brcmnand_controller *ctrl = host->ctrl;
1547 unsigned long timeo = msecs_to_jiffies(100);
1548
1549 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1550 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1551 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1552 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1553
1554 /* Start FLASH_DMA engine */
1555 ctrl->dma_pending = true;
1556 mb(); /* flush previous writes */
1557 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1558
1559 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1560 dev_err(ctrl->dev,
1561 "timeout waiting for DMA; status %#x, error status %#x\n",
1562 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1563 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1564 }
1565 ctrl->dma_pending = false;
1566 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1567 }
1568
brcmnand_dma_trans(struct brcmnand_host * host,u64 addr,u32 * buf,u32 len,u8 dma_cmd)1569 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1570 u32 len, u8 dma_cmd)
1571 {
1572 struct brcmnand_controller *ctrl = host->ctrl;
1573 dma_addr_t buf_pa;
1574 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1575
1576 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1577 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1578 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1579 return -ENOMEM;
1580 }
1581
1582 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1583 dma_cmd, true, true, 0);
1584
1585 brcmnand_dma_run(host, ctrl->dma_pa);
1586
1587 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1588
1589 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1590 return -EBADMSG;
1591 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1592 return -EUCLEAN;
1593
1594 return 0;
1595 }
1596
1597 /*
1598 * Assumes proper CS is already set
1599 */
brcmnand_read_by_pio(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob,u64 * err_addr)1600 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1601 u64 addr, unsigned int trans, u32 *buf,
1602 u8 *oob, u64 *err_addr)
1603 {
1604 struct brcmnand_host *host = nand_get_controller_data(chip);
1605 struct brcmnand_controller *ctrl = host->ctrl;
1606 int i, j, ret = 0;
1607
1608 /* Clear error addresses */
1609 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1610 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1611 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1612 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
1613
1614 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1615 (host->cs << 16) | ((addr >> 32) & 0xffff));
1616 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1617
1618 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1619 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1620 lower_32_bits(addr));
1621 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1622 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1623 brcmnand_send_cmd(host, CMD_PAGE_READ);
1624 brcmnand_waitfunc(mtd, chip);
1625
1626 if (likely(buf)) {
1627 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1628
1629 for (j = 0; j < FC_WORDS; j++, buf++)
1630 *buf = brcmnand_read_fc(ctrl, j);
1631
1632 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1633 }
1634
1635 if (oob)
1636 oob += read_oob_from_regs(ctrl, i, oob,
1637 mtd->oobsize / trans,
1638 host->hwcfg.sector_size_1k);
1639
1640 if (!ret) {
1641 *err_addr = brcmnand_read_reg(ctrl,
1642 BRCMNAND_UNCORR_ADDR) |
1643 ((u64)(brcmnand_read_reg(ctrl,
1644 BRCMNAND_UNCORR_EXT_ADDR)
1645 & 0xffff) << 32);
1646 if (*err_addr)
1647 ret = -EBADMSG;
1648 }
1649
1650 if (!ret) {
1651 *err_addr = brcmnand_read_reg(ctrl,
1652 BRCMNAND_CORR_ADDR) |
1653 ((u64)(brcmnand_read_reg(ctrl,
1654 BRCMNAND_CORR_EXT_ADDR)
1655 & 0xffff) << 32);
1656 if (*err_addr)
1657 ret = -EUCLEAN;
1658 }
1659 }
1660
1661 return ret;
1662 }
1663
1664 /*
1665 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
1666 * error
1667 *
1668 * Because the HW ECC signals an ECC error if an erase paged has even a single
1669 * bitflip, we must check each ECC error to see if it is actually an erased
1670 * page with bitflips, not a truly corrupted page.
1671 *
1672 * On a real error, return a negative error code (-EBADMSG for ECC error), and
1673 * buf will contain raw data.
1674 * Otherwise, buf gets filled with 0xffs and return the maximum number of
1675 * bitflips-per-ECC-sector to the caller.
1676 *
1677 */
brcmstb_nand_verify_erased_page(struct mtd_info * mtd,struct nand_chip * chip,void * buf,u64 addr)1678 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
1679 struct nand_chip *chip, void *buf, u64 addr)
1680 {
1681 int i, sas;
1682 void *oob = chip->oob_poi;
1683 int bitflips = 0;
1684 int page = addr >> chip->page_shift;
1685 int ret;
1686
1687 if (!buf) {
1688 buf = chip->data_buf;
1689 /* Invalidate page cache */
1690 chip->pagebuf = -1;
1691 }
1692
1693 sas = mtd->oobsize / chip->ecc.steps;
1694
1695 /* read without ecc for verification */
1696 ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
1697 if (ret)
1698 return ret;
1699
1700 for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
1701 ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
1702 oob, sas, NULL, 0,
1703 chip->ecc.strength);
1704 if (ret < 0)
1705 return ret;
1706
1707 bitflips = max(bitflips, ret);
1708 }
1709
1710 return bitflips;
1711 }
1712
brcmnand_read(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob)1713 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1714 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1715 {
1716 struct brcmnand_host *host = nand_get_controller_data(chip);
1717 struct brcmnand_controller *ctrl = host->ctrl;
1718 u64 err_addr = 0;
1719 int err;
1720 bool retry = true;
1721
1722 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1723
1724 try_dmaread:
1725 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1726
1727 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1728 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1729 CMD_PAGE_READ);
1730 if (err) {
1731 if (mtd_is_bitflip_or_eccerr(err))
1732 err_addr = addr;
1733 else
1734 return -EIO;
1735 }
1736 } else {
1737 if (oob)
1738 memset(oob, 0x99, mtd->oobsize);
1739
1740 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1741 oob, &err_addr);
1742 }
1743
1744 if (mtd_is_eccerr(err)) {
1745 /*
1746 * On controller version and 7.0, 7.1 , DMA read after a
1747 * prior PIO read that reported uncorrectable error,
1748 * the DMA engine captures this error following DMA read
1749 * cleared only on subsequent DMA read, so just retry once
1750 * to clear a possible false error reported for current DMA
1751 * read
1752 */
1753 if ((ctrl->nand_version == 0x0700) ||
1754 (ctrl->nand_version == 0x0701)) {
1755 if (retry) {
1756 retry = false;
1757 goto try_dmaread;
1758 }
1759 }
1760
1761 /*
1762 * Controller version 7.2 has hw encoder to detect erased page
1763 * bitflips, apply sw verification for older controllers only
1764 */
1765 if (ctrl->nand_version < 0x0702) {
1766 err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
1767 addr);
1768 /* erased page bitflips corrected */
1769 if (err >= 0)
1770 return err;
1771 }
1772
1773 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1774 (unsigned long long)err_addr);
1775 mtd->ecc_stats.failed++;
1776 /* NAND layer expects zero on ECC errors */
1777 return 0;
1778 }
1779
1780 if (mtd_is_bitflip(err)) {
1781 unsigned int corrected = brcmnand_count_corrected(ctrl);
1782
1783 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1784 (unsigned long long)err_addr);
1785 mtd->ecc_stats.corrected += corrected;
1786 /* Always exceed the software-imposed threshold */
1787 return max(mtd->bitflip_threshold, corrected);
1788 }
1789
1790 return 0;
1791 }
1792
brcmnand_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1793 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1794 uint8_t *buf, int oob_required, int page)
1795 {
1796 struct brcmnand_host *host = nand_get_controller_data(chip);
1797 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1798
1799 nand_read_page_op(chip, page, 0, NULL, 0);
1800
1801 return brcmnand_read(mtd, chip, host->last_addr,
1802 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1803 }
1804
brcmnand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1805 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1806 uint8_t *buf, int oob_required, int page)
1807 {
1808 struct brcmnand_host *host = nand_get_controller_data(chip);
1809 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1810 int ret;
1811
1812 nand_read_page_op(chip, page, 0, NULL, 0);
1813
1814 brcmnand_set_ecc_enabled(host, 0);
1815 ret = brcmnand_read(mtd, chip, host->last_addr,
1816 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1817 brcmnand_set_ecc_enabled(host, 1);
1818 return ret;
1819 }
1820
brcmnand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1821 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1822 int page)
1823 {
1824 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1825 mtd->writesize >> FC_SHIFT,
1826 NULL, (u8 *)chip->oob_poi);
1827 }
1828
brcmnand_read_oob_raw(struct mtd_info * mtd,struct nand_chip * chip,int page)1829 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1830 int page)
1831 {
1832 struct brcmnand_host *host = nand_get_controller_data(chip);
1833
1834 brcmnand_set_ecc_enabled(host, 0);
1835 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1836 mtd->writesize >> FC_SHIFT,
1837 NULL, (u8 *)chip->oob_poi);
1838 brcmnand_set_ecc_enabled(host, 1);
1839 return 0;
1840 }
1841
brcmnand_write(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,const u32 * buf,u8 * oob)1842 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1843 u64 addr, const u32 *buf, u8 *oob)
1844 {
1845 struct brcmnand_host *host = nand_get_controller_data(chip);
1846 struct brcmnand_controller *ctrl = host->ctrl;
1847 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1848 int status, ret = 0;
1849
1850 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1851
1852 if (unlikely((unsigned long)buf & 0x03)) {
1853 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1854 buf = (u32 *)((unsigned long)buf & ~0x03);
1855 }
1856
1857 brcmnand_wp(mtd, 0);
1858
1859 for (i = 0; i < ctrl->max_oob; i += 4)
1860 oob_reg_write(ctrl, i, 0xffffffff);
1861
1862 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1863 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1864 mtd->writesize, CMD_PROGRAM_PAGE))
1865 ret = -EIO;
1866 goto out;
1867 }
1868
1869 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1870 (host->cs << 16) | ((addr >> 32) & 0xffff));
1871 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1872
1873 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1874 /* full address MUST be set before populating FC */
1875 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1876 lower_32_bits(addr));
1877 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1878
1879 if (buf) {
1880 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1881
1882 for (j = 0; j < FC_WORDS; j++, buf++)
1883 brcmnand_write_fc(ctrl, j, *buf);
1884
1885 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1886 } else if (oob) {
1887 for (j = 0; j < FC_WORDS; j++)
1888 brcmnand_write_fc(ctrl, j, 0xffffffff);
1889 }
1890
1891 if (oob) {
1892 oob += write_oob_to_regs(ctrl, i, oob,
1893 mtd->oobsize / trans,
1894 host->hwcfg.sector_size_1k);
1895 }
1896
1897 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1898 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1899 status = brcmnand_waitfunc(mtd, chip);
1900
1901 if (status & NAND_STATUS_FAIL) {
1902 dev_info(ctrl->dev, "program failed at %llx\n",
1903 (unsigned long long)addr);
1904 ret = -EIO;
1905 goto out;
1906 }
1907 }
1908 out:
1909 brcmnand_wp(mtd, 1);
1910 return ret;
1911 }
1912
brcmnand_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)1913 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1914 const uint8_t *buf, int oob_required, int page)
1915 {
1916 struct brcmnand_host *host = nand_get_controller_data(chip);
1917 void *oob = oob_required ? chip->oob_poi : NULL;
1918
1919 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1920 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1921
1922 return nand_prog_page_end_op(chip);
1923 }
1924
brcmnand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)1925 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1926 struct nand_chip *chip, const uint8_t *buf,
1927 int oob_required, int page)
1928 {
1929 struct brcmnand_host *host = nand_get_controller_data(chip);
1930 void *oob = oob_required ? chip->oob_poi : NULL;
1931
1932 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1933 brcmnand_set_ecc_enabled(host, 0);
1934 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1935 brcmnand_set_ecc_enabled(host, 1);
1936
1937 return nand_prog_page_end_op(chip);
1938 }
1939
brcmnand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)1940 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1941 int page)
1942 {
1943 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1944 NULL, chip->oob_poi);
1945 }
1946
brcmnand_write_oob_raw(struct mtd_info * mtd,struct nand_chip * chip,int page)1947 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1948 int page)
1949 {
1950 struct brcmnand_host *host = nand_get_controller_data(chip);
1951 int ret;
1952
1953 brcmnand_set_ecc_enabled(host, 0);
1954 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1955 (u8 *)chip->oob_poi);
1956 brcmnand_set_ecc_enabled(host, 1);
1957
1958 return ret;
1959 }
1960
1961 /***********************************************************************
1962 * Per-CS setup (1 NAND device)
1963 ***********************************************************************/
1964
brcmnand_set_cfg(struct brcmnand_host * host,struct brcmnand_cfg * cfg)1965 static int brcmnand_set_cfg(struct brcmnand_host *host,
1966 struct brcmnand_cfg *cfg)
1967 {
1968 struct brcmnand_controller *ctrl = host->ctrl;
1969 struct nand_chip *chip = &host->chip;
1970 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1971 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1972 BRCMNAND_CS_CFG_EXT);
1973 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1974 BRCMNAND_CS_ACC_CONTROL);
1975 u8 block_size = 0, page_size = 0, device_size = 0;
1976 u32 tmp;
1977
1978 if (ctrl->block_sizes) {
1979 int i, found;
1980
1981 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1982 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1983 block_size = i;
1984 found = 1;
1985 }
1986 if (!found) {
1987 dev_warn(ctrl->dev, "invalid block size %u\n",
1988 cfg->block_size);
1989 return -EINVAL;
1990 }
1991 } else {
1992 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1993 }
1994
1995 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1996 cfg->block_size > ctrl->max_block_size)) {
1997 dev_warn(ctrl->dev, "invalid block size %u\n",
1998 cfg->block_size);
1999 block_size = 0;
2000 }
2001
2002 if (ctrl->page_sizes) {
2003 int i, found;
2004
2005 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
2006 if (ctrl->page_sizes[i] == cfg->page_size) {
2007 page_size = i;
2008 found = 1;
2009 }
2010 if (!found) {
2011 dev_warn(ctrl->dev, "invalid page size %u\n",
2012 cfg->page_size);
2013 return -EINVAL;
2014 }
2015 } else {
2016 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
2017 }
2018
2019 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
2020 cfg->page_size > ctrl->max_page_size)) {
2021 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
2022 return -EINVAL;
2023 }
2024
2025 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
2026 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
2027 (unsigned long long)cfg->device_size);
2028 return -EINVAL;
2029 }
2030 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
2031
2032 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
2033 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
2034 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
2035 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
2036 (device_size << CFG_DEVICE_SIZE_SHIFT);
2037 if (cfg_offs == cfg_ext_offs) {
2038 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
2039 (block_size << CFG_BLK_SIZE_SHIFT);
2040 nand_writereg(ctrl, cfg_offs, tmp);
2041 } else {
2042 nand_writereg(ctrl, cfg_offs, tmp);
2043 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
2044 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
2045 nand_writereg(ctrl, cfg_ext_offs, tmp);
2046 }
2047
2048 tmp = nand_readreg(ctrl, acc_control_offs);
2049 tmp &= ~brcmnand_ecc_level_mask(ctrl);
2050 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
2051 tmp &= ~brcmnand_spare_area_mask(ctrl);
2052 tmp |= cfg->spare_area_size;
2053 nand_writereg(ctrl, acc_control_offs, tmp);
2054
2055 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
2056
2057 /* threshold = ceil(BCH-level * 0.75) */
2058 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2059
2060 return 0;
2061 }
2062
brcmnand_print_cfg(struct brcmnand_host * host,char * buf,struct brcmnand_cfg * cfg)2063 static void brcmnand_print_cfg(struct brcmnand_host *host,
2064 char *buf, struct brcmnand_cfg *cfg)
2065 {
2066 buf += sprintf(buf,
2067 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2068 (unsigned long long)cfg->device_size >> 20,
2069 cfg->block_size >> 10,
2070 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2071 cfg->page_size >= 1024 ? "KiB" : "B",
2072 cfg->spare_area_size, cfg->device_width);
2073
2074 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2075 if (is_hamming_ecc(host->ctrl, cfg))
2076 sprintf(buf, ", Hamming ECC");
2077 else if (cfg->sector_size_1k)
2078 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2079 else
2080 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2081 }
2082
2083 /*
2084 * Minimum number of bytes to address a page. Calculated as:
2085 * roundup(log2(size / page-size) / 8)
2086 *
2087 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2088 * OK because many other things will break if 'size' is irregular...
2089 */
get_blk_adr_bytes(u64 size,u32 writesize)2090 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2091 {
2092 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2093 }
2094
brcmnand_setup_dev(struct brcmnand_host * host)2095 static int brcmnand_setup_dev(struct brcmnand_host *host)
2096 {
2097 struct mtd_info *mtd = nand_to_mtd(&host->chip);
2098 struct nand_chip *chip = &host->chip;
2099 struct brcmnand_controller *ctrl = host->ctrl;
2100 struct brcmnand_cfg *cfg = &host->hwcfg;
2101 char msg[128];
2102 u32 offs, tmp, oob_sector;
2103 int ret;
2104
2105 memset(cfg, 0, sizeof(*cfg));
2106
2107 ret = of_property_read_u32(nand_get_flash_node(chip),
2108 "brcm,nand-oob-sector-size",
2109 &oob_sector);
2110 if (ret) {
2111 /* Use detected size */
2112 cfg->spare_area_size = mtd->oobsize /
2113 (mtd->writesize >> FC_SHIFT);
2114 } else {
2115 cfg->spare_area_size = oob_sector;
2116 }
2117 if (cfg->spare_area_size > ctrl->max_oob)
2118 cfg->spare_area_size = ctrl->max_oob;
2119 /*
2120 * Set oobsize to be consistent with controller's spare_area_size, as
2121 * the rest is inaccessible.
2122 */
2123 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2124
2125 cfg->device_size = mtd->size;
2126 cfg->block_size = mtd->erasesize;
2127 cfg->page_size = mtd->writesize;
2128 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2129 cfg->col_adr_bytes = 2;
2130 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2131
2132 if (chip->ecc.mode != NAND_ECC_HW) {
2133 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2134 chip->ecc.mode);
2135 return -EINVAL;
2136 }
2137
2138 if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
2139 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2140 /* Default to Hamming for 1-bit ECC, if unspecified */
2141 chip->ecc.algo = NAND_ECC_HAMMING;
2142 else
2143 /* Otherwise, BCH */
2144 chip->ecc.algo = NAND_ECC_BCH;
2145 }
2146
2147 if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
2148 chip->ecc.size != 512)) {
2149 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2150 chip->ecc.strength, chip->ecc.size);
2151 return -EINVAL;
2152 }
2153
2154 switch (chip->ecc.size) {
2155 case 512:
2156 if (chip->ecc.algo == NAND_ECC_HAMMING)
2157 cfg->ecc_level = 15;
2158 else
2159 cfg->ecc_level = chip->ecc.strength;
2160 cfg->sector_size_1k = 0;
2161 break;
2162 case 1024:
2163 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2164 dev_err(ctrl->dev, "1KB sectors not supported\n");
2165 return -EINVAL;
2166 }
2167 if (chip->ecc.strength & 0x1) {
2168 dev_err(ctrl->dev,
2169 "odd ECC not supported with 1KB sectors\n");
2170 return -EINVAL;
2171 }
2172
2173 cfg->ecc_level = chip->ecc.strength >> 1;
2174 cfg->sector_size_1k = 1;
2175 break;
2176 default:
2177 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2178 chip->ecc.size);
2179 return -EINVAL;
2180 }
2181
2182 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2183 if (mtd->writesize > 512)
2184 cfg->ful_adr_bytes += cfg->col_adr_bytes;
2185 else
2186 cfg->ful_adr_bytes += 1;
2187
2188 ret = brcmnand_set_cfg(host, cfg);
2189 if (ret)
2190 return ret;
2191
2192 brcmnand_set_ecc_enabled(host, 1);
2193
2194 brcmnand_print_cfg(host, msg, cfg);
2195 dev_info(ctrl->dev, "detected %s\n", msg);
2196
2197 /* Configure ACC_CONTROL */
2198 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2199 tmp = nand_readreg(ctrl, offs);
2200 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2201 tmp &= ~ACC_CONTROL_RD_ERASED;
2202
2203 /* We need to turn on Read from erased paged protected by ECC */
2204 if (ctrl->nand_version >= 0x0702)
2205 tmp |= ACC_CONTROL_RD_ERASED;
2206 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2207 if (ctrl->features & BRCMNAND_HAS_PREFETCH)
2208 tmp &= ~ACC_CONTROL_PREFETCH;
2209
2210 nand_writereg(ctrl, offs, tmp);
2211
2212 return 0;
2213 }
2214
brcmnand_attach_chip(struct nand_chip * chip)2215 static int brcmnand_attach_chip(struct nand_chip *chip)
2216 {
2217 struct mtd_info *mtd = nand_to_mtd(chip);
2218 struct brcmnand_host *host = nand_get_controller_data(chip);
2219 int ret;
2220
2221 chip->options |= NAND_NO_SUBPAGE_WRITE;
2222 /*
2223 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2224 * to/from, and have nand_base pass us a bounce buffer instead, as
2225 * needed.
2226 */
2227 chip->options |= NAND_USE_BOUNCE_BUFFER;
2228
2229 if (chip->bbt_options & NAND_BBT_USE_FLASH)
2230 chip->bbt_options |= NAND_BBT_NO_OOB;
2231
2232 if (brcmnand_setup_dev(host))
2233 return -ENXIO;
2234
2235 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2236
2237 /* only use our internal HW threshold */
2238 mtd->bitflip_threshold = 1;
2239
2240 ret = brcmstb_choose_ecc_layout(host);
2241
2242 return ret;
2243 }
2244
2245 static const struct nand_controller_ops brcmnand_controller_ops = {
2246 .attach_chip = brcmnand_attach_chip,
2247 };
2248
brcmnand_init_cs(struct brcmnand_host * host,struct device_node * dn)2249 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
2250 {
2251 struct brcmnand_controller *ctrl = host->ctrl;
2252 struct platform_device *pdev = host->pdev;
2253 struct mtd_info *mtd;
2254 struct nand_chip *chip;
2255 int ret;
2256 u16 cfg_offs;
2257
2258 ret = of_property_read_u32(dn, "reg", &host->cs);
2259 if (ret) {
2260 dev_err(&pdev->dev, "can't get chip-select\n");
2261 return -ENXIO;
2262 }
2263
2264 mtd = nand_to_mtd(&host->chip);
2265 chip = &host->chip;
2266
2267 nand_set_flash_node(chip, dn);
2268 nand_set_controller_data(chip, host);
2269 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2270 host->cs);
2271 if (!mtd->name)
2272 return -ENOMEM;
2273
2274 mtd->owner = THIS_MODULE;
2275 mtd->dev.parent = &pdev->dev;
2276
2277 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2278 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
2279
2280 chip->cmd_ctrl = brcmnand_cmd_ctrl;
2281 chip->cmdfunc = brcmnand_cmdfunc;
2282 chip->waitfunc = brcmnand_waitfunc;
2283 chip->read_byte = brcmnand_read_byte;
2284 chip->read_buf = brcmnand_read_buf;
2285 chip->write_buf = brcmnand_write_buf;
2286
2287 chip->ecc.mode = NAND_ECC_HW;
2288 chip->ecc.read_page = brcmnand_read_page;
2289 chip->ecc.write_page = brcmnand_write_page;
2290 chip->ecc.read_page_raw = brcmnand_read_page_raw;
2291 chip->ecc.write_page_raw = brcmnand_write_page_raw;
2292 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2293 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2294 chip->ecc.read_oob = brcmnand_read_oob;
2295 chip->ecc.write_oob = brcmnand_write_oob;
2296
2297 chip->controller = &ctrl->controller;
2298
2299 /*
2300 * The bootloader might have configured 16bit mode but
2301 * NAND READID command only works in 8bit mode. We force
2302 * 8bit mode here to ensure that NAND READID commands works.
2303 */
2304 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2305 nand_writereg(ctrl, cfg_offs,
2306 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
2307
2308 ret = nand_scan(chip, 1);
2309 if (ret)
2310 return ret;
2311
2312 ret = mtd_device_register(mtd, NULL, 0);
2313 if (ret)
2314 nand_cleanup(chip);
2315
2316 return ret;
2317 }
2318
brcmnand_save_restore_cs_config(struct brcmnand_host * host,int restore)2319 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2320 int restore)
2321 {
2322 struct brcmnand_controller *ctrl = host->ctrl;
2323 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2324 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2325 BRCMNAND_CS_CFG_EXT);
2326 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2327 BRCMNAND_CS_ACC_CONTROL);
2328 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2329 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2330
2331 if (restore) {
2332 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2333 if (cfg_offs != cfg_ext_offs)
2334 nand_writereg(ctrl, cfg_ext_offs,
2335 host->hwcfg.config_ext);
2336 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2337 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2338 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2339 } else {
2340 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2341 if (cfg_offs != cfg_ext_offs)
2342 host->hwcfg.config_ext =
2343 nand_readreg(ctrl, cfg_ext_offs);
2344 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2345 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2346 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2347 }
2348 }
2349
brcmnand_suspend(struct device * dev)2350 static int brcmnand_suspend(struct device *dev)
2351 {
2352 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2353 struct brcmnand_host *host;
2354
2355 list_for_each_entry(host, &ctrl->host_list, node)
2356 brcmnand_save_restore_cs_config(host, 0);
2357
2358 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2359 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2360 ctrl->corr_stat_threshold =
2361 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2362
2363 if (has_flash_dma(ctrl))
2364 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2365
2366 return 0;
2367 }
2368
brcmnand_resume(struct device * dev)2369 static int brcmnand_resume(struct device *dev)
2370 {
2371 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2372 struct brcmnand_host *host;
2373
2374 if (has_flash_dma(ctrl)) {
2375 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2376 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2377 }
2378
2379 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2380 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2381 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2382 ctrl->corr_stat_threshold);
2383 if (ctrl->soc) {
2384 /* Clear/re-enable interrupt */
2385 ctrl->soc->ctlrdy_ack(ctrl->soc);
2386 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2387 }
2388
2389 list_for_each_entry(host, &ctrl->host_list, node) {
2390 struct nand_chip *chip = &host->chip;
2391
2392 brcmnand_save_restore_cs_config(host, 1);
2393
2394 /* Reset the chip, required by some chips after power-up */
2395 nand_reset_op(chip);
2396 }
2397
2398 return 0;
2399 }
2400
2401 const struct dev_pm_ops brcmnand_pm_ops = {
2402 .suspend = brcmnand_suspend,
2403 .resume = brcmnand_resume,
2404 };
2405 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2406
2407 static const struct of_device_id brcmnand_of_match[] = {
2408 { .compatible = "brcm,brcmnand-v4.0" },
2409 { .compatible = "brcm,brcmnand-v5.0" },
2410 { .compatible = "brcm,brcmnand-v6.0" },
2411 { .compatible = "brcm,brcmnand-v6.1" },
2412 { .compatible = "brcm,brcmnand-v6.2" },
2413 { .compatible = "brcm,brcmnand-v7.0" },
2414 { .compatible = "brcm,brcmnand-v7.1" },
2415 { .compatible = "brcm,brcmnand-v7.2" },
2416 {},
2417 };
2418 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2419
2420 /***********************************************************************
2421 * Platform driver setup (per controller)
2422 ***********************************************************************/
2423
brcmnand_probe(struct platform_device * pdev,struct brcmnand_soc * soc)2424 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2425 {
2426 struct device *dev = &pdev->dev;
2427 struct device_node *dn = dev->of_node, *child;
2428 struct brcmnand_controller *ctrl;
2429 struct resource *res;
2430 int ret;
2431
2432 /* We only support device-tree instantiation */
2433 if (!dn)
2434 return -ENODEV;
2435
2436 if (!of_match_node(brcmnand_of_match, dn))
2437 return -ENODEV;
2438
2439 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2440 if (!ctrl)
2441 return -ENOMEM;
2442
2443 dev_set_drvdata(dev, ctrl);
2444 ctrl->dev = dev;
2445
2446 init_completion(&ctrl->done);
2447 init_completion(&ctrl->dma_done);
2448 nand_controller_init(&ctrl->controller);
2449 ctrl->controller.ops = &brcmnand_controller_ops;
2450 INIT_LIST_HEAD(&ctrl->host_list);
2451
2452 /* NAND register range */
2453 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2454 ctrl->nand_base = devm_ioremap_resource(dev, res);
2455 if (IS_ERR(ctrl->nand_base))
2456 return PTR_ERR(ctrl->nand_base);
2457
2458 /* Enable clock before using NAND registers */
2459 ctrl->clk = devm_clk_get(dev, "nand");
2460 if (!IS_ERR(ctrl->clk)) {
2461 ret = clk_prepare_enable(ctrl->clk);
2462 if (ret)
2463 return ret;
2464 } else {
2465 ret = PTR_ERR(ctrl->clk);
2466 if (ret == -EPROBE_DEFER)
2467 return ret;
2468
2469 ctrl->clk = NULL;
2470 }
2471
2472 /* Initialize NAND revision */
2473 ret = brcmnand_revision_init(ctrl);
2474 if (ret)
2475 goto err;
2476
2477 /*
2478 * Most chips have this cache at a fixed offset within 'nand' block.
2479 * Some must specify this region separately.
2480 */
2481 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2482 if (res) {
2483 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2484 if (IS_ERR(ctrl->nand_fc)) {
2485 ret = PTR_ERR(ctrl->nand_fc);
2486 goto err;
2487 }
2488 } else {
2489 ctrl->nand_fc = ctrl->nand_base +
2490 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2491 }
2492
2493 /* FLASH_DMA */
2494 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2495 if (res) {
2496 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2497 if (IS_ERR(ctrl->flash_dma_base)) {
2498 ret = PTR_ERR(ctrl->flash_dma_base);
2499 goto err;
2500 }
2501
2502 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2503 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2504
2505 /* Allocate descriptor(s) */
2506 ctrl->dma_desc = dmam_alloc_coherent(dev,
2507 sizeof(*ctrl->dma_desc),
2508 &ctrl->dma_pa, GFP_KERNEL);
2509 if (!ctrl->dma_desc) {
2510 ret = -ENOMEM;
2511 goto err;
2512 }
2513
2514 ctrl->dma_irq = platform_get_irq(pdev, 1);
2515 if ((int)ctrl->dma_irq < 0) {
2516 dev_err(dev, "missing FLASH_DMA IRQ\n");
2517 ret = -ENODEV;
2518 goto err;
2519 }
2520
2521 ret = devm_request_irq(dev, ctrl->dma_irq,
2522 brcmnand_dma_irq, 0, DRV_NAME,
2523 ctrl);
2524 if (ret < 0) {
2525 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2526 ctrl->dma_irq, ret);
2527 goto err;
2528 }
2529
2530 dev_info(dev, "enabling FLASH_DMA\n");
2531 }
2532
2533 /* Disable automatic device ID config, direct addressing */
2534 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2535 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2536 /* Disable XOR addressing */
2537 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2538
2539 if (ctrl->features & BRCMNAND_HAS_WP) {
2540 /* Permanently disable write protection */
2541 if (wp_on == 2)
2542 brcmnand_set_wp(ctrl, false);
2543 } else {
2544 wp_on = 0;
2545 }
2546
2547 /* IRQ */
2548 ctrl->irq = platform_get_irq(pdev, 0);
2549 if ((int)ctrl->irq < 0) {
2550 dev_err(dev, "no IRQ defined\n");
2551 ret = -ENODEV;
2552 goto err;
2553 }
2554
2555 /*
2556 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2557 * interesting ways
2558 */
2559 if (soc) {
2560 ctrl->soc = soc;
2561
2562 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2563 DRV_NAME, ctrl);
2564
2565 /* Enable interrupt */
2566 ctrl->soc->ctlrdy_ack(ctrl->soc);
2567 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2568 } else {
2569 /* Use standard interrupt infrastructure */
2570 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2571 DRV_NAME, ctrl);
2572 }
2573 if (ret < 0) {
2574 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2575 ctrl->irq, ret);
2576 goto err;
2577 }
2578
2579 for_each_available_child_of_node(dn, child) {
2580 if (of_device_is_compatible(child, "brcm,nandcs")) {
2581 struct brcmnand_host *host;
2582
2583 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2584 if (!host) {
2585 of_node_put(child);
2586 ret = -ENOMEM;
2587 goto err;
2588 }
2589 host->pdev = pdev;
2590 host->ctrl = ctrl;
2591
2592 ret = brcmnand_init_cs(host, child);
2593 if (ret) {
2594 devm_kfree(dev, host);
2595 continue; /* Try all chip-selects */
2596 }
2597
2598 list_add_tail(&host->node, &ctrl->host_list);
2599 }
2600 }
2601
2602 /* No chip-selects could initialize properly */
2603 if (list_empty(&ctrl->host_list)) {
2604 ret = -ENODEV;
2605 goto err;
2606 }
2607
2608 return 0;
2609
2610 err:
2611 clk_disable_unprepare(ctrl->clk);
2612 return ret;
2613
2614 }
2615 EXPORT_SYMBOL_GPL(brcmnand_probe);
2616
brcmnand_remove(struct platform_device * pdev)2617 int brcmnand_remove(struct platform_device *pdev)
2618 {
2619 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2620 struct brcmnand_host *host;
2621
2622 list_for_each_entry(host, &ctrl->host_list, node)
2623 nand_release(&host->chip);
2624
2625 clk_disable_unprepare(ctrl->clk);
2626
2627 dev_set_drvdata(&pdev->dev, NULL);
2628
2629 return 0;
2630 }
2631 EXPORT_SYMBOL_GPL(brcmnand_remove);
2632
2633 MODULE_LICENSE("GPL v2");
2634 MODULE_AUTHOR("Kevin Cernekee");
2635 MODULE_AUTHOR("Brian Norris");
2636 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2637 MODULE_ALIAS("platform:brcmnand");
2638