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1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #include <linux/if_vlan.h>
8 #include <linux/ip.h>
9 #include <linux/ipv6.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/skbuff.h>
13 #include <linux/sctp.h>
14 #include <linux/vermagic.h>
15 #include <net/gre.h>
16 #include <net/pkt_cls.h>
17 #include <net/vxlan.h>
18 
19 #include "hnae3.h"
20 #include "hns3_enet.h"
21 
22 static void hns3_clear_all_ring(struct hnae3_handle *h);
23 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
24 
25 static const char hns3_driver_name[] = "hns3";
26 const char hns3_driver_version[] = VERMAGIC_STRING;
27 static const char hns3_driver_string[] =
28 			"Hisilicon Ethernet Network Driver for Hip08 Family";
29 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
30 static struct hnae3_client client;
31 
32 /* hns3_pci_tbl - PCI Device ID Table
33  *
34  * Last entry must be all 0s
35  *
36  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
37  *   Class, Class Mask, private data (not used) }
38  */
39 static const struct pci_device_id hns3_pci_tbl[] = {
40 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
43 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
44 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
45 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
46 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
47 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
48 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
49 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
50 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
51 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
52 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
53 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
54 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
55 	/* required last entry */
56 	{0, }
57 };
58 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
59 
hns3_irq_handle(int irq,void * vector)60 static irqreturn_t hns3_irq_handle(int irq, void *vector)
61 {
62 	struct hns3_enet_tqp_vector *tqp_vector = vector;
63 
64 	napi_schedule(&tqp_vector->napi);
65 
66 	return IRQ_HANDLED;
67 }
68 
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)69 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
70 {
71 	struct hns3_enet_tqp_vector *tqp_vectors;
72 	unsigned int i;
73 
74 	for (i = 0; i < priv->vector_num; i++) {
75 		tqp_vectors = &priv->tqp_vector[i];
76 
77 		if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
78 			continue;
79 
80 		/* release the irq resource */
81 		free_irq(tqp_vectors->vector_irq, tqp_vectors);
82 		tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
83 	}
84 }
85 
hns3_nic_init_irq(struct hns3_nic_priv * priv)86 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
87 {
88 	struct hns3_enet_tqp_vector *tqp_vectors;
89 	int txrx_int_idx = 0;
90 	int rx_int_idx = 0;
91 	int tx_int_idx = 0;
92 	unsigned int i;
93 	int ret;
94 
95 	for (i = 0; i < priv->vector_num; i++) {
96 		tqp_vectors = &priv->tqp_vector[i];
97 
98 		if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
99 			continue;
100 
101 		if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
102 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
103 				 "%s-%s-%d", priv->netdev->name, "TxRx",
104 				 txrx_int_idx++);
105 			txrx_int_idx++;
106 		} else if (tqp_vectors->rx_group.ring) {
107 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
108 				 "%s-%s-%d", priv->netdev->name, "Rx",
109 				 rx_int_idx++);
110 		} else if (tqp_vectors->tx_group.ring) {
111 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
112 				 "%s-%s-%d", priv->netdev->name, "Tx",
113 				 tx_int_idx++);
114 		} else {
115 			/* Skip this unused q_vector */
116 			continue;
117 		}
118 
119 		tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
120 
121 		ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
122 				  tqp_vectors->name,
123 				       tqp_vectors);
124 		if (ret) {
125 			netdev_err(priv->netdev, "request irq(%d) fail\n",
126 				   tqp_vectors->vector_irq);
127 			return ret;
128 		}
129 
130 		tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
131 	}
132 
133 	return 0;
134 }
135 
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)136 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
137 				 u32 mask_en)
138 {
139 	writel(mask_en, tqp_vector->mask_addr);
140 }
141 
hns3_vector_enable(struct hns3_enet_tqp_vector * tqp_vector)142 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
143 {
144 	napi_enable(&tqp_vector->napi);
145 
146 	/* enable vector */
147 	hns3_mask_vector_irq(tqp_vector, 1);
148 }
149 
hns3_vector_disable(struct hns3_enet_tqp_vector * tqp_vector)150 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
151 {
152 	/* disable vector */
153 	hns3_mask_vector_irq(tqp_vector, 0);
154 
155 	disable_irq(tqp_vector->vector_irq);
156 	napi_disable(&tqp_vector->napi);
157 }
158 
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)159 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
160 				 u32 rl_value)
161 {
162 	u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
163 
164 	/* this defines the configuration for RL (Interrupt Rate Limiter).
165 	 * Rl defines rate of interrupts i.e. number of interrupts-per-second
166 	 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
167 	 */
168 
169 	if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
170 	    !tqp_vector->rx_group.coal.gl_adapt_enable)
171 		/* According to the hardware, the range of rl_reg is
172 		 * 0-59 and the unit is 4.
173 		 */
174 		rl_reg |=  HNS3_INT_RL_ENABLE_MASK;
175 
176 	writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
177 }
178 
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)179 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
180 				    u32 gl_value)
181 {
182 	u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
183 
184 	writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
185 }
186 
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)187 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
188 				    u32 gl_value)
189 {
190 	u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
191 
192 	writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
193 }
194 
hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)195 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
196 				   struct hns3_nic_priv *priv)
197 {
198 	/* initialize the configuration for interrupt coalescing.
199 	 * 1. GL (Interrupt Gap Limiter)
200 	 * 2. RL (Interrupt Rate Limiter)
201 	 */
202 
203 	/* Default: enable interrupt coalescing self-adaptive and GL */
204 	tqp_vector->tx_group.coal.gl_adapt_enable = 1;
205 	tqp_vector->rx_group.coal.gl_adapt_enable = 1;
206 
207 	tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
208 	tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
209 
210 	tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
211 	tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
212 	tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
213 }
214 
hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)215 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
216 				      struct hns3_nic_priv *priv)
217 {
218 	struct hnae3_handle *h = priv->ae_handle;
219 
220 	hns3_set_vector_coalesce_tx_gl(tqp_vector,
221 				       tqp_vector->tx_group.coal.int_gl);
222 	hns3_set_vector_coalesce_rx_gl(tqp_vector,
223 				       tqp_vector->rx_group.coal.int_gl);
224 	hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
225 }
226 
hns3_nic_set_real_num_queue(struct net_device * netdev)227 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
228 {
229 	struct hnae3_handle *h = hns3_get_handle(netdev);
230 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
231 	unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
232 	int i, ret;
233 
234 	if (kinfo->num_tc <= 1) {
235 		netdev_reset_tc(netdev);
236 	} else {
237 		ret = netdev_set_num_tc(netdev, kinfo->num_tc);
238 		if (ret) {
239 			netdev_err(netdev,
240 				   "netdev_set_num_tc fail, ret=%d!\n", ret);
241 			return ret;
242 		}
243 
244 		for (i = 0; i < HNAE3_MAX_TC; i++) {
245 			if (!kinfo->tc_info[i].enable)
246 				continue;
247 
248 			netdev_set_tc_queue(netdev,
249 					    kinfo->tc_info[i].tc,
250 					    kinfo->tc_info[i].tqp_count,
251 					    kinfo->tc_info[i].tqp_offset);
252 		}
253 	}
254 
255 	ret = netif_set_real_num_tx_queues(netdev, queue_size);
256 	if (ret) {
257 		netdev_err(netdev,
258 			   "netif_set_real_num_tx_queues fail, ret=%d!\n",
259 			   ret);
260 		return ret;
261 	}
262 
263 	ret = netif_set_real_num_rx_queues(netdev, queue_size);
264 	if (ret) {
265 		netdev_err(netdev,
266 			   "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
267 		return ret;
268 	}
269 
270 	return 0;
271 }
272 
hns3_get_max_available_channels(struct hnae3_handle * h)273 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
274 {
275 	u16 free_tqps, max_rss_size, max_tqps;
276 
277 	h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size);
278 	max_tqps = h->kinfo.num_tc * max_rss_size;
279 
280 	return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps));
281 }
282 
hns3_nic_net_up(struct net_device * netdev)283 static int hns3_nic_net_up(struct net_device *netdev)
284 {
285 	struct hns3_nic_priv *priv = netdev_priv(netdev);
286 	struct hnae3_handle *h = priv->ae_handle;
287 	int i, j;
288 	int ret;
289 
290 	ret = hns3_nic_reset_all_ring(h);
291 	if (ret)
292 		return ret;
293 
294 	/* get irq resource for all vectors */
295 	ret = hns3_nic_init_irq(priv);
296 	if (ret) {
297 		netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
298 		return ret;
299 	}
300 
301 	/* enable the vectors */
302 	for (i = 0; i < priv->vector_num; i++)
303 		hns3_vector_enable(&priv->tqp_vector[i]);
304 
305 	/* start the ae_dev */
306 	ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
307 	if (ret)
308 		goto out_start_err;
309 
310 	clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
311 
312 	return 0;
313 
314 out_start_err:
315 	for (j = i - 1; j >= 0; j--)
316 		hns3_vector_disable(&priv->tqp_vector[j]);
317 
318 	hns3_nic_uninit_irq(priv);
319 
320 	return ret;
321 }
322 
hns3_nic_net_open(struct net_device * netdev)323 static int hns3_nic_net_open(struct net_device *netdev)
324 {
325 	struct hns3_nic_priv *priv = netdev_priv(netdev);
326 	struct hnae3_handle *h = hns3_get_handle(netdev);
327 	struct hnae3_knic_private_info *kinfo;
328 	int i, ret;
329 
330 	netif_carrier_off(netdev);
331 
332 	ret = hns3_nic_set_real_num_queue(netdev);
333 	if (ret)
334 		return ret;
335 
336 	ret = hns3_nic_net_up(netdev);
337 	if (ret) {
338 		netdev_err(netdev,
339 			   "hns net up fail, ret=%d!\n", ret);
340 		return ret;
341 	}
342 
343 	kinfo = &h->kinfo;
344 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
345 		netdev_set_prio_tc_map(netdev, i,
346 				       kinfo->prio_tc[i]);
347 	}
348 
349 	priv->ae_handle->last_reset_time = jiffies;
350 	return 0;
351 }
352 
hns3_nic_net_down(struct net_device * netdev)353 static void hns3_nic_net_down(struct net_device *netdev)
354 {
355 	struct hns3_nic_priv *priv = netdev_priv(netdev);
356 	const struct hnae3_ae_ops *ops;
357 	int i;
358 
359 	if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
360 		return;
361 
362 	/* disable vectors */
363 	for (i = 0; i < priv->vector_num; i++)
364 		hns3_vector_disable(&priv->tqp_vector[i]);
365 
366 	/* stop ae_dev */
367 	ops = priv->ae_handle->ae_algo->ops;
368 	if (ops->stop)
369 		ops->stop(priv->ae_handle);
370 
371 	/* free irq resources */
372 	hns3_nic_uninit_irq(priv);
373 
374 	hns3_clear_all_ring(priv->ae_handle);
375 }
376 
hns3_nic_net_stop(struct net_device * netdev)377 static int hns3_nic_net_stop(struct net_device *netdev)
378 {
379 	netif_tx_stop_all_queues(netdev);
380 	netif_carrier_off(netdev);
381 
382 	hns3_nic_net_down(netdev);
383 
384 	return 0;
385 }
386 
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)387 static int hns3_nic_uc_sync(struct net_device *netdev,
388 			    const unsigned char *addr)
389 {
390 	struct hnae3_handle *h = hns3_get_handle(netdev);
391 
392 	if (h->ae_algo->ops->add_uc_addr)
393 		return h->ae_algo->ops->add_uc_addr(h, addr);
394 
395 	return 0;
396 }
397 
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)398 static int hns3_nic_uc_unsync(struct net_device *netdev,
399 			      const unsigned char *addr)
400 {
401 	struct hnae3_handle *h = hns3_get_handle(netdev);
402 
403 	if (h->ae_algo->ops->rm_uc_addr)
404 		return h->ae_algo->ops->rm_uc_addr(h, addr);
405 
406 	return 0;
407 }
408 
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)409 static int hns3_nic_mc_sync(struct net_device *netdev,
410 			    const unsigned char *addr)
411 {
412 	struct hnae3_handle *h = hns3_get_handle(netdev);
413 
414 	if (h->ae_algo->ops->add_mc_addr)
415 		return h->ae_algo->ops->add_mc_addr(h, addr);
416 
417 	return 0;
418 }
419 
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)420 static int hns3_nic_mc_unsync(struct net_device *netdev,
421 			      const unsigned char *addr)
422 {
423 	struct hnae3_handle *h = hns3_get_handle(netdev);
424 
425 	if (h->ae_algo->ops->rm_mc_addr)
426 		return h->ae_algo->ops->rm_mc_addr(h, addr);
427 
428 	return 0;
429 }
430 
hns3_nic_set_rx_mode(struct net_device * netdev)431 static void hns3_nic_set_rx_mode(struct net_device *netdev)
432 {
433 	struct hnae3_handle *h = hns3_get_handle(netdev);
434 
435 	if (h->ae_algo->ops->set_promisc_mode) {
436 		if (netdev->flags & IFF_PROMISC)
437 			h->ae_algo->ops->set_promisc_mode(h, true, true);
438 		else if (netdev->flags & IFF_ALLMULTI)
439 			h->ae_algo->ops->set_promisc_mode(h, false, true);
440 		else
441 			h->ae_algo->ops->set_promisc_mode(h, false, false);
442 	}
443 	if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync))
444 		netdev_err(netdev, "sync uc address fail\n");
445 	if (netdev->flags & IFF_MULTICAST) {
446 		if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync))
447 			netdev_err(netdev, "sync mc address fail\n");
448 
449 		if (h->ae_algo->ops->update_mta_status)
450 			h->ae_algo->ops->update_mta_status(h);
451 	}
452 }
453 
hns3_set_tso(struct sk_buff * skb,u32 * paylen,u16 * mss,u32 * type_cs_vlan_tso)454 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
455 			u16 *mss, u32 *type_cs_vlan_tso)
456 {
457 	u32 l4_offset, hdr_len;
458 	union l3_hdr_info l3;
459 	union l4_hdr_info l4;
460 	u32 l4_paylen;
461 	int ret;
462 
463 	if (!skb_is_gso(skb))
464 		return 0;
465 
466 	ret = skb_cow_head(skb, 0);
467 	if (ret)
468 		return ret;
469 
470 	l3.hdr = skb_network_header(skb);
471 	l4.hdr = skb_transport_header(skb);
472 
473 	/* Software should clear the IPv4's checksum field when tso is
474 	 * needed.
475 	 */
476 	if (l3.v4->version == 4)
477 		l3.v4->check = 0;
478 
479 	/* tunnel packet.*/
480 	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
481 					 SKB_GSO_GRE_CSUM |
482 					 SKB_GSO_UDP_TUNNEL |
483 					 SKB_GSO_UDP_TUNNEL_CSUM)) {
484 		if ((!(skb_shinfo(skb)->gso_type &
485 		    SKB_GSO_PARTIAL)) &&
486 		    (skb_shinfo(skb)->gso_type &
487 		    SKB_GSO_UDP_TUNNEL_CSUM)) {
488 			/* Software should clear the udp's checksum
489 			 * field when tso is needed.
490 			 */
491 			l4.udp->check = 0;
492 		}
493 		/* reset l3&l4 pointers from outer to inner headers */
494 		l3.hdr = skb_inner_network_header(skb);
495 		l4.hdr = skb_inner_transport_header(skb);
496 
497 		/* Software should clear the IPv4's checksum field when
498 		 * tso is needed.
499 		 */
500 		if (l3.v4->version == 4)
501 			l3.v4->check = 0;
502 	}
503 
504 	/* normal or tunnel packet*/
505 	l4_offset = l4.hdr - skb->data;
506 	hdr_len = (l4.tcp->doff * 4) + l4_offset;
507 
508 	/* remove payload length from inner pseudo checksum when tso*/
509 	l4_paylen = skb->len - l4_offset;
510 	csum_replace_by_diff(&l4.tcp->check,
511 			     (__force __wsum)htonl(l4_paylen));
512 
513 	/* find the txbd field values */
514 	*paylen = skb->len - hdr_len;
515 	hnae3_set_bit(*type_cs_vlan_tso,
516 		      HNS3_TXD_TSO_B, 1);
517 
518 	/* get MSS for TSO */
519 	*mss = skb_shinfo(skb)->gso_size;
520 
521 	return 0;
522 }
523 
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)524 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
525 				u8 *il4_proto)
526 {
527 	union {
528 		struct iphdr *v4;
529 		struct ipv6hdr *v6;
530 		unsigned char *hdr;
531 	} l3;
532 	unsigned char *l4_hdr;
533 	unsigned char *exthdr;
534 	u8 l4_proto_tmp;
535 	__be16 frag_off;
536 
537 	/* find outer header point */
538 	l3.hdr = skb_network_header(skb);
539 	l4_hdr = skb_transport_header(skb);
540 
541 	if (skb->protocol == htons(ETH_P_IPV6)) {
542 		exthdr = l3.hdr + sizeof(*l3.v6);
543 		l4_proto_tmp = l3.v6->nexthdr;
544 		if (l4_hdr != exthdr)
545 			ipv6_skip_exthdr(skb, exthdr - skb->data,
546 					 &l4_proto_tmp, &frag_off);
547 	} else if (skb->protocol == htons(ETH_P_IP)) {
548 		l4_proto_tmp = l3.v4->protocol;
549 	} else {
550 		return -EINVAL;
551 	}
552 
553 	*ol4_proto = l4_proto_tmp;
554 
555 	/* tunnel packet */
556 	if (!skb->encapsulation) {
557 		*il4_proto = 0;
558 		return 0;
559 	}
560 
561 	/* find inner header point */
562 	l3.hdr = skb_inner_network_header(skb);
563 	l4_hdr = skb_inner_transport_header(skb);
564 
565 	if (l3.v6->version == 6) {
566 		exthdr = l3.hdr + sizeof(*l3.v6);
567 		l4_proto_tmp = l3.v6->nexthdr;
568 		if (l4_hdr != exthdr)
569 			ipv6_skip_exthdr(skb, exthdr - skb->data,
570 					 &l4_proto_tmp, &frag_off);
571 	} else if (l3.v4->version == 4) {
572 		l4_proto_tmp = l3.v4->protocol;
573 	}
574 
575 	*il4_proto = l4_proto_tmp;
576 
577 	return 0;
578 }
579 
hns3_set_l2l3l4_len(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)580 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
581 				u8 il4_proto, u32 *type_cs_vlan_tso,
582 				u32 *ol_type_vlan_len_msec)
583 {
584 	union {
585 		struct iphdr *v4;
586 		struct ipv6hdr *v6;
587 		unsigned char *hdr;
588 	} l3;
589 	union {
590 		struct tcphdr *tcp;
591 		struct udphdr *udp;
592 		struct gre_base_hdr *gre;
593 		unsigned char *hdr;
594 	} l4;
595 	unsigned char *l2_hdr;
596 	u8 l4_proto = ol4_proto;
597 	u32 ol2_len;
598 	u32 ol3_len;
599 	u32 ol4_len;
600 	u32 l2_len;
601 	u32 l3_len;
602 
603 	l3.hdr = skb_network_header(skb);
604 	l4.hdr = skb_transport_header(skb);
605 
606 	/* compute L2 header size for normal packet, defined in 2 Bytes */
607 	l2_len = l3.hdr - skb->data;
608 	hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
609 			HNS3_TXD_L2LEN_S, l2_len >> 1);
610 
611 	/* tunnel packet*/
612 	if (skb->encapsulation) {
613 		/* compute OL2 header size, defined in 2 Bytes */
614 		ol2_len = l2_len;
615 		hnae3_set_field(*ol_type_vlan_len_msec,
616 				HNS3_TXD_L2LEN_M,
617 				HNS3_TXD_L2LEN_S, ol2_len >> 1);
618 
619 		/* compute OL3 header size, defined in 4 Bytes */
620 		ol3_len = l4.hdr - l3.hdr;
621 		hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
622 				HNS3_TXD_L3LEN_S, ol3_len >> 2);
623 
624 		/* MAC in UDP, MAC in GRE (0x6558)*/
625 		if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
626 			/* switch MAC header ptr from outer to inner header.*/
627 			l2_hdr = skb_inner_mac_header(skb);
628 
629 			/* compute OL4 header size, defined in 4 Bytes. */
630 			ol4_len = l2_hdr - l4.hdr;
631 			hnae3_set_field(*ol_type_vlan_len_msec,
632 					HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
633 					ol4_len >> 2);
634 
635 			/* switch IP header ptr from outer to inner header */
636 			l3.hdr = skb_inner_network_header(skb);
637 
638 			/* compute inner l2 header size, defined in 2 Bytes. */
639 			l2_len = l3.hdr - l2_hdr;
640 			hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
641 					HNS3_TXD_L2LEN_S, l2_len >> 1);
642 		} else {
643 			/* skb packet types not supported by hardware,
644 			 * txbd len fild doesn't be filled.
645 			 */
646 			return;
647 		}
648 
649 		/* switch L4 header pointer from outer to inner */
650 		l4.hdr = skb_inner_transport_header(skb);
651 
652 		l4_proto = il4_proto;
653 	}
654 
655 	/* compute inner(/normal) L3 header size, defined in 4 Bytes */
656 	l3_len = l4.hdr - l3.hdr;
657 	hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
658 			HNS3_TXD_L3LEN_S, l3_len >> 2);
659 
660 	/* compute inner(/normal) L4 header size, defined in 4 Bytes */
661 	switch (l4_proto) {
662 	case IPPROTO_TCP:
663 		hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
664 				HNS3_TXD_L4LEN_S, l4.tcp->doff);
665 		break;
666 	case IPPROTO_SCTP:
667 		hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
668 				HNS3_TXD_L4LEN_S,
669 				(sizeof(struct sctphdr) >> 2));
670 		break;
671 	case IPPROTO_UDP:
672 		hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
673 				HNS3_TXD_L4LEN_S,
674 				(sizeof(struct udphdr) >> 2));
675 		break;
676 	default:
677 		/* skb packet types not supported by hardware,
678 		 * txbd len fild doesn't be filled.
679 		 */
680 		return;
681 	}
682 }
683 
684 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
685  * and it is udp packet, which has a dest port as the IANA assigned.
686  * the hardware is expected to do the checksum offload, but the
687  * hardware will not do the checksum offload when udp dest port is
688  * 4789.
689  */
hns3_tunnel_csum_bug(struct sk_buff * skb)690 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
691 {
692 #define IANA_VXLAN_PORT	4789
693 	union {
694 		struct tcphdr *tcp;
695 		struct udphdr *udp;
696 		struct gre_base_hdr *gre;
697 		unsigned char *hdr;
698 	} l4;
699 
700 	l4.hdr = skb_transport_header(skb);
701 
702 	if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
703 		return false;
704 
705 	skb_checksum_help(skb);
706 
707 	return true;
708 }
709 
hns3_set_l3l4_type_csum(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)710 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
711 				   u8 il4_proto, u32 *type_cs_vlan_tso,
712 				   u32 *ol_type_vlan_len_msec)
713 {
714 	union {
715 		struct iphdr *v4;
716 		struct ipv6hdr *v6;
717 		unsigned char *hdr;
718 	} l3;
719 	u32 l4_proto = ol4_proto;
720 
721 	l3.hdr = skb_network_header(skb);
722 
723 	/* define OL3 type and tunnel type(OL4).*/
724 	if (skb->encapsulation) {
725 		/* define outer network header type.*/
726 		if (skb->protocol == htons(ETH_P_IP)) {
727 			if (skb_is_gso(skb))
728 				hnae3_set_field(*ol_type_vlan_len_msec,
729 						HNS3_TXD_OL3T_M,
730 						HNS3_TXD_OL3T_S,
731 						HNS3_OL3T_IPV4_CSUM);
732 			else
733 				hnae3_set_field(*ol_type_vlan_len_msec,
734 						HNS3_TXD_OL3T_M,
735 						HNS3_TXD_OL3T_S,
736 						HNS3_OL3T_IPV4_NO_CSUM);
737 
738 		} else if (skb->protocol == htons(ETH_P_IPV6)) {
739 			hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
740 					HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
741 		}
742 
743 		/* define tunnel type(OL4).*/
744 		switch (l4_proto) {
745 		case IPPROTO_UDP:
746 			hnae3_set_field(*ol_type_vlan_len_msec,
747 					HNS3_TXD_TUNTYPE_M,
748 					HNS3_TXD_TUNTYPE_S,
749 					HNS3_TUN_MAC_IN_UDP);
750 			break;
751 		case IPPROTO_GRE:
752 			hnae3_set_field(*ol_type_vlan_len_msec,
753 					HNS3_TXD_TUNTYPE_M,
754 					HNS3_TXD_TUNTYPE_S,
755 					HNS3_TUN_NVGRE);
756 			break;
757 		default:
758 			/* drop the skb tunnel packet if hardware don't support,
759 			 * because hardware can't calculate csum when TSO.
760 			 */
761 			if (skb_is_gso(skb))
762 				return -EDOM;
763 
764 			/* the stack computes the IP header already,
765 			 * driver calculate l4 checksum when not TSO.
766 			 */
767 			skb_checksum_help(skb);
768 			return 0;
769 		}
770 
771 		l3.hdr = skb_inner_network_header(skb);
772 		l4_proto = il4_proto;
773 	}
774 
775 	if (l3.v4->version == 4) {
776 		hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
777 				HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
778 
779 		/* the stack computes the IP header already, the only time we
780 		 * need the hardware to recompute it is in the case of TSO.
781 		 */
782 		if (skb_is_gso(skb))
783 			hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
784 	} else if (l3.v6->version == 6) {
785 		hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
786 				HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
787 	}
788 
789 	switch (l4_proto) {
790 	case IPPROTO_TCP:
791 		hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
792 		hnae3_set_field(*type_cs_vlan_tso,
793 				HNS3_TXD_L4T_M,
794 				HNS3_TXD_L4T_S,
795 				HNS3_L4T_TCP);
796 		break;
797 	case IPPROTO_UDP:
798 		if (hns3_tunnel_csum_bug(skb))
799 			break;
800 
801 		hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
802 		hnae3_set_field(*type_cs_vlan_tso,
803 				HNS3_TXD_L4T_M,
804 				HNS3_TXD_L4T_S,
805 				HNS3_L4T_UDP);
806 		break;
807 	case IPPROTO_SCTP:
808 		hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
809 		hnae3_set_field(*type_cs_vlan_tso,
810 				HNS3_TXD_L4T_M,
811 				HNS3_TXD_L4T_S,
812 				HNS3_L4T_SCTP);
813 		break;
814 	default:
815 		/* drop the skb tunnel packet if hardware don't support,
816 		 * because hardware can't calculate csum when TSO.
817 		 */
818 		if (skb_is_gso(skb))
819 			return -EDOM;
820 
821 		/* the stack computes the IP header already,
822 		 * driver calculate l4 checksum when not TSO.
823 		 */
824 		skb_checksum_help(skb);
825 		return 0;
826 	}
827 
828 	return 0;
829 }
830 
hns3_set_txbd_baseinfo(u16 * bdtp_fe_sc_vld_ra_ri,int frag_end)831 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
832 {
833 	/* Config bd buffer end */
834 	hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
835 			HNS3_TXD_BDTYPE_S, 0);
836 	hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
837 	hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
838 	hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
839 }
840 
hns3_fill_desc_vtags(struct sk_buff * skb,struct hns3_enet_ring * tx_ring,u32 * inner_vlan_flag,u32 * out_vlan_flag,u16 * inner_vtag,u16 * out_vtag)841 static int hns3_fill_desc_vtags(struct sk_buff *skb,
842 				struct hns3_enet_ring *tx_ring,
843 				u32 *inner_vlan_flag,
844 				u32 *out_vlan_flag,
845 				u16 *inner_vtag,
846 				u16 *out_vtag)
847 {
848 #define HNS3_TX_VLAN_PRIO_SHIFT 13
849 
850 	if (skb->protocol == htons(ETH_P_8021Q) &&
851 	    !(tx_ring->tqp->handle->kinfo.netdev->features &
852 	    NETIF_F_HW_VLAN_CTAG_TX)) {
853 		/* When HW VLAN acceleration is turned off, and the stack
854 		 * sets the protocol to 802.1q, the driver just need to
855 		 * set the protocol to the encapsulated ethertype.
856 		 */
857 		skb->protocol = vlan_get_protocol(skb);
858 		return 0;
859 	}
860 
861 	if (skb_vlan_tag_present(skb)) {
862 		u16 vlan_tag;
863 
864 		vlan_tag = skb_vlan_tag_get(skb);
865 		vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
866 
867 		/* Based on hw strategy, use out_vtag in two layer tag case,
868 		 * and use inner_vtag in one tag case.
869 		 */
870 		if (skb->protocol == htons(ETH_P_8021Q)) {
871 			hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
872 			*out_vtag = vlan_tag;
873 		} else {
874 			hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
875 			*inner_vtag = vlan_tag;
876 		}
877 	} else if (skb->protocol == htons(ETH_P_8021Q)) {
878 		struct vlan_ethhdr *vhdr;
879 		int rc;
880 
881 		rc = skb_cow_head(skb, 0);
882 		if (rc < 0)
883 			return rc;
884 		vhdr = (struct vlan_ethhdr *)skb->data;
885 		vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
886 					<< HNS3_TX_VLAN_PRIO_SHIFT);
887 	}
888 
889 	skb->protocol = vlan_get_protocol(skb);
890 	return 0;
891 }
892 
hns3_fill_desc(struct hns3_enet_ring * ring,void * priv,int size,dma_addr_t dma,int frag_end,enum hns_desc_type type)893 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
894 			  int size, dma_addr_t dma, int frag_end,
895 			  enum hns_desc_type type)
896 {
897 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
898 	struct hns3_desc *desc = &ring->desc[ring->next_to_use];
899 	u32 ol_type_vlan_len_msec = 0;
900 	u16 bdtp_fe_sc_vld_ra_ri = 0;
901 	u32 type_cs_vlan_tso = 0;
902 	struct sk_buff *skb;
903 	u16 inner_vtag = 0;
904 	u16 out_vtag = 0;
905 	u32 paylen = 0;
906 	u16 mss = 0;
907 	u8 ol4_proto;
908 	u8 il4_proto;
909 	int ret;
910 
911 	/* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
912 	desc_cb->priv = priv;
913 	desc_cb->length = size;
914 	desc_cb->dma = dma;
915 	desc_cb->type = type;
916 
917 	/* now, fill the descriptor */
918 	desc->addr = cpu_to_le64(dma);
919 	desc->tx.send_size = cpu_to_le16((u16)size);
920 	hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
921 	desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
922 
923 	if (type == DESC_TYPE_SKB) {
924 		skb = (struct sk_buff *)priv;
925 		paylen = skb->len;
926 
927 		ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
928 					   &ol_type_vlan_len_msec,
929 					   &inner_vtag, &out_vtag);
930 		if (unlikely(ret))
931 			return ret;
932 
933 		if (skb->ip_summed == CHECKSUM_PARTIAL) {
934 			skb_reset_mac_len(skb);
935 
936 			ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
937 			if (ret)
938 				return ret;
939 			hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
940 					    &type_cs_vlan_tso,
941 					    &ol_type_vlan_len_msec);
942 			ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
943 						      &type_cs_vlan_tso,
944 						      &ol_type_vlan_len_msec);
945 			if (ret)
946 				return ret;
947 
948 			ret = hns3_set_tso(skb, &paylen, &mss,
949 					   &type_cs_vlan_tso);
950 			if (ret)
951 				return ret;
952 		}
953 
954 		/* Set txbd */
955 		desc->tx.ol_type_vlan_len_msec =
956 			cpu_to_le32(ol_type_vlan_len_msec);
957 		desc->tx.type_cs_vlan_tso_len =
958 			cpu_to_le32(type_cs_vlan_tso);
959 		desc->tx.paylen = cpu_to_le32(paylen);
960 		desc->tx.mss = cpu_to_le16(mss);
961 		desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
962 		desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
963 	}
964 
965 	/* move ring pointer to next.*/
966 	ring_ptr_move_fw(ring, next_to_use);
967 
968 	return 0;
969 }
970 
hns3_fill_desc_tso(struct hns3_enet_ring * ring,void * priv,int size,dma_addr_t dma,int frag_end,enum hns_desc_type type)971 static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv,
972 			      int size, dma_addr_t dma, int frag_end,
973 			      enum hns_desc_type type)
974 {
975 	unsigned int frag_buf_num;
976 	unsigned int k;
977 	int sizeoflast;
978 	int ret;
979 
980 	frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
981 	sizeoflast = size % HNS3_MAX_BD_SIZE;
982 	sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
983 
984 	/* When the frag size is bigger than hardware, split this frag */
985 	for (k = 0; k < frag_buf_num; k++) {
986 		ret = hns3_fill_desc(ring, priv,
987 				     (k == frag_buf_num - 1) ?
988 				sizeoflast : HNS3_MAX_BD_SIZE,
989 				dma + HNS3_MAX_BD_SIZE * k,
990 				frag_end && (k == frag_buf_num - 1) ? 1 : 0,
991 				(type == DESC_TYPE_SKB && !k) ?
992 					DESC_TYPE_SKB : DESC_TYPE_PAGE);
993 		if (ret)
994 			return ret;
995 	}
996 
997 	return 0;
998 }
999 
hns3_nic_maybe_stop_tso(struct sk_buff ** out_skb,int * bnum,struct hns3_enet_ring * ring)1000 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1001 				   struct hns3_enet_ring *ring)
1002 {
1003 	struct sk_buff *skb = *out_skb;
1004 	struct skb_frag_struct *frag;
1005 	int bdnum_for_frag;
1006 	int frag_num;
1007 	int buf_num;
1008 	int size;
1009 	int i;
1010 
1011 	size = skb_headlen(skb);
1012 	buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1013 
1014 	frag_num = skb_shinfo(skb)->nr_frags;
1015 	for (i = 0; i < frag_num; i++) {
1016 		frag = &skb_shinfo(skb)->frags[i];
1017 		size = skb_frag_size(frag);
1018 		bdnum_for_frag =
1019 			(size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1020 		if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1021 			return -ENOMEM;
1022 
1023 		buf_num += bdnum_for_frag;
1024 	}
1025 
1026 	if (buf_num > ring_space(ring))
1027 		return -EBUSY;
1028 
1029 	*bnum = buf_num;
1030 	return 0;
1031 }
1032 
hns3_nic_maybe_stop_tx(struct sk_buff ** out_skb,int * bnum,struct hns3_enet_ring * ring)1033 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1034 				  struct hns3_enet_ring *ring)
1035 {
1036 	struct sk_buff *skb = *out_skb;
1037 	int buf_num;
1038 
1039 	/* No. of segments (plus a header) */
1040 	buf_num = skb_shinfo(skb)->nr_frags + 1;
1041 
1042 	if (buf_num > ring_space(ring))
1043 		return -EBUSY;
1044 
1045 	*bnum = buf_num;
1046 
1047 	return 0;
1048 }
1049 
hns_nic_dma_unmap(struct hns3_enet_ring * ring,int next_to_use_orig)1050 static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig)
1051 {
1052 	struct device *dev = ring_to_dev(ring);
1053 	unsigned int i;
1054 
1055 	for (i = 0; i < ring->desc_num; i++) {
1056 		/* check if this is where we started */
1057 		if (ring->next_to_use == next_to_use_orig)
1058 			break;
1059 
1060 		/* unmap the descriptor dma address */
1061 		if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1062 			dma_unmap_single(dev,
1063 					 ring->desc_cb[ring->next_to_use].dma,
1064 					ring->desc_cb[ring->next_to_use].length,
1065 					DMA_TO_DEVICE);
1066 		else
1067 			dma_unmap_page(dev,
1068 				       ring->desc_cb[ring->next_to_use].dma,
1069 				       ring->desc_cb[ring->next_to_use].length,
1070 				       DMA_TO_DEVICE);
1071 
1072 		/* rollback one */
1073 		ring_ptr_move_bw(ring, next_to_use);
1074 	}
1075 }
1076 
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)1077 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1078 {
1079 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1080 	struct hns3_nic_ring_data *ring_data =
1081 		&tx_ring_data(priv, skb->queue_mapping);
1082 	struct hns3_enet_ring *ring = ring_data->ring;
1083 	struct device *dev = priv->dev;
1084 	struct netdev_queue *dev_queue;
1085 	struct skb_frag_struct *frag;
1086 	int next_to_use_head;
1087 	int next_to_use_frag;
1088 	dma_addr_t dma;
1089 	int buf_num;
1090 	int seg_num;
1091 	int size;
1092 	int ret;
1093 	int i;
1094 
1095 	/* Prefetch the data used later */
1096 	prefetch(skb->data);
1097 
1098 	switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1099 	case -EBUSY:
1100 		u64_stats_update_begin(&ring->syncp);
1101 		ring->stats.tx_busy++;
1102 		u64_stats_update_end(&ring->syncp);
1103 
1104 		goto out_net_tx_busy;
1105 	case -ENOMEM:
1106 		u64_stats_update_begin(&ring->syncp);
1107 		ring->stats.sw_err_cnt++;
1108 		u64_stats_update_end(&ring->syncp);
1109 		netdev_err(netdev, "no memory to xmit!\n");
1110 
1111 		goto out_err_tx_ok;
1112 	default:
1113 		break;
1114 	}
1115 
1116 	/* No. of segments (plus a header) */
1117 	seg_num = skb_shinfo(skb)->nr_frags + 1;
1118 	/* Fill the first part */
1119 	size = skb_headlen(skb);
1120 
1121 	next_to_use_head = ring->next_to_use;
1122 
1123 	dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1124 	if (dma_mapping_error(dev, dma)) {
1125 		netdev_err(netdev, "TX head DMA map failed\n");
1126 		ring->stats.sw_err_cnt++;
1127 		goto out_err_tx_ok;
1128 	}
1129 
1130 	ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,
1131 			   DESC_TYPE_SKB);
1132 	if (ret)
1133 		goto head_dma_map_err;
1134 
1135 	next_to_use_frag = ring->next_to_use;
1136 	/* Fill the fragments */
1137 	for (i = 1; i < seg_num; i++) {
1138 		frag = &skb_shinfo(skb)->frags[i - 1];
1139 		size = skb_frag_size(frag);
1140 		dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1141 		if (dma_mapping_error(dev, dma)) {
1142 			netdev_err(netdev, "TX frag(%d) DMA map failed\n", i);
1143 			ring->stats.sw_err_cnt++;
1144 			goto frag_dma_map_err;
1145 		}
1146 		ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma,
1147 				    seg_num - 1 == i ? 1 : 0,
1148 				    DESC_TYPE_PAGE);
1149 
1150 		if (ret)
1151 			goto frag_dma_map_err;
1152 	}
1153 
1154 	/* Complete translate all packets */
1155 	dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1156 	netdev_tx_sent_queue(dev_queue, skb->len);
1157 
1158 	wmb(); /* Commit all data before submit */
1159 
1160 	hnae3_queue_xmit(ring->tqp, buf_num);
1161 
1162 	return NETDEV_TX_OK;
1163 
1164 frag_dma_map_err:
1165 	hns_nic_dma_unmap(ring, next_to_use_frag);
1166 
1167 head_dma_map_err:
1168 	hns_nic_dma_unmap(ring, next_to_use_head);
1169 
1170 out_err_tx_ok:
1171 	dev_kfree_skb_any(skb);
1172 	return NETDEV_TX_OK;
1173 
1174 out_net_tx_busy:
1175 	netif_stop_subqueue(netdev, ring_data->queue_index);
1176 	smp_mb(); /* Commit all data before submit */
1177 
1178 	return NETDEV_TX_BUSY;
1179 }
1180 
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)1181 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1182 {
1183 	struct hnae3_handle *h = hns3_get_handle(netdev);
1184 	struct sockaddr *mac_addr = p;
1185 	int ret;
1186 
1187 	if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1188 		return -EADDRNOTAVAIL;
1189 
1190 	if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1191 		netdev_info(netdev, "already using mac address %pM\n",
1192 			    mac_addr->sa_data);
1193 		return 0;
1194 	}
1195 
1196 	ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1197 	if (ret) {
1198 		netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1199 		return ret;
1200 	}
1201 
1202 	ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1203 
1204 	return 0;
1205 }
1206 
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)1207 static int hns3_nic_set_features(struct net_device *netdev,
1208 				 netdev_features_t features)
1209 {
1210 	netdev_features_t changed = netdev->features ^ features;
1211 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1212 	struct hnae3_handle *h = priv->ae_handle;
1213 	int ret;
1214 
1215 	if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1216 		if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
1217 			priv->ops.fill_desc = hns3_fill_desc_tso;
1218 			priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1219 		} else {
1220 			priv->ops.fill_desc = hns3_fill_desc;
1221 			priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1222 		}
1223 	}
1224 
1225 	if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1226 	    h->ae_algo->ops->enable_vlan_filter) {
1227 		if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1228 			h->ae_algo->ops->enable_vlan_filter(h, true);
1229 		else
1230 			h->ae_algo->ops->enable_vlan_filter(h, false);
1231 	}
1232 
1233 	if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1234 	    h->ae_algo->ops->enable_hw_strip_rxvtag) {
1235 		if (features & NETIF_F_HW_VLAN_CTAG_RX)
1236 			ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1237 		else
1238 			ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1239 
1240 		if (ret)
1241 			return ret;
1242 	}
1243 
1244 	netdev->features = features;
1245 	return 0;
1246 }
1247 
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)1248 static void hns3_nic_get_stats64(struct net_device *netdev,
1249 				 struct rtnl_link_stats64 *stats)
1250 {
1251 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1252 	int queue_num = priv->ae_handle->kinfo.num_tqps;
1253 	struct hnae3_handle *handle = priv->ae_handle;
1254 	struct hns3_enet_ring *ring;
1255 	unsigned int start;
1256 	unsigned int idx;
1257 	u64 tx_bytes = 0;
1258 	u64 rx_bytes = 0;
1259 	u64 tx_pkts = 0;
1260 	u64 rx_pkts = 0;
1261 	u64 tx_drop = 0;
1262 	u64 rx_drop = 0;
1263 
1264 	if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1265 		return;
1266 
1267 	handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1268 
1269 	for (idx = 0; idx < queue_num; idx++) {
1270 		/* fetch the tx stats */
1271 		ring = priv->ring_data[idx].ring;
1272 		do {
1273 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1274 			tx_bytes += ring->stats.tx_bytes;
1275 			tx_pkts += ring->stats.tx_pkts;
1276 			tx_drop += ring->stats.tx_busy;
1277 			tx_drop += ring->stats.sw_err_cnt;
1278 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1279 
1280 		/* fetch the rx stats */
1281 		ring = priv->ring_data[idx + queue_num].ring;
1282 		do {
1283 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1284 			rx_bytes += ring->stats.rx_bytes;
1285 			rx_pkts += ring->stats.rx_pkts;
1286 			rx_drop += ring->stats.non_vld_descs;
1287 			rx_drop += ring->stats.err_pkt_len;
1288 			rx_drop += ring->stats.l2_err;
1289 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1290 	}
1291 
1292 	stats->tx_bytes = tx_bytes;
1293 	stats->tx_packets = tx_pkts;
1294 	stats->rx_bytes = rx_bytes;
1295 	stats->rx_packets = rx_pkts;
1296 
1297 	stats->rx_errors = netdev->stats.rx_errors;
1298 	stats->multicast = netdev->stats.multicast;
1299 	stats->rx_length_errors = netdev->stats.rx_length_errors;
1300 	stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1301 	stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1302 
1303 	stats->tx_errors = netdev->stats.tx_errors;
1304 	stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1305 	stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
1306 	stats->collisions = netdev->stats.collisions;
1307 	stats->rx_over_errors = netdev->stats.rx_over_errors;
1308 	stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1309 	stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1310 	stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1311 	stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1312 	stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1313 	stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1314 	stats->tx_window_errors = netdev->stats.tx_window_errors;
1315 	stats->rx_compressed = netdev->stats.rx_compressed;
1316 	stats->tx_compressed = netdev->stats.tx_compressed;
1317 }
1318 
hns3_setup_tc(struct net_device * netdev,void * type_data)1319 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1320 {
1321 	struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1322 	struct hnae3_handle *h = hns3_get_handle(netdev);
1323 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
1324 	u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1325 	u8 tc = mqprio_qopt->qopt.num_tc;
1326 	u16 mode = mqprio_qopt->mode;
1327 	u8 hw = mqprio_qopt->qopt.hw;
1328 	bool if_running;
1329 	int ret;
1330 
1331 	if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1332 	       mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1333 		return -EOPNOTSUPP;
1334 
1335 	if (tc > HNAE3_MAX_TC)
1336 		return -EINVAL;
1337 
1338 	if (!netdev)
1339 		return -EINVAL;
1340 
1341 	if_running = netif_running(netdev);
1342 	if (if_running) {
1343 		hns3_nic_net_stop(netdev);
1344 		msleep(100);
1345 	}
1346 
1347 	ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1348 		kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
1349 	if (ret)
1350 		goto out;
1351 
1352 	ret = hns3_nic_set_real_num_queue(netdev);
1353 
1354 out:
1355 	if (if_running)
1356 		hns3_nic_net_open(netdev);
1357 
1358 	return ret;
1359 }
1360 
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)1361 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1362 			     void *type_data)
1363 {
1364 	if (type != TC_SETUP_QDISC_MQPRIO)
1365 		return -EOPNOTSUPP;
1366 
1367 	return hns3_setup_tc(dev, type_data);
1368 }
1369 
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)1370 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1371 				__be16 proto, u16 vid)
1372 {
1373 	struct hnae3_handle *h = hns3_get_handle(netdev);
1374 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1375 	int ret = -EIO;
1376 
1377 	if (h->ae_algo->ops->set_vlan_filter)
1378 		ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1379 
1380 	if (!ret)
1381 		set_bit(vid, priv->active_vlans);
1382 
1383 	return ret;
1384 }
1385 
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)1386 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1387 				 __be16 proto, u16 vid)
1388 {
1389 	struct hnae3_handle *h = hns3_get_handle(netdev);
1390 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1391 	int ret = -EIO;
1392 
1393 	if (h->ae_algo->ops->set_vlan_filter)
1394 		ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1395 
1396 	if (!ret)
1397 		clear_bit(vid, priv->active_vlans);
1398 
1399 	return ret;
1400 }
1401 
hns3_restore_vlan(struct net_device * netdev)1402 static void hns3_restore_vlan(struct net_device *netdev)
1403 {
1404 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1405 	u16 vid;
1406 	int ret;
1407 
1408 	for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1409 		ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1410 		if (ret)
1411 			netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n",
1412 				    vid, ret);
1413 	}
1414 }
1415 
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)1416 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1417 				u8 qos, __be16 vlan_proto)
1418 {
1419 	struct hnae3_handle *h = hns3_get_handle(netdev);
1420 	int ret = -EIO;
1421 
1422 	if (h->ae_algo->ops->set_vf_vlan_filter)
1423 		ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1424 						   qos, vlan_proto);
1425 
1426 	return ret;
1427 }
1428 
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)1429 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1430 {
1431 	struct hnae3_handle *h = hns3_get_handle(netdev);
1432 	bool if_running = netif_running(netdev);
1433 	int ret;
1434 
1435 	if (!h->ae_algo->ops->set_mtu)
1436 		return -EOPNOTSUPP;
1437 
1438 	/* if this was called with netdev up then bring netdevice down */
1439 	if (if_running) {
1440 		(void)hns3_nic_net_stop(netdev);
1441 		msleep(100);
1442 	}
1443 
1444 	ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1445 	if (ret)
1446 		netdev_err(netdev, "failed to change MTU in hardware %d\n",
1447 			   ret);
1448 	else
1449 		netdev->mtu = new_mtu;
1450 
1451 	/* if the netdev was running earlier, bring it up again */
1452 	if (if_running && hns3_nic_net_open(netdev))
1453 		ret = -EINVAL;
1454 
1455 	return ret;
1456 }
1457 
hns3_get_tx_timeo_queue_info(struct net_device * ndev)1458 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1459 {
1460 	struct hns3_nic_priv *priv = netdev_priv(ndev);
1461 	struct hns3_enet_ring *tx_ring = NULL;
1462 	int timeout_queue = 0;
1463 	int hw_head, hw_tail;
1464 	int i;
1465 
1466 	/* Find the stopped queue the same way the stack does */
1467 	for (i = 0; i < ndev->num_tx_queues; i++) {
1468 		struct netdev_queue *q;
1469 		unsigned long trans_start;
1470 
1471 		q = netdev_get_tx_queue(ndev, i);
1472 		trans_start = q->trans_start;
1473 		if (netif_xmit_stopped(q) &&
1474 		    time_after(jiffies,
1475 			       (trans_start + ndev->watchdog_timeo))) {
1476 			timeout_queue = i;
1477 			netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1478 				    q->state,
1479 				    jiffies_to_msecs(jiffies - trans_start));
1480 			break;
1481 		}
1482 	}
1483 
1484 	if (i == ndev->num_tx_queues) {
1485 		netdev_info(ndev,
1486 			    "no netdev TX timeout queue found, timeout count: %llu\n",
1487 			    priv->tx_timeout_count);
1488 		return false;
1489 	}
1490 
1491 	tx_ring = priv->ring_data[timeout_queue].ring;
1492 
1493 	hw_head = readl_relaxed(tx_ring->tqp->io_base +
1494 				HNS3_RING_TX_RING_HEAD_REG);
1495 	hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1496 				HNS3_RING_TX_RING_TAIL_REG);
1497 	netdev_info(ndev,
1498 		    "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1499 		    priv->tx_timeout_count,
1500 		    timeout_queue,
1501 		    tx_ring->next_to_use,
1502 		    tx_ring->next_to_clean,
1503 		    hw_head,
1504 		    hw_tail,
1505 		    readl(tx_ring->tqp_vector->mask_addr));
1506 
1507 	return true;
1508 }
1509 
hns3_nic_net_timeout(struct net_device * ndev)1510 static void hns3_nic_net_timeout(struct net_device *ndev)
1511 {
1512 	struct hns3_nic_priv *priv = netdev_priv(ndev);
1513 	struct hnae3_handle *h = priv->ae_handle;
1514 
1515 	if (!hns3_get_tx_timeo_queue_info(ndev))
1516 		return;
1517 
1518 	priv->tx_timeout_count++;
1519 
1520 	if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo)))
1521 		return;
1522 
1523 	/* request the reset */
1524 	if (h->ae_algo->ops->reset_event)
1525 		h->ae_algo->ops->reset_event(h);
1526 }
1527 
1528 static const struct net_device_ops hns3_nic_netdev_ops = {
1529 	.ndo_open		= hns3_nic_net_open,
1530 	.ndo_stop		= hns3_nic_net_stop,
1531 	.ndo_start_xmit		= hns3_nic_net_xmit,
1532 	.ndo_tx_timeout		= hns3_nic_net_timeout,
1533 	.ndo_set_mac_address	= hns3_nic_net_set_mac_address,
1534 	.ndo_change_mtu		= hns3_nic_change_mtu,
1535 	.ndo_set_features	= hns3_nic_set_features,
1536 	.ndo_get_stats64	= hns3_nic_get_stats64,
1537 	.ndo_setup_tc		= hns3_nic_setup_tc,
1538 	.ndo_set_rx_mode	= hns3_nic_set_rx_mode,
1539 	.ndo_vlan_rx_add_vid	= hns3_vlan_rx_add_vid,
1540 	.ndo_vlan_rx_kill_vid	= hns3_vlan_rx_kill_vid,
1541 	.ndo_set_vf_vlan	= hns3_ndo_set_vf_vlan,
1542 };
1543 
hns3_is_phys_func(struct pci_dev * pdev)1544 static bool hns3_is_phys_func(struct pci_dev *pdev)
1545 {
1546 	u32 dev_id = pdev->device;
1547 
1548 	switch (dev_id) {
1549 	case HNAE3_DEV_ID_GE:
1550 	case HNAE3_DEV_ID_25GE:
1551 	case HNAE3_DEV_ID_25GE_RDMA:
1552 	case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1553 	case HNAE3_DEV_ID_50GE_RDMA:
1554 	case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1555 	case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1556 		return true;
1557 	case HNAE3_DEV_ID_100G_VF:
1558 	case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1559 		return false;
1560 	default:
1561 		dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1562 			 dev_id);
1563 	}
1564 
1565 	return false;
1566 }
1567 
hns3_disable_sriov(struct pci_dev * pdev)1568 static void hns3_disable_sriov(struct pci_dev *pdev)
1569 {
1570 	/* If our VFs are assigned we cannot shut down SR-IOV
1571 	 * without causing issues, so just leave the hardware
1572 	 * available but disabled
1573 	 */
1574 	if (pci_vfs_assigned(pdev)) {
1575 		dev_warn(&pdev->dev,
1576 			 "disabling driver while VFs are assigned\n");
1577 		return;
1578 	}
1579 
1580 	pci_disable_sriov(pdev);
1581 }
1582 
1583 /* hns3_probe - Device initialization routine
1584  * @pdev: PCI device information struct
1585  * @ent: entry in hns3_pci_tbl
1586  *
1587  * hns3_probe initializes a PF identified by a pci_dev structure.
1588  * The OS initialization, configuring of the PF private structure,
1589  * and a hardware reset occur.
1590  *
1591  * Returns 0 on success, negative on failure
1592  */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1593 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1594 {
1595 	struct hnae3_ae_dev *ae_dev;
1596 	int ret;
1597 
1598 	ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1599 			      GFP_KERNEL);
1600 	if (!ae_dev) {
1601 		ret = -ENOMEM;
1602 		return ret;
1603 	}
1604 
1605 	ae_dev->pdev = pdev;
1606 	ae_dev->flag = ent->driver_data;
1607 	ae_dev->dev_type = HNAE3_DEV_KNIC;
1608 	pci_set_drvdata(pdev, ae_dev);
1609 
1610 	ret = hnae3_register_ae_dev(ae_dev);
1611 	if (ret) {
1612 		devm_kfree(&pdev->dev, ae_dev);
1613 		pci_set_drvdata(pdev, NULL);
1614 	}
1615 
1616 	return ret;
1617 }
1618 
1619 /* hns3_remove - Device removal routine
1620  * @pdev: PCI device information struct
1621  */
hns3_remove(struct pci_dev * pdev)1622 static void hns3_remove(struct pci_dev *pdev)
1623 {
1624 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1625 
1626 	if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1627 		hns3_disable_sriov(pdev);
1628 
1629 	hnae3_unregister_ae_dev(ae_dev);
1630 	pci_set_drvdata(pdev, NULL);
1631 }
1632 
1633 /**
1634  * hns3_pci_sriov_configure
1635  * @pdev: pointer to a pci_dev structure
1636  * @num_vfs: number of VFs to allocate
1637  *
1638  * Enable or change the number of VFs. Called when the user updates the number
1639  * of VFs in sysfs.
1640  **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)1641 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
1642 {
1643 	int ret;
1644 
1645 	if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1646 		dev_warn(&pdev->dev, "Can not config SRIOV\n");
1647 		return -EINVAL;
1648 	}
1649 
1650 	if (num_vfs) {
1651 		ret = pci_enable_sriov(pdev, num_vfs);
1652 		if (ret)
1653 			dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
1654 		else
1655 			return num_vfs;
1656 	} else if (!pci_vfs_assigned(pdev)) {
1657 		pci_disable_sriov(pdev);
1658 	} else {
1659 		dev_warn(&pdev->dev,
1660 			 "Unable to free VFs because some are assigned to VMs.\n");
1661 	}
1662 
1663 	return 0;
1664 }
1665 
1666 static struct pci_driver hns3_driver = {
1667 	.name     = hns3_driver_name,
1668 	.id_table = hns3_pci_tbl,
1669 	.probe    = hns3_probe,
1670 	.remove   = hns3_remove,
1671 	.sriov_configure = hns3_pci_sriov_configure,
1672 };
1673 
1674 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)1675 static void hns3_set_default_feature(struct net_device *netdev)
1676 {
1677 	struct hnae3_handle *h = hns3_get_handle(netdev);
1678 	struct pci_dev *pdev = h->pdev;
1679 
1680 	netdev->priv_flags |= IFF_UNICAST_FLT;
1681 
1682 	netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1683 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1684 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1685 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1686 		NETIF_F_GSO_UDP_TUNNEL_CSUM;
1687 
1688 	netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1689 
1690 	netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1691 
1692 	netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1693 		NETIF_F_HW_VLAN_CTAG_FILTER |
1694 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1695 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1696 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1697 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1698 		NETIF_F_GSO_UDP_TUNNEL_CSUM;
1699 
1700 	netdev->vlan_features |=
1701 		NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1702 		NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1703 		NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1704 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1705 		NETIF_F_GSO_UDP_TUNNEL_CSUM;
1706 
1707 	netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1708 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1709 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1710 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1711 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1712 		NETIF_F_GSO_UDP_TUNNEL_CSUM;
1713 
1714 	if (pdev->revision != 0x20)
1715 		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1716 }
1717 
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1718 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1719 			     struct hns3_desc_cb *cb)
1720 {
1721 	unsigned int order = hnae3_page_order(ring);
1722 	struct page *p;
1723 
1724 	p = dev_alloc_pages(order);
1725 	if (!p)
1726 		return -ENOMEM;
1727 
1728 	cb->priv = p;
1729 	cb->page_offset = 0;
1730 	cb->reuse_flag = 0;
1731 	cb->buf  = page_address(p);
1732 	cb->length = hnae3_page_size(ring);
1733 	cb->type = DESC_TYPE_PAGE;
1734 
1735 	return 0;
1736 }
1737 
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1738 static void hns3_free_buffer(struct hns3_enet_ring *ring,
1739 			     struct hns3_desc_cb *cb)
1740 {
1741 	if (cb->type == DESC_TYPE_SKB)
1742 		dev_kfree_skb_any((struct sk_buff *)cb->priv);
1743 	else if (!HNAE3_IS_TX_RING(ring))
1744 		put_page((struct page *)cb->priv);
1745 	memset(cb, 0, sizeof(*cb));
1746 }
1747 
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1748 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1749 {
1750 	cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1751 			       cb->length, ring_to_dma_dir(ring));
1752 
1753 	if (dma_mapping_error(ring_to_dev(ring), cb->dma))
1754 		return -EIO;
1755 
1756 	return 0;
1757 }
1758 
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1759 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1760 			      struct hns3_desc_cb *cb)
1761 {
1762 	if (cb->type == DESC_TYPE_SKB)
1763 		dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1764 				 ring_to_dma_dir(ring));
1765 	else
1766 		dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1767 			       ring_to_dma_dir(ring));
1768 }
1769 
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)1770 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1771 {
1772 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1773 	ring->desc[i].addr = 0;
1774 }
1775 
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i)1776 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
1777 {
1778 	struct hns3_desc_cb *cb = &ring->desc_cb[i];
1779 
1780 	if (!ring->desc_cb[i].dma)
1781 		return;
1782 
1783 	hns3_buffer_detach(ring, i);
1784 	hns3_free_buffer(ring, cb);
1785 }
1786 
hns3_free_buffers(struct hns3_enet_ring * ring)1787 static void hns3_free_buffers(struct hns3_enet_ring *ring)
1788 {
1789 	int i;
1790 
1791 	for (i = 0; i < ring->desc_num; i++)
1792 		hns3_free_buffer_detach(ring, i);
1793 }
1794 
1795 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)1796 static void hns3_free_desc(struct hns3_enet_ring *ring)
1797 {
1798 	int size = ring->desc_num * sizeof(ring->desc[0]);
1799 
1800 	hns3_free_buffers(ring);
1801 
1802 	if (ring->desc) {
1803 		dma_free_coherent(ring_to_dev(ring), size,
1804 				  ring->desc, ring->desc_dma_addr);
1805 		ring->desc = NULL;
1806 	}
1807 }
1808 
hns3_alloc_desc(struct hns3_enet_ring * ring)1809 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
1810 {
1811 	int size = ring->desc_num * sizeof(ring->desc[0]);
1812 
1813 	ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
1814 					 &ring->desc_dma_addr,
1815 					 GFP_KERNEL);
1816 	if (!ring->desc)
1817 		return -ENOMEM;
1818 
1819 	return 0;
1820 }
1821 
hns3_reserve_buffer_map(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1822 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
1823 				   struct hns3_desc_cb *cb)
1824 {
1825 	int ret;
1826 
1827 	ret = hns3_alloc_buffer(ring, cb);
1828 	if (ret)
1829 		goto out;
1830 
1831 	ret = hns3_map_buffer(ring, cb);
1832 	if (ret)
1833 		goto out_with_buf;
1834 
1835 	return 0;
1836 
1837 out_with_buf:
1838 	hns3_free_buffer(ring, cb);
1839 out:
1840 	return ret;
1841 }
1842 
hns3_alloc_buffer_attach(struct hns3_enet_ring * ring,int i)1843 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
1844 {
1845 	int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
1846 
1847 	if (ret)
1848 		return ret;
1849 
1850 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1851 
1852 	return 0;
1853 }
1854 
1855 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)1856 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
1857 {
1858 	int i, j, ret;
1859 
1860 	for (i = 0; i < ring->desc_num; i++) {
1861 		ret = hns3_alloc_buffer_attach(ring, i);
1862 		if (ret)
1863 			goto out_buffer_fail;
1864 	}
1865 
1866 	return 0;
1867 
1868 out_buffer_fail:
1869 	for (j = i - 1; j >= 0; j--)
1870 		hns3_free_buffer_detach(ring, j);
1871 	return ret;
1872 }
1873 
1874 /* detach a in-used buffer and replace with a reserved one  */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)1875 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
1876 				struct hns3_desc_cb *res_cb)
1877 {
1878 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1879 	ring->desc_cb[i] = *res_cb;
1880 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1881 	ring->desc[i].rx.bd_base_info = 0;
1882 }
1883 
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)1884 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
1885 {
1886 	ring->desc_cb[i].reuse_flag = 0;
1887 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
1888 		+ ring->desc_cb[i].page_offset);
1889 	ring->desc[i].rx.bd_base_info = 0;
1890 }
1891 
hns3_nic_reclaim_one_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts)1892 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
1893 				      int *pkts)
1894 {
1895 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
1896 
1897 	(*pkts) += (desc_cb->type == DESC_TYPE_SKB);
1898 	(*bytes) += desc_cb->length;
1899 	/* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
1900 	hns3_free_buffer_detach(ring, ring->next_to_clean);
1901 
1902 	ring_ptr_move_fw(ring, next_to_clean);
1903 }
1904 
is_valid_clean_head(struct hns3_enet_ring * ring,int h)1905 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
1906 {
1907 	int u = ring->next_to_use;
1908 	int c = ring->next_to_clean;
1909 
1910 	if (unlikely(h > ring->desc_num))
1911 		return 0;
1912 
1913 	return u > c ? (h > c && h <= u) : (h > c || h <= u);
1914 }
1915 
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)1916 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
1917 {
1918 	struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
1919 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1920 	struct netdev_queue *dev_queue;
1921 	int bytes, pkts;
1922 	int head;
1923 
1924 	head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
1925 	rmb(); /* Make sure head is ready before touch any data */
1926 
1927 	if (is_ring_empty(ring) || head == ring->next_to_clean)
1928 		return true; /* no data to poll */
1929 
1930 	if (unlikely(!is_valid_clean_head(ring, head))) {
1931 		netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
1932 			   ring->next_to_use, ring->next_to_clean);
1933 
1934 		u64_stats_update_begin(&ring->syncp);
1935 		ring->stats.io_err_cnt++;
1936 		u64_stats_update_end(&ring->syncp);
1937 		return true;
1938 	}
1939 
1940 	bytes = 0;
1941 	pkts = 0;
1942 	while (head != ring->next_to_clean && budget) {
1943 		hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
1944 		/* Issue prefetch for next Tx descriptor */
1945 		prefetch(&ring->desc_cb[ring->next_to_clean]);
1946 		budget--;
1947 	}
1948 
1949 	ring->tqp_vector->tx_group.total_bytes += bytes;
1950 	ring->tqp_vector->tx_group.total_packets += pkts;
1951 
1952 	u64_stats_update_begin(&ring->syncp);
1953 	ring->stats.tx_bytes += bytes;
1954 	ring->stats.tx_pkts += pkts;
1955 	u64_stats_update_end(&ring->syncp);
1956 
1957 	dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
1958 	netdev_tx_completed_queue(dev_queue, pkts, bytes);
1959 
1960 	if (unlikely(pkts && netif_carrier_ok(netdev) &&
1961 		     (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
1962 		/* Make sure that anybody stopping the queue after this
1963 		 * sees the new next_to_clean.
1964 		 */
1965 		smp_mb();
1966 		if (netif_tx_queue_stopped(dev_queue) &&
1967 		    !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1968 			netif_tx_wake_queue(dev_queue);
1969 			ring->stats.restart_queue++;
1970 		}
1971 	}
1972 
1973 	return !!budget;
1974 }
1975 
hns3_desc_unused(struct hns3_enet_ring * ring)1976 static int hns3_desc_unused(struct hns3_enet_ring *ring)
1977 {
1978 	int ntc = ring->next_to_clean;
1979 	int ntu = ring->next_to_use;
1980 
1981 	return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
1982 }
1983 
1984 static void
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)1985 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
1986 {
1987 	struct hns3_desc_cb *desc_cb;
1988 	struct hns3_desc_cb res_cbs;
1989 	int i, ret;
1990 
1991 	for (i = 0; i < cleand_count; i++) {
1992 		desc_cb = &ring->desc_cb[ring->next_to_use];
1993 		if (desc_cb->reuse_flag) {
1994 			u64_stats_update_begin(&ring->syncp);
1995 			ring->stats.reuse_pg_cnt++;
1996 			u64_stats_update_end(&ring->syncp);
1997 
1998 			hns3_reuse_buffer(ring, ring->next_to_use);
1999 		} else {
2000 			ret = hns3_reserve_buffer_map(ring, &res_cbs);
2001 			if (ret) {
2002 				u64_stats_update_begin(&ring->syncp);
2003 				ring->stats.sw_err_cnt++;
2004 				u64_stats_update_end(&ring->syncp);
2005 
2006 				netdev_err(ring->tqp->handle->kinfo.netdev,
2007 					   "hnae reserve buffer map failed.\n");
2008 				break;
2009 			}
2010 			hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2011 		}
2012 
2013 		ring_ptr_move_fw(ring, next_to_use);
2014 	}
2015 
2016 	wmb(); /* Make all data has been write before submit */
2017 	writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2018 }
2019 
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)2020 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2021 				struct hns3_enet_ring *ring, int pull_len,
2022 				struct hns3_desc_cb *desc_cb)
2023 {
2024 	struct hns3_desc *desc;
2025 	u32 truesize;
2026 	int size;
2027 	int last_offset;
2028 	bool twobufs;
2029 
2030 	twobufs = ((PAGE_SIZE < 8192) &&
2031 		hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
2032 
2033 	desc = &ring->desc[ring->next_to_clean];
2034 	size = le16_to_cpu(desc->rx.size);
2035 
2036 	truesize = hnae3_buf_size(ring);
2037 
2038 	if (!twobufs)
2039 		last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
2040 
2041 	skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2042 			size - pull_len, truesize);
2043 
2044 	 /* Avoid re-using remote pages,flag default unreuse */
2045 	if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2046 		return;
2047 
2048 	if (twobufs) {
2049 		/* If we are only owner of page we can reuse it */
2050 		if (likely(page_count(desc_cb->priv) == 1)) {
2051 			/* Flip page offset to other buffer */
2052 			desc_cb->page_offset ^= truesize;
2053 
2054 			desc_cb->reuse_flag = 1;
2055 			/* bump ref count on page before it is given*/
2056 			get_page(desc_cb->priv);
2057 		}
2058 		return;
2059 	}
2060 
2061 	/* Move offset up to the next cache line */
2062 	desc_cb->page_offset += truesize;
2063 
2064 	if (desc_cb->page_offset <= last_offset) {
2065 		desc_cb->reuse_flag = 1;
2066 		/* Bump ref count on page before it is given*/
2067 		get_page(desc_cb->priv);
2068 	}
2069 }
2070 
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc)2071 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2072 			     struct hns3_desc *desc)
2073 {
2074 	struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2075 	int l3_type, l4_type;
2076 	u32 bd_base_info;
2077 	int ol4_type;
2078 	u32 l234info;
2079 
2080 	bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2081 	l234info = le32_to_cpu(desc->rx.l234_info);
2082 
2083 	skb->ip_summed = CHECKSUM_NONE;
2084 
2085 	skb_checksum_none_assert(skb);
2086 
2087 	if (!(netdev->features & NETIF_F_RXCSUM))
2088 		return;
2089 
2090 	/* check if hardware has done checksum */
2091 	if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
2092 		return;
2093 
2094 	if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2095 		     hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2096 		     hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2097 		     hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
2098 		netdev_err(netdev, "L3/L4 error pkt\n");
2099 		u64_stats_update_begin(&ring->syncp);
2100 		ring->stats.l3l4_csum_err++;
2101 		u64_stats_update_end(&ring->syncp);
2102 
2103 		return;
2104 	}
2105 
2106 	l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2107 				  HNS3_RXD_L3ID_S);
2108 	l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2109 				  HNS3_RXD_L4ID_S);
2110 
2111 	ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2112 				   HNS3_RXD_OL4ID_S);
2113 	switch (ol4_type) {
2114 	case HNS3_OL4_TYPE_MAC_IN_UDP:
2115 	case HNS3_OL4_TYPE_NVGRE:
2116 		skb->csum_level = 1;
2117 		/* fall through */
2118 	case HNS3_OL4_TYPE_NO_TUN:
2119 		/* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2120 		if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2121 		     l3_type == HNS3_L3_TYPE_IPV6) &&
2122 		    (l4_type == HNS3_L4_TYPE_UDP ||
2123 		     l4_type == HNS3_L4_TYPE_TCP ||
2124 		     l4_type == HNS3_L4_TYPE_SCTP))
2125 			skb->ip_summed = CHECKSUM_UNNECESSARY;
2126 		break;
2127 	}
2128 }
2129 
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)2130 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2131 {
2132 	napi_gro_receive(&ring->tqp_vector->napi, skb);
2133 }
2134 
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)2135 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2136 				struct hns3_desc *desc, u32 l234info,
2137 				u16 *vlan_tag)
2138 {
2139 	struct pci_dev *pdev = ring->tqp->handle->pdev;
2140 
2141 	if (pdev->revision == 0x20) {
2142 		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2143 		if (!(*vlan_tag & VLAN_VID_MASK))
2144 			*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2145 
2146 		return (*vlan_tag != 0);
2147 	}
2148 
2149 #define HNS3_STRP_OUTER_VLAN	0x1
2150 #define HNS3_STRP_INNER_VLAN	0x2
2151 
2152 	switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2153 				HNS3_RXD_STRP_TAGP_S)) {
2154 	case HNS3_STRP_OUTER_VLAN:
2155 		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2156 		return true;
2157 	case HNS3_STRP_INNER_VLAN:
2158 		*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2159 		return true;
2160 	default:
2161 		return false;
2162 	}
2163 }
2164 
hns3_handle_rx_bd(struct hns3_enet_ring * ring,struct sk_buff ** out_skb,int * out_bnum)2165 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2166 			     struct sk_buff **out_skb, int *out_bnum)
2167 {
2168 	struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2169 	struct hns3_desc_cb *desc_cb;
2170 	struct hns3_desc *desc;
2171 	struct sk_buff *skb;
2172 	unsigned char *va;
2173 	u32 bd_base_info;
2174 	int pull_len;
2175 	u32 l234info;
2176 	int length;
2177 	int bnum;
2178 
2179 	desc = &ring->desc[ring->next_to_clean];
2180 	desc_cb = &ring->desc_cb[ring->next_to_clean];
2181 
2182 	prefetch(desc);
2183 
2184 	length = le16_to_cpu(desc->rx.size);
2185 	bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2186 
2187 	/* Check valid BD */
2188 	if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
2189 		return -EFAULT;
2190 
2191 	va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2192 
2193 	/* Prefetch first cache line of first page
2194 	 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2195 	 * line size is 64B so need to prefetch twice to make it 128B. But in
2196 	 * actual we can have greater size of caches with 128B Level 1 cache
2197 	 * lines. In such a case, single fetch would suffice to cache in the
2198 	 * relevant part of the header.
2199 	 */
2200 	prefetch(va);
2201 #if L1_CACHE_BYTES < 128
2202 	prefetch(va + L1_CACHE_BYTES);
2203 #endif
2204 
2205 	skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2206 					HNS3_RX_HEAD_SIZE);
2207 	if (unlikely(!skb)) {
2208 		netdev_err(netdev, "alloc rx skb fail\n");
2209 
2210 		u64_stats_update_begin(&ring->syncp);
2211 		ring->stats.sw_err_cnt++;
2212 		u64_stats_update_end(&ring->syncp);
2213 
2214 		return -ENOMEM;
2215 	}
2216 
2217 	prefetchw(skb->data);
2218 
2219 	bnum = 1;
2220 	if (length <= HNS3_RX_HEAD_SIZE) {
2221 		memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2222 
2223 		/* We can reuse buffer as-is, just make sure it is local */
2224 		if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2225 			desc_cb->reuse_flag = 1;
2226 		else /* This page cannot be reused so discard it */
2227 			put_page(desc_cb->priv);
2228 
2229 		ring_ptr_move_fw(ring, next_to_clean);
2230 	} else {
2231 		u64_stats_update_begin(&ring->syncp);
2232 		ring->stats.seg_pkt_cnt++;
2233 		u64_stats_update_end(&ring->syncp);
2234 
2235 		pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2236 
2237 		memcpy(__skb_put(skb, pull_len), va,
2238 		       ALIGN(pull_len, sizeof(long)));
2239 
2240 		hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb);
2241 		ring_ptr_move_fw(ring, next_to_clean);
2242 
2243 		while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2244 			desc = &ring->desc[ring->next_to_clean];
2245 			desc_cb = &ring->desc_cb[ring->next_to_clean];
2246 			bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2247 			hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb);
2248 			ring_ptr_move_fw(ring, next_to_clean);
2249 			bnum++;
2250 		}
2251 	}
2252 
2253 	*out_bnum = bnum;
2254 
2255 	l234info = le32_to_cpu(desc->rx.l234_info);
2256 
2257 	/* Based on hw strategy, the tag offloaded will be stored at
2258 	 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2259 	 * in one layer tag case.
2260 	 */
2261 	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2262 		u16 vlan_tag;
2263 
2264 		if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2265 			__vlan_hwaccel_put_tag(skb,
2266 					       htons(ETH_P_8021Q),
2267 					       vlan_tag);
2268 	}
2269 
2270 	if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
2271 		netdev_err(netdev, "no valid bd,%016llx,%016llx\n",
2272 			   ((u64 *)desc)[0], ((u64 *)desc)[1]);
2273 		u64_stats_update_begin(&ring->syncp);
2274 		ring->stats.non_vld_descs++;
2275 		u64_stats_update_end(&ring->syncp);
2276 
2277 		dev_kfree_skb_any(skb);
2278 		return -EINVAL;
2279 	}
2280 
2281 	if (unlikely((!desc->rx.pkt_len) ||
2282 		     hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
2283 		netdev_err(netdev, "truncated pkt\n");
2284 		u64_stats_update_begin(&ring->syncp);
2285 		ring->stats.err_pkt_len++;
2286 		u64_stats_update_end(&ring->syncp);
2287 
2288 		dev_kfree_skb_any(skb);
2289 		return -EFAULT;
2290 	}
2291 
2292 	if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
2293 		netdev_err(netdev, "L2 error pkt\n");
2294 		u64_stats_update_begin(&ring->syncp);
2295 		ring->stats.l2_err++;
2296 		u64_stats_update_end(&ring->syncp);
2297 
2298 		dev_kfree_skb_any(skb);
2299 		return -EFAULT;
2300 	}
2301 
2302 	u64_stats_update_begin(&ring->syncp);
2303 	ring->stats.rx_pkts++;
2304 	ring->stats.rx_bytes += skb->len;
2305 	u64_stats_update_end(&ring->syncp);
2306 
2307 	ring->tqp_vector->rx_group.total_bytes += skb->len;
2308 
2309 	hns3_rx_checksum(ring, skb, desc);
2310 	return 0;
2311 }
2312 
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))2313 int hns3_clean_rx_ring(
2314 		struct hns3_enet_ring *ring, int budget,
2315 		void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
2316 {
2317 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2318 	struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2319 	int recv_pkts, recv_bds, clean_count, err;
2320 	int unused_count = hns3_desc_unused(ring);
2321 	struct sk_buff *skb = NULL;
2322 	int num, bnum = 0;
2323 
2324 	num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2325 	rmb(); /* Make sure num taken effect before the other data is touched */
2326 
2327 	recv_pkts = 0, recv_bds = 0, clean_count = 0;
2328 	num -= unused_count;
2329 
2330 	while (recv_pkts < budget && recv_bds < num) {
2331 		/* Reuse or realloc buffers */
2332 		if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2333 			hns3_nic_alloc_rx_buffers(ring,
2334 						  clean_count + unused_count);
2335 			clean_count = 0;
2336 			unused_count = hns3_desc_unused(ring);
2337 		}
2338 
2339 		/* Poll one pkt */
2340 		err = hns3_handle_rx_bd(ring, &skb, &bnum);
2341 		if (unlikely(!skb)) /* This fault cannot be repaired */
2342 			goto out;
2343 
2344 		recv_bds += bnum;
2345 		clean_count += bnum;
2346 		if (unlikely(err)) {  /* Do jump the err */
2347 			recv_pkts++;
2348 			continue;
2349 		}
2350 
2351 		/* Do update ip stack process */
2352 		skb->protocol = eth_type_trans(skb, netdev);
2353 		rx_fn(ring, skb);
2354 
2355 		recv_pkts++;
2356 	}
2357 
2358 out:
2359 	/* Make all data has been write before submit */
2360 	if (clean_count + unused_count > 0)
2361 		hns3_nic_alloc_rx_buffers(ring,
2362 					  clean_count + unused_count);
2363 
2364 	return recv_pkts;
2365 }
2366 
hns3_get_new_int_gl(struct hns3_enet_ring_group * ring_group)2367 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2368 {
2369 	struct hns3_enet_tqp_vector *tqp_vector =
2370 					ring_group->ring->tqp_vector;
2371 	enum hns3_flow_level_range new_flow_level;
2372 	int packets_per_msecs;
2373 	int bytes_per_msecs;
2374 	u32 time_passed_ms;
2375 	u16 new_int_gl;
2376 
2377 	if (!tqp_vector->last_jiffies)
2378 		return false;
2379 
2380 	if (ring_group->total_packets == 0) {
2381 		ring_group->coal.int_gl = HNS3_INT_GL_50K;
2382 		ring_group->coal.flow_level = HNS3_FLOW_LOW;
2383 		return true;
2384 	}
2385 
2386 	/* Simple throttlerate management
2387 	 * 0-10MB/s   lower     (50000 ints/s)
2388 	 * 10-20MB/s   middle    (20000 ints/s)
2389 	 * 20-1249MB/s high      (18000 ints/s)
2390 	 * > 40000pps  ultra     (8000 ints/s)
2391 	 */
2392 	new_flow_level = ring_group->coal.flow_level;
2393 	new_int_gl = ring_group->coal.int_gl;
2394 	time_passed_ms =
2395 		jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2396 
2397 	if (!time_passed_ms)
2398 		return false;
2399 
2400 	do_div(ring_group->total_packets, time_passed_ms);
2401 	packets_per_msecs = ring_group->total_packets;
2402 
2403 	do_div(ring_group->total_bytes, time_passed_ms);
2404 	bytes_per_msecs = ring_group->total_bytes;
2405 
2406 #define HNS3_RX_LOW_BYTE_RATE 10000
2407 #define HNS3_RX_MID_BYTE_RATE 20000
2408 
2409 	switch (new_flow_level) {
2410 	case HNS3_FLOW_LOW:
2411 		if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
2412 			new_flow_level = HNS3_FLOW_MID;
2413 		break;
2414 	case HNS3_FLOW_MID:
2415 		if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
2416 			new_flow_level = HNS3_FLOW_HIGH;
2417 		else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
2418 			new_flow_level = HNS3_FLOW_LOW;
2419 		break;
2420 	case HNS3_FLOW_HIGH:
2421 	case HNS3_FLOW_ULTRA:
2422 	default:
2423 		if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
2424 			new_flow_level = HNS3_FLOW_MID;
2425 		break;
2426 	}
2427 
2428 #define HNS3_RX_ULTRA_PACKET_RATE 40
2429 
2430 	if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2431 	    &tqp_vector->rx_group == ring_group)
2432 		new_flow_level = HNS3_FLOW_ULTRA;
2433 
2434 	switch (new_flow_level) {
2435 	case HNS3_FLOW_LOW:
2436 		new_int_gl = HNS3_INT_GL_50K;
2437 		break;
2438 	case HNS3_FLOW_MID:
2439 		new_int_gl = HNS3_INT_GL_20K;
2440 		break;
2441 	case HNS3_FLOW_HIGH:
2442 		new_int_gl = HNS3_INT_GL_18K;
2443 		break;
2444 	case HNS3_FLOW_ULTRA:
2445 		new_int_gl = HNS3_INT_GL_8K;
2446 		break;
2447 	default:
2448 		break;
2449 	}
2450 
2451 	ring_group->total_bytes = 0;
2452 	ring_group->total_packets = 0;
2453 	ring_group->coal.flow_level = new_flow_level;
2454 	if (new_int_gl != ring_group->coal.int_gl) {
2455 		ring_group->coal.int_gl = new_int_gl;
2456 		return true;
2457 	}
2458 	return false;
2459 }
2460 
hns3_update_new_int_gl(struct hns3_enet_tqp_vector * tqp_vector)2461 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2462 {
2463 	struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2464 	struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2465 	bool rx_update, tx_update;
2466 
2467 	if (tqp_vector->int_adapt_down > 0) {
2468 		tqp_vector->int_adapt_down--;
2469 		return;
2470 	}
2471 
2472 	if (rx_group->coal.gl_adapt_enable) {
2473 		rx_update = hns3_get_new_int_gl(rx_group);
2474 		if (rx_update)
2475 			hns3_set_vector_coalesce_rx_gl(tqp_vector,
2476 						       rx_group->coal.int_gl);
2477 	}
2478 
2479 	if (tx_group->coal.gl_adapt_enable) {
2480 		tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2481 		if (tx_update)
2482 			hns3_set_vector_coalesce_tx_gl(tqp_vector,
2483 						       tx_group->coal.int_gl);
2484 	}
2485 
2486 	tqp_vector->last_jiffies = jiffies;
2487 	tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
2488 }
2489 
hns3_nic_common_poll(struct napi_struct * napi,int budget)2490 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2491 {
2492 	struct hns3_enet_ring *ring;
2493 	int rx_pkt_total = 0;
2494 
2495 	struct hns3_enet_tqp_vector *tqp_vector =
2496 		container_of(napi, struct hns3_enet_tqp_vector, napi);
2497 	bool clean_complete = true;
2498 	int rx_budget;
2499 
2500 	/* Since the actual Tx work is minimal, we can give the Tx a larger
2501 	 * budget and be more aggressive about cleaning up the Tx descriptors.
2502 	 */
2503 	hns3_for_each_ring(ring, tqp_vector->tx_group) {
2504 		if (!hns3_clean_tx_ring(ring, budget))
2505 			clean_complete = false;
2506 	}
2507 
2508 	/* make sure rx ring budget not smaller than 1 */
2509 	rx_budget = max(budget / tqp_vector->num_tqps, 1);
2510 
2511 	hns3_for_each_ring(ring, tqp_vector->rx_group) {
2512 		int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2513 						    hns3_rx_skb);
2514 
2515 		if (rx_cleaned >= rx_budget)
2516 			clean_complete = false;
2517 
2518 		rx_pkt_total += rx_cleaned;
2519 	}
2520 
2521 	tqp_vector->rx_group.total_packets += rx_pkt_total;
2522 
2523 	if (!clean_complete)
2524 		return budget;
2525 
2526 	napi_complete(napi);
2527 	hns3_update_new_int_gl(tqp_vector);
2528 	hns3_mask_vector_irq(tqp_vector, 1);
2529 
2530 	return rx_pkt_total;
2531 }
2532 
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)2533 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2534 				      struct hnae3_ring_chain_node *head)
2535 {
2536 	struct pci_dev *pdev = tqp_vector->handle->pdev;
2537 	struct hnae3_ring_chain_node *cur_chain = head;
2538 	struct hnae3_ring_chain_node *chain;
2539 	struct hns3_enet_ring *tx_ring;
2540 	struct hns3_enet_ring *rx_ring;
2541 
2542 	tx_ring = tqp_vector->tx_group.ring;
2543 	if (tx_ring) {
2544 		cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2545 		hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2546 			      HNAE3_RING_TYPE_TX);
2547 		hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2548 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
2549 
2550 		cur_chain->next = NULL;
2551 
2552 		while (tx_ring->next) {
2553 			tx_ring = tx_ring->next;
2554 
2555 			chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2556 					     GFP_KERNEL);
2557 			if (!chain)
2558 				goto err_free_chain;
2559 
2560 			cur_chain->next = chain;
2561 			chain->tqp_index = tx_ring->tqp->tqp_index;
2562 			hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2563 				      HNAE3_RING_TYPE_TX);
2564 			hnae3_set_field(chain->int_gl_idx,
2565 					HNAE3_RING_GL_IDX_M,
2566 					HNAE3_RING_GL_IDX_S,
2567 					HNAE3_RING_GL_TX);
2568 
2569 			cur_chain = chain;
2570 		}
2571 	}
2572 
2573 	rx_ring = tqp_vector->rx_group.ring;
2574 	if (!tx_ring && rx_ring) {
2575 		cur_chain->next = NULL;
2576 		cur_chain->tqp_index = rx_ring->tqp->tqp_index;
2577 		hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2578 			      HNAE3_RING_TYPE_RX);
2579 		hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2580 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2581 
2582 		rx_ring = rx_ring->next;
2583 	}
2584 
2585 	while (rx_ring) {
2586 		chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2587 		if (!chain)
2588 			goto err_free_chain;
2589 
2590 		cur_chain->next = chain;
2591 		chain->tqp_index = rx_ring->tqp->tqp_index;
2592 		hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2593 			      HNAE3_RING_TYPE_RX);
2594 		hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2595 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2596 
2597 		cur_chain = chain;
2598 
2599 		rx_ring = rx_ring->next;
2600 	}
2601 
2602 	return 0;
2603 
2604 err_free_chain:
2605 	cur_chain = head->next;
2606 	while (cur_chain) {
2607 		chain = cur_chain->next;
2608 		devm_kfree(&pdev->dev, cur_chain);
2609 		cur_chain = chain;
2610 	}
2611 	head->next = NULL;
2612 
2613 	return -ENOMEM;
2614 }
2615 
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)2616 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2617 					struct hnae3_ring_chain_node *head)
2618 {
2619 	struct pci_dev *pdev = tqp_vector->handle->pdev;
2620 	struct hnae3_ring_chain_node *chain_tmp, *chain;
2621 
2622 	chain = head->next;
2623 
2624 	while (chain) {
2625 		chain_tmp = chain->next;
2626 		devm_kfree(&pdev->dev, chain);
2627 		chain = chain_tmp;
2628 	}
2629 }
2630 
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)2631 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
2632 				   struct hns3_enet_ring *ring)
2633 {
2634 	ring->next = group->ring;
2635 	group->ring = ring;
2636 
2637 	group->count++;
2638 }
2639 
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)2640 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
2641 {
2642 	struct hnae3_ring_chain_node vector_ring_chain;
2643 	struct hnae3_handle *h = priv->ae_handle;
2644 	struct hns3_enet_tqp_vector *tqp_vector;
2645 	int ret = 0;
2646 	int i;
2647 
2648 	for (i = 0; i < priv->vector_num; i++) {
2649 		tqp_vector = &priv->tqp_vector[i];
2650 		hns3_vector_gl_rl_init_hw(tqp_vector, priv);
2651 		tqp_vector->num_tqps = 0;
2652 	}
2653 
2654 	for (i = 0; i < h->kinfo.num_tqps; i++) {
2655 		u16 vector_i = i % priv->vector_num;
2656 		u16 tqp_num = h->kinfo.num_tqps;
2657 
2658 		tqp_vector = &priv->tqp_vector[vector_i];
2659 
2660 		hns3_add_ring_to_group(&tqp_vector->tx_group,
2661 				       priv->ring_data[i].ring);
2662 
2663 		hns3_add_ring_to_group(&tqp_vector->rx_group,
2664 				       priv->ring_data[i + tqp_num].ring);
2665 
2666 		priv->ring_data[i].ring->tqp_vector = tqp_vector;
2667 		priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
2668 		tqp_vector->num_tqps++;
2669 	}
2670 
2671 	for (i = 0; i < priv->vector_num; i++) {
2672 		tqp_vector = &priv->tqp_vector[i];
2673 
2674 		tqp_vector->rx_group.total_bytes = 0;
2675 		tqp_vector->rx_group.total_packets = 0;
2676 		tqp_vector->tx_group.total_bytes = 0;
2677 		tqp_vector->tx_group.total_packets = 0;
2678 		tqp_vector->handle = h;
2679 
2680 		ret = hns3_get_vector_ring_chain(tqp_vector,
2681 						 &vector_ring_chain);
2682 		if (ret)
2683 			goto map_ring_fail;
2684 
2685 		ret = h->ae_algo->ops->map_ring_to_vector(h,
2686 			tqp_vector->vector_irq, &vector_ring_chain);
2687 
2688 		hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2689 
2690 		if (ret)
2691 			goto map_ring_fail;
2692 
2693 		netif_napi_add(priv->netdev, &tqp_vector->napi,
2694 			       hns3_nic_common_poll, NAPI_POLL_WEIGHT);
2695 	}
2696 
2697 	return 0;
2698 
2699 map_ring_fail:
2700 	while (i--)
2701 		netif_napi_del(&priv->tqp_vector[i].napi);
2702 
2703 	return ret;
2704 }
2705 
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)2706 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
2707 {
2708 #define HNS3_VECTOR_PF_MAX_NUM		64
2709 
2710 	struct hnae3_handle *h = priv->ae_handle;
2711 	struct hns3_enet_tqp_vector *tqp_vector;
2712 	struct hnae3_vector_info *vector;
2713 	struct pci_dev *pdev = h->pdev;
2714 	u16 tqp_num = h->kinfo.num_tqps;
2715 	u16 vector_num;
2716 	int ret = 0;
2717 	u16 i;
2718 
2719 	/* RSS size, cpu online and vector_num should be the same */
2720 	/* Should consider 2p/4p later */
2721 	vector_num = min_t(u16, num_online_cpus(), tqp_num);
2722 	vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
2723 
2724 	vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
2725 			      GFP_KERNEL);
2726 	if (!vector)
2727 		return -ENOMEM;
2728 
2729 	vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
2730 
2731 	priv->vector_num = vector_num;
2732 	priv->tqp_vector = (struct hns3_enet_tqp_vector *)
2733 		devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
2734 			     GFP_KERNEL);
2735 	if (!priv->tqp_vector) {
2736 		ret = -ENOMEM;
2737 		goto out;
2738 	}
2739 
2740 	for (i = 0; i < priv->vector_num; i++) {
2741 		tqp_vector = &priv->tqp_vector[i];
2742 		tqp_vector->idx = i;
2743 		tqp_vector->mask_addr = vector[i].io_addr;
2744 		tqp_vector->vector_irq = vector[i].vector;
2745 		hns3_vector_gl_rl_init(tqp_vector, priv);
2746 	}
2747 
2748 out:
2749 	devm_kfree(&pdev->dev, vector);
2750 	return ret;
2751 }
2752 
hns3_clear_ring_group(struct hns3_enet_ring_group * group)2753 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
2754 {
2755 	group->ring = NULL;
2756 	group->count = 0;
2757 }
2758 
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)2759 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
2760 {
2761 	struct hnae3_ring_chain_node vector_ring_chain;
2762 	struct hnae3_handle *h = priv->ae_handle;
2763 	struct hns3_enet_tqp_vector *tqp_vector;
2764 	int i, ret;
2765 
2766 	for (i = 0; i < priv->vector_num; i++) {
2767 		tqp_vector = &priv->tqp_vector[i];
2768 
2769 		ret = hns3_get_vector_ring_chain(tqp_vector,
2770 						 &vector_ring_chain);
2771 		if (ret)
2772 			return ret;
2773 
2774 		ret = h->ae_algo->ops->unmap_ring_from_vector(h,
2775 			tqp_vector->vector_irq, &vector_ring_chain);
2776 		if (ret)
2777 			return ret;
2778 
2779 		hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2780 
2781 		if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
2782 			irq_set_affinity_notifier(tqp_vector->vector_irq,
2783 						  NULL);
2784 			irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
2785 			free_irq(tqp_vector->vector_irq, tqp_vector);
2786 			tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
2787 		}
2788 
2789 		priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
2790 		hns3_clear_ring_group(&tqp_vector->rx_group);
2791 		hns3_clear_ring_group(&tqp_vector->tx_group);
2792 		netif_napi_del(&priv->tqp_vector[i].napi);
2793 	}
2794 
2795 	return 0;
2796 }
2797 
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)2798 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
2799 {
2800 	struct hnae3_handle *h = priv->ae_handle;
2801 	struct pci_dev *pdev = h->pdev;
2802 	int i, ret;
2803 
2804 	for (i = 0; i < priv->vector_num; i++) {
2805 		struct hns3_enet_tqp_vector *tqp_vector;
2806 
2807 		tqp_vector = &priv->tqp_vector[i];
2808 		ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2809 		if (ret)
2810 			return ret;
2811 	}
2812 
2813 	devm_kfree(&pdev->dev, priv->tqp_vector);
2814 	return 0;
2815 }
2816 
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,int ring_type)2817 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
2818 			     int ring_type)
2819 {
2820 	struct hns3_nic_ring_data *ring_data = priv->ring_data;
2821 	int queue_num = priv->ae_handle->kinfo.num_tqps;
2822 	struct pci_dev *pdev = priv->ae_handle->pdev;
2823 	struct hns3_enet_ring *ring;
2824 
2825 	ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
2826 	if (!ring)
2827 		return -ENOMEM;
2828 
2829 	if (ring_type == HNAE3_RING_TYPE_TX) {
2830 		ring_data[q->tqp_index].ring = ring;
2831 		ring_data[q->tqp_index].queue_index = q->tqp_index;
2832 		ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
2833 	} else {
2834 		ring_data[q->tqp_index + queue_num].ring = ring;
2835 		ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
2836 		ring->io_base = q->io_base;
2837 	}
2838 
2839 	hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
2840 
2841 	ring->tqp = q;
2842 	ring->desc = NULL;
2843 	ring->desc_cb = NULL;
2844 	ring->dev = priv->dev;
2845 	ring->desc_dma_addr = 0;
2846 	ring->buf_size = q->buf_size;
2847 	ring->desc_num = q->desc_num;
2848 	ring->next_to_use = 0;
2849 	ring->next_to_clean = 0;
2850 
2851 	return 0;
2852 }
2853 
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)2854 static int hns3_queue_to_ring(struct hnae3_queue *tqp,
2855 			      struct hns3_nic_priv *priv)
2856 {
2857 	int ret;
2858 
2859 	ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
2860 	if (ret)
2861 		return ret;
2862 
2863 	ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
2864 	if (ret) {
2865 		devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
2866 		return ret;
2867 	}
2868 
2869 	return 0;
2870 }
2871 
hns3_get_ring_config(struct hns3_nic_priv * priv)2872 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
2873 {
2874 	struct hnae3_handle *h = priv->ae_handle;
2875 	struct pci_dev *pdev = h->pdev;
2876 	int i, ret;
2877 
2878 	priv->ring_data =  devm_kzalloc(&pdev->dev,
2879 					array3_size(h->kinfo.num_tqps,
2880 						    sizeof(*priv->ring_data),
2881 						    2),
2882 					GFP_KERNEL);
2883 	if (!priv->ring_data)
2884 		return -ENOMEM;
2885 
2886 	for (i = 0; i < h->kinfo.num_tqps; i++) {
2887 		ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
2888 		if (ret)
2889 			goto err;
2890 	}
2891 
2892 	return 0;
2893 err:
2894 	while (i--) {
2895 		devm_kfree(priv->dev, priv->ring_data[i].ring);
2896 		devm_kfree(priv->dev,
2897 			   priv->ring_data[i + h->kinfo.num_tqps].ring);
2898 	}
2899 
2900 	devm_kfree(&pdev->dev, priv->ring_data);
2901 	return ret;
2902 }
2903 
hns3_put_ring_config(struct hns3_nic_priv * priv)2904 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
2905 {
2906 	struct hnae3_handle *h = priv->ae_handle;
2907 	int i;
2908 
2909 	for (i = 0; i < h->kinfo.num_tqps; i++) {
2910 		devm_kfree(priv->dev, priv->ring_data[i].ring);
2911 		devm_kfree(priv->dev,
2912 			   priv->ring_data[i + h->kinfo.num_tqps].ring);
2913 	}
2914 	devm_kfree(priv->dev, priv->ring_data);
2915 }
2916 
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)2917 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
2918 {
2919 	int ret;
2920 
2921 	if (ring->desc_num <= 0 || ring->buf_size <= 0)
2922 		return -EINVAL;
2923 
2924 	ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
2925 				GFP_KERNEL);
2926 	if (!ring->desc_cb) {
2927 		ret = -ENOMEM;
2928 		goto out;
2929 	}
2930 
2931 	ret = hns3_alloc_desc(ring);
2932 	if (ret)
2933 		goto out_with_desc_cb;
2934 
2935 	if (!HNAE3_IS_TX_RING(ring)) {
2936 		ret = hns3_alloc_ring_buffers(ring);
2937 		if (ret)
2938 			goto out_with_desc;
2939 	}
2940 
2941 	return 0;
2942 
2943 out_with_desc:
2944 	hns3_free_desc(ring);
2945 out_with_desc_cb:
2946 	kfree(ring->desc_cb);
2947 	ring->desc_cb = NULL;
2948 out:
2949 	return ret;
2950 }
2951 
hns3_fini_ring(struct hns3_enet_ring * ring)2952 static void hns3_fini_ring(struct hns3_enet_ring *ring)
2953 {
2954 	hns3_free_desc(ring);
2955 	kfree(ring->desc_cb);
2956 	ring->desc_cb = NULL;
2957 	ring->next_to_clean = 0;
2958 	ring->next_to_use = 0;
2959 }
2960 
hns3_buf_size2type(u32 buf_size)2961 static int hns3_buf_size2type(u32 buf_size)
2962 {
2963 	int bd_size_type;
2964 
2965 	switch (buf_size) {
2966 	case 512:
2967 		bd_size_type = HNS3_BD_SIZE_512_TYPE;
2968 		break;
2969 	case 1024:
2970 		bd_size_type = HNS3_BD_SIZE_1024_TYPE;
2971 		break;
2972 	case 2048:
2973 		bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2974 		break;
2975 	case 4096:
2976 		bd_size_type = HNS3_BD_SIZE_4096_TYPE;
2977 		break;
2978 	default:
2979 		bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2980 	}
2981 
2982 	return bd_size_type;
2983 }
2984 
hns3_init_ring_hw(struct hns3_enet_ring * ring)2985 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
2986 {
2987 	dma_addr_t dma = ring->desc_dma_addr;
2988 	struct hnae3_queue *q = ring->tqp;
2989 
2990 	if (!HNAE3_IS_TX_RING(ring)) {
2991 		hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
2992 			       (u32)dma);
2993 		hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
2994 			       (u32)((dma >> 31) >> 1));
2995 
2996 		hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
2997 			       hns3_buf_size2type(ring->buf_size));
2998 		hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
2999 			       ring->desc_num / 8 - 1);
3000 
3001 	} else {
3002 		hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3003 			       (u32)dma);
3004 		hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3005 			       (u32)((dma >> 31) >> 1));
3006 
3007 		hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3008 			       ring->desc_num / 8 - 1);
3009 	}
3010 }
3011 
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)3012 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3013 {
3014 	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3015 	int i;
3016 
3017 	for (i = 0; i < HNAE3_MAX_TC; i++) {
3018 		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3019 		int j;
3020 
3021 		if (!tc_info->enable)
3022 			continue;
3023 
3024 		for (j = 0; j < tc_info->tqp_count; j++) {
3025 			struct hnae3_queue *q;
3026 
3027 			q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3028 			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3029 				       tc_info->tc);
3030 		}
3031 	}
3032 }
3033 
hns3_init_all_ring(struct hns3_nic_priv * priv)3034 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3035 {
3036 	struct hnae3_handle *h = priv->ae_handle;
3037 	int ring_num = h->kinfo.num_tqps * 2;
3038 	int i, j;
3039 	int ret;
3040 
3041 	for (i = 0; i < ring_num; i++) {
3042 		ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3043 		if (ret) {
3044 			dev_err(priv->dev,
3045 				"Alloc ring memory fail! ret=%d\n", ret);
3046 			goto out_when_alloc_ring_memory;
3047 		}
3048 
3049 		u64_stats_init(&priv->ring_data[i].ring->syncp);
3050 	}
3051 
3052 	return 0;
3053 
3054 out_when_alloc_ring_memory:
3055 	for (j = i - 1; j >= 0; j--)
3056 		hns3_fini_ring(priv->ring_data[j].ring);
3057 
3058 	return -ENOMEM;
3059 }
3060 
hns3_uninit_all_ring(struct hns3_nic_priv * priv)3061 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3062 {
3063 	struct hnae3_handle *h = priv->ae_handle;
3064 	int i;
3065 
3066 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3067 		if (h->ae_algo->ops->reset_queue)
3068 			h->ae_algo->ops->reset_queue(h, i);
3069 
3070 		hns3_fini_ring(priv->ring_data[i].ring);
3071 		hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3072 	}
3073 	return 0;
3074 }
3075 
3076 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev,bool init)3077 static void hns3_init_mac_addr(struct net_device *netdev, bool init)
3078 {
3079 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3080 	struct hnae3_handle *h = priv->ae_handle;
3081 	u8 mac_addr_temp[ETH_ALEN];
3082 
3083 	if (h->ae_algo->ops->get_mac_addr && init) {
3084 		h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3085 		ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3086 	}
3087 
3088 	/* Check if the MAC address is valid, if not get a random one */
3089 	if (!is_valid_ether_addr(netdev->dev_addr)) {
3090 		eth_hw_addr_random(netdev);
3091 		dev_warn(priv->dev, "using random MAC address %pM\n",
3092 			 netdev->dev_addr);
3093 	}
3094 
3095 	if (h->ae_algo->ops->set_mac_addr)
3096 		h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3097 
3098 }
3099 
hns3_uninit_mac_addr(struct net_device * netdev)3100 static void hns3_uninit_mac_addr(struct net_device *netdev)
3101 {
3102 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3103 	struct hnae3_handle *h = priv->ae_handle;
3104 
3105 	if (h->ae_algo->ops->rm_uc_addr)
3106 		h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr);
3107 }
3108 
hns3_nic_set_priv_ops(struct net_device * netdev)3109 static void hns3_nic_set_priv_ops(struct net_device *netdev)
3110 {
3111 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3112 
3113 	if ((netdev->features & NETIF_F_TSO) ||
3114 	    (netdev->features & NETIF_F_TSO6)) {
3115 		priv->ops.fill_desc = hns3_fill_desc_tso;
3116 		priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3117 	} else {
3118 		priv->ops.fill_desc = hns3_fill_desc;
3119 		priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3120 	}
3121 }
3122 
hns3_client_init(struct hnae3_handle * handle)3123 static int hns3_client_init(struct hnae3_handle *handle)
3124 {
3125 	struct pci_dev *pdev = handle->pdev;
3126 	struct hns3_nic_priv *priv;
3127 	struct net_device *netdev;
3128 	int ret;
3129 
3130 	netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv),
3131 				   hns3_get_max_available_channels(handle));
3132 	if (!netdev)
3133 		return -ENOMEM;
3134 
3135 	priv = netdev_priv(netdev);
3136 	priv->dev = &pdev->dev;
3137 	priv->netdev = netdev;
3138 	priv->ae_handle = handle;
3139 	priv->ae_handle->last_reset_time = jiffies;
3140 	priv->tx_timeout_count = 0;
3141 
3142 	handle->kinfo.netdev = netdev;
3143 	handle->priv = (void *)priv;
3144 
3145 	hns3_init_mac_addr(netdev, true);
3146 
3147 	hns3_set_default_feature(netdev);
3148 
3149 	netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3150 	netdev->priv_flags |= IFF_UNICAST_FLT;
3151 	netdev->netdev_ops = &hns3_nic_netdev_ops;
3152 	SET_NETDEV_DEV(netdev, &pdev->dev);
3153 	hns3_ethtool_set_ops(netdev);
3154 	hns3_nic_set_priv_ops(netdev);
3155 
3156 	/* Carrier off reporting is important to ethtool even BEFORE open */
3157 	netif_carrier_off(netdev);
3158 
3159 	if (handle->flags & HNAE3_SUPPORT_VF)
3160 		handle->reset_level = HNAE3_VF_RESET;
3161 	else
3162 		handle->reset_level = HNAE3_FUNC_RESET;
3163 
3164 	ret = hns3_get_ring_config(priv);
3165 	if (ret) {
3166 		ret = -ENOMEM;
3167 		goto out_get_ring_cfg;
3168 	}
3169 
3170 	ret = hns3_nic_alloc_vector_data(priv);
3171 	if (ret) {
3172 		ret = -ENOMEM;
3173 		goto out_alloc_vector_data;
3174 	}
3175 
3176 	ret = hns3_nic_init_vector_data(priv);
3177 	if (ret) {
3178 		ret = -ENOMEM;
3179 		goto out_init_vector_data;
3180 	}
3181 
3182 	ret = hns3_init_all_ring(priv);
3183 	if (ret) {
3184 		ret = -ENOMEM;
3185 		goto out_init_ring_data;
3186 	}
3187 
3188 	ret = register_netdev(netdev);
3189 	if (ret) {
3190 		dev_err(priv->dev, "probe register netdev fail!\n");
3191 		goto out_reg_netdev_fail;
3192 	}
3193 
3194 	hns3_dcbnl_setup(handle);
3195 
3196 	/* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */
3197 	netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
3198 
3199 	return ret;
3200 
3201 out_reg_netdev_fail:
3202 out_init_ring_data:
3203 	(void)hns3_nic_uninit_vector_data(priv);
3204 out_init_vector_data:
3205 	hns3_nic_dealloc_vector_data(priv);
3206 out_alloc_vector_data:
3207 	priv->ring_data = NULL;
3208 out_get_ring_cfg:
3209 	priv->ae_handle = NULL;
3210 	free_netdev(netdev);
3211 	return ret;
3212 }
3213 
hns3_client_uninit(struct hnae3_handle * handle,bool reset)3214 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3215 {
3216 	struct net_device *netdev = handle->kinfo.netdev;
3217 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3218 	int ret;
3219 
3220 	if (netdev->reg_state != NETREG_UNINITIALIZED)
3221 		unregister_netdev(netdev);
3222 
3223 	hns3_force_clear_all_rx_ring(handle);
3224 
3225 	ret = hns3_nic_uninit_vector_data(priv);
3226 	if (ret)
3227 		netdev_err(netdev, "uninit vector error\n");
3228 
3229 	ret = hns3_nic_dealloc_vector_data(priv);
3230 	if (ret)
3231 		netdev_err(netdev, "dealloc vector error\n");
3232 
3233 	ret = hns3_uninit_all_ring(priv);
3234 	if (ret)
3235 		netdev_err(netdev, "uninit ring error\n");
3236 
3237 	hns3_put_ring_config(priv);
3238 
3239 	priv->ring_data = NULL;
3240 
3241 	hns3_uninit_mac_addr(netdev);
3242 
3243 	free_netdev(netdev);
3244 }
3245 
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)3246 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3247 {
3248 	struct net_device *netdev = handle->kinfo.netdev;
3249 
3250 	if (!netdev)
3251 		return;
3252 
3253 	if (linkup) {
3254 		netif_carrier_on(netdev);
3255 		netif_tx_wake_all_queues(netdev);
3256 		netdev_info(netdev, "link up\n");
3257 	} else {
3258 		netif_carrier_off(netdev);
3259 		netif_tx_stop_all_queues(netdev);
3260 		netdev_info(netdev, "link down\n");
3261 	}
3262 }
3263 
hns3_client_setup_tc(struct hnae3_handle * handle,u8 tc)3264 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3265 {
3266 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3267 	struct net_device *ndev = kinfo->netdev;
3268 	bool if_running;
3269 	int ret;
3270 
3271 	if (tc > HNAE3_MAX_TC)
3272 		return -EINVAL;
3273 
3274 	if (!ndev)
3275 		return -ENODEV;
3276 
3277 	if_running = netif_running(ndev);
3278 
3279 	if (if_running) {
3280 		(void)hns3_nic_net_stop(ndev);
3281 		msleep(100);
3282 	}
3283 
3284 	ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3285 		kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3286 	if (ret)
3287 		goto err_out;
3288 
3289 	ret = hns3_nic_set_real_num_queue(ndev);
3290 
3291 err_out:
3292 	if (if_running)
3293 		(void)hns3_nic_net_open(ndev);
3294 
3295 	return ret;
3296 }
3297 
hns3_recover_hw_addr(struct net_device * ndev)3298 static void hns3_recover_hw_addr(struct net_device *ndev)
3299 {
3300 	struct netdev_hw_addr_list *list;
3301 	struct netdev_hw_addr *ha, *tmp;
3302 
3303 	/* go through and sync uc_addr entries to the device */
3304 	list = &ndev->uc;
3305 	list_for_each_entry_safe(ha, tmp, &list->list, list)
3306 		hns3_nic_uc_sync(ndev, ha->addr);
3307 
3308 	/* go through and sync mc_addr entries to the device */
3309 	list = &ndev->mc;
3310 	list_for_each_entry_safe(ha, tmp, &list->list, list)
3311 		hns3_nic_mc_sync(ndev, ha->addr);
3312 }
3313 
hns3_clear_tx_ring(struct hns3_enet_ring * ring)3314 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
3315 {
3316 	while (ring->next_to_clean != ring->next_to_use) {
3317 		ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
3318 		hns3_free_buffer_detach(ring, ring->next_to_clean);
3319 		ring_ptr_move_fw(ring, next_to_clean);
3320 	}
3321 }
3322 
hns3_clear_rx_ring(struct hns3_enet_ring * ring)3323 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3324 {
3325 	struct hns3_desc_cb res_cbs;
3326 	int ret;
3327 
3328 	while (ring->next_to_use != ring->next_to_clean) {
3329 		/* When a buffer is not reused, it's memory has been
3330 		 * freed in hns3_handle_rx_bd or will be freed by
3331 		 * stack, so we need to replace the buffer here.
3332 		 */
3333 		if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3334 			ret = hns3_reserve_buffer_map(ring, &res_cbs);
3335 			if (ret) {
3336 				u64_stats_update_begin(&ring->syncp);
3337 				ring->stats.sw_err_cnt++;
3338 				u64_stats_update_end(&ring->syncp);
3339 				/* if alloc new buffer fail, exit directly
3340 				 * and reclear in up flow.
3341 				 */
3342 				netdev_warn(ring->tqp->handle->kinfo.netdev,
3343 					    "reserve buffer map failed, ret = %d\n",
3344 					    ret);
3345 				return ret;
3346 			}
3347 			hns3_replace_buffer(ring, ring->next_to_use,
3348 					    &res_cbs);
3349 		}
3350 		ring_ptr_move_fw(ring, next_to_use);
3351 	}
3352 
3353 	return 0;
3354 }
3355 
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)3356 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
3357 {
3358 	while (ring->next_to_use != ring->next_to_clean) {
3359 		/* When a buffer is not reused, it's memory has been
3360 		 * freed in hns3_handle_rx_bd or will be freed by
3361 		 * stack, so only need to unmap the buffer here.
3362 		 */
3363 		if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3364 			hns3_unmap_buffer(ring,
3365 					  &ring->desc_cb[ring->next_to_use]);
3366 			ring->desc_cb[ring->next_to_use].dma = 0;
3367 		}
3368 
3369 		ring_ptr_move_fw(ring, next_to_use);
3370 	}
3371 }
3372 
hns3_force_clear_all_rx_ring(struct hnae3_handle * h)3373 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3374 {
3375 	struct net_device *ndev = h->kinfo.netdev;
3376 	struct hns3_nic_priv *priv = netdev_priv(ndev);
3377 	struct hns3_enet_ring *ring;
3378 	u32 i;
3379 
3380 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3381 		ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3382 		hns3_force_clear_rx_ring(ring);
3383 	}
3384 }
3385 
hns3_clear_all_ring(struct hnae3_handle * h)3386 static void hns3_clear_all_ring(struct hnae3_handle *h)
3387 {
3388 	struct net_device *ndev = h->kinfo.netdev;
3389 	struct hns3_nic_priv *priv = netdev_priv(ndev);
3390 	u32 i;
3391 
3392 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3393 		struct netdev_queue *dev_queue;
3394 		struct hns3_enet_ring *ring;
3395 
3396 		ring = priv->ring_data[i].ring;
3397 		hns3_clear_tx_ring(ring);
3398 		dev_queue = netdev_get_tx_queue(ndev,
3399 						priv->ring_data[i].queue_index);
3400 		netdev_tx_reset_queue(dev_queue);
3401 
3402 		ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3403 		/* Continue to clear other rings even if clearing some
3404 		 * rings failed.
3405 		 */
3406 		hns3_clear_rx_ring(ring);
3407 	}
3408 }
3409 
hns3_nic_reset_all_ring(struct hnae3_handle * h)3410 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3411 {
3412 	struct net_device *ndev = h->kinfo.netdev;
3413 	struct hns3_nic_priv *priv = netdev_priv(ndev);
3414 	struct hns3_enet_ring *rx_ring;
3415 	int i, j;
3416 	int ret;
3417 
3418 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3419 		h->ae_algo->ops->reset_queue(h, i);
3420 		hns3_init_ring_hw(priv->ring_data[i].ring);
3421 
3422 		/* We need to clear tx ring here because self test will
3423 		 * use the ring and will not run down before up
3424 		 */
3425 		hns3_clear_tx_ring(priv->ring_data[i].ring);
3426 		priv->ring_data[i].ring->next_to_clean = 0;
3427 		priv->ring_data[i].ring->next_to_use = 0;
3428 
3429 		rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3430 		hns3_init_ring_hw(rx_ring);
3431 		ret = hns3_clear_rx_ring(rx_ring);
3432 		if (ret)
3433 			return ret;
3434 
3435 		/* We can not know the hardware head and tail when this
3436 		 * function is called in reset flow, so we reuse all desc.
3437 		 */
3438 		for (j = 0; j < rx_ring->desc_num; j++)
3439 			hns3_reuse_buffer(rx_ring, j);
3440 
3441 		rx_ring->next_to_clean = 0;
3442 		rx_ring->next_to_use = 0;
3443 	}
3444 
3445 	hns3_init_tx_ring_tc(priv);
3446 
3447 	return 0;
3448 }
3449 
hns3_store_coal(struct hns3_nic_priv * priv)3450 static void hns3_store_coal(struct hns3_nic_priv *priv)
3451 {
3452 	/* ethtool only support setting and querying one coal
3453 	 * configuation for now, so save the vector 0' coal
3454 	 * configuation here in order to restore it.
3455 	 */
3456 	memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3457 	       sizeof(struct hns3_enet_coalesce));
3458 	memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3459 	       sizeof(struct hns3_enet_coalesce));
3460 }
3461 
hns3_restore_coal(struct hns3_nic_priv * priv)3462 static void hns3_restore_coal(struct hns3_nic_priv *priv)
3463 {
3464 	u16 vector_num = priv->vector_num;
3465 	int i;
3466 
3467 	for (i = 0; i < vector_num; i++) {
3468 		memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3469 		       sizeof(struct hns3_enet_coalesce));
3470 		memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3471 		       sizeof(struct hns3_enet_coalesce));
3472 	}
3473 }
3474 
hns3_reset_notify_down_enet(struct hnae3_handle * handle)3475 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3476 {
3477 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3478 	struct net_device *ndev = kinfo->netdev;
3479 
3480 	if (!netif_running(ndev))
3481 		return 0;
3482 
3483 	return hns3_nic_net_stop(ndev);
3484 }
3485 
hns3_reset_notify_up_enet(struct hnae3_handle * handle)3486 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3487 {
3488 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3489 	int ret = 0;
3490 
3491 	if (netif_running(kinfo->netdev)) {
3492 		ret = hns3_nic_net_up(kinfo->netdev);
3493 		if (ret) {
3494 			netdev_err(kinfo->netdev,
3495 				   "hns net up fail, ret=%d!\n", ret);
3496 			return ret;
3497 		}
3498 		handle->last_reset_time = jiffies;
3499 	}
3500 
3501 	return ret;
3502 }
3503 
hns3_reset_notify_init_enet(struct hnae3_handle * handle)3504 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
3505 {
3506 	struct net_device *netdev = handle->kinfo.netdev;
3507 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3508 	int ret;
3509 
3510 	hns3_init_mac_addr(netdev, false);
3511 	hns3_nic_set_rx_mode(netdev);
3512 	hns3_recover_hw_addr(netdev);
3513 
3514 	/* Hardware table is only clear when pf resets */
3515 	if (!(handle->flags & HNAE3_SUPPORT_VF))
3516 		hns3_restore_vlan(netdev);
3517 
3518 	/* Carrier off reporting is important to ethtool even BEFORE open */
3519 	netif_carrier_off(netdev);
3520 
3521 	hns3_restore_coal(priv);
3522 
3523 	ret = hns3_nic_init_vector_data(priv);
3524 	if (ret)
3525 		return ret;
3526 
3527 	ret = hns3_init_all_ring(priv);
3528 	if (ret) {
3529 		hns3_nic_uninit_vector_data(priv);
3530 		priv->ring_data = NULL;
3531 	}
3532 
3533 	return ret;
3534 }
3535 
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)3536 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
3537 {
3538 	struct net_device *netdev = handle->kinfo.netdev;
3539 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3540 	int ret;
3541 
3542 	hns3_force_clear_all_rx_ring(handle);
3543 
3544 	ret = hns3_nic_uninit_vector_data(priv);
3545 	if (ret) {
3546 		netdev_err(netdev, "uninit vector error\n");
3547 		return ret;
3548 	}
3549 
3550 	hns3_store_coal(priv);
3551 
3552 	ret = hns3_uninit_all_ring(priv);
3553 	if (ret)
3554 		netdev_err(netdev, "uninit ring error\n");
3555 
3556 	hns3_uninit_mac_addr(netdev);
3557 
3558 	return ret;
3559 }
3560 
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)3561 static int hns3_reset_notify(struct hnae3_handle *handle,
3562 			     enum hnae3_reset_notify_type type)
3563 {
3564 	int ret = 0;
3565 
3566 	switch (type) {
3567 	case HNAE3_UP_CLIENT:
3568 		ret = hns3_reset_notify_up_enet(handle);
3569 		break;
3570 	case HNAE3_DOWN_CLIENT:
3571 		ret = hns3_reset_notify_down_enet(handle);
3572 		break;
3573 	case HNAE3_INIT_CLIENT:
3574 		ret = hns3_reset_notify_init_enet(handle);
3575 		break;
3576 	case HNAE3_UNINIT_CLIENT:
3577 		ret = hns3_reset_notify_uninit_enet(handle);
3578 		break;
3579 	default:
3580 		break;
3581 	}
3582 
3583 	return ret;
3584 }
3585 
hns3_modify_tqp_num(struct net_device * netdev,u16 new_tqp_num)3586 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num)
3587 {
3588 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3589 	struct hnae3_handle *h = hns3_get_handle(netdev);
3590 	int ret;
3591 
3592 	ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
3593 	if (ret)
3594 		return ret;
3595 
3596 	ret = hns3_get_ring_config(priv);
3597 	if (ret)
3598 		return ret;
3599 
3600 	ret = hns3_nic_alloc_vector_data(priv);
3601 	if (ret)
3602 		goto err_alloc_vector;
3603 
3604 	hns3_restore_coal(priv);
3605 
3606 	ret = hns3_nic_init_vector_data(priv);
3607 	if (ret)
3608 		goto err_uninit_vector;
3609 
3610 	ret = hns3_init_all_ring(priv);
3611 	if (ret)
3612 		goto err_put_ring;
3613 
3614 	return 0;
3615 
3616 err_put_ring:
3617 	hns3_put_ring_config(priv);
3618 err_uninit_vector:
3619 	hns3_nic_uninit_vector_data(priv);
3620 err_alloc_vector:
3621 	hns3_nic_dealloc_vector_data(priv);
3622 	return ret;
3623 }
3624 
hns3_adjust_tqps_num(u8 num_tc,u32 new_tqp_num)3625 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
3626 {
3627 	return (new_tqp_num / num_tc) * num_tc;
3628 }
3629 
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)3630 int hns3_set_channels(struct net_device *netdev,
3631 		      struct ethtool_channels *ch)
3632 {
3633 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3634 	struct hnae3_handle *h = hns3_get_handle(netdev);
3635 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
3636 	bool if_running = netif_running(netdev);
3637 	u32 new_tqp_num = ch->combined_count;
3638 	u16 org_tqp_num;
3639 	int ret;
3640 
3641 	if (ch->rx_count || ch->tx_count)
3642 		return -EINVAL;
3643 
3644 	if (new_tqp_num > hns3_get_max_available_channels(h) ||
3645 	    new_tqp_num < kinfo->num_tc) {
3646 		dev_err(&netdev->dev,
3647 			"Change tqps fail, the tqp range is from %d to %d",
3648 			kinfo->num_tc,
3649 			hns3_get_max_available_channels(h));
3650 		return -EINVAL;
3651 	}
3652 
3653 	new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
3654 	if (kinfo->num_tqps == new_tqp_num)
3655 		return 0;
3656 
3657 	if (if_running)
3658 		hns3_nic_net_stop(netdev);
3659 
3660 	ret = hns3_nic_uninit_vector_data(priv);
3661 	if (ret) {
3662 		dev_err(&netdev->dev,
3663 			"Unbind vector with tqp fail, nothing is changed");
3664 		goto open_netdev;
3665 	}
3666 
3667 	hns3_store_coal(priv);
3668 
3669 	hns3_nic_dealloc_vector_data(priv);
3670 
3671 	hns3_uninit_all_ring(priv);
3672 	hns3_put_ring_config(priv);
3673 
3674 	org_tqp_num = h->kinfo.num_tqps;
3675 	ret = hns3_modify_tqp_num(netdev, new_tqp_num);
3676 	if (ret) {
3677 		ret = hns3_modify_tqp_num(netdev, org_tqp_num);
3678 		if (ret) {
3679 			/* If revert to old tqp failed, fatal error occurred */
3680 			dev_err(&netdev->dev,
3681 				"Revert to old tqp num fail, ret=%d", ret);
3682 			return ret;
3683 		}
3684 		dev_info(&netdev->dev,
3685 			 "Change tqp num fail, Revert to old tqp num");
3686 	}
3687 
3688 open_netdev:
3689 	if (if_running)
3690 		hns3_nic_net_open(netdev);
3691 
3692 	return ret;
3693 }
3694 
3695 static const struct hnae3_client_ops client_ops = {
3696 	.init_instance = hns3_client_init,
3697 	.uninit_instance = hns3_client_uninit,
3698 	.link_status_change = hns3_link_status_change,
3699 	.setup_tc = hns3_client_setup_tc,
3700 	.reset_notify = hns3_reset_notify,
3701 };
3702 
3703 /* hns3_init_module - Driver registration routine
3704  * hns3_init_module is the first routine called when the driver is
3705  * loaded. All it does is register with the PCI subsystem.
3706  */
hns3_init_module(void)3707 static int __init hns3_init_module(void)
3708 {
3709 	int ret;
3710 
3711 	pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
3712 	pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
3713 
3714 	client.type = HNAE3_CLIENT_KNIC;
3715 	snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
3716 		 hns3_driver_name);
3717 
3718 	client.ops = &client_ops;
3719 
3720 	INIT_LIST_HEAD(&client.node);
3721 
3722 	ret = hnae3_register_client(&client);
3723 	if (ret)
3724 		return ret;
3725 
3726 	ret = pci_register_driver(&hns3_driver);
3727 	if (ret)
3728 		hnae3_unregister_client(&client);
3729 
3730 	return ret;
3731 }
3732 module_init(hns3_init_module);
3733 
3734 /* hns3_exit_module - Driver exit cleanup routine
3735  * hns3_exit_module is called just before the driver is removed
3736  * from memory.
3737  */
hns3_exit_module(void)3738 static void __exit hns3_exit_module(void)
3739 {
3740 	pci_unregister_driver(&hns3_driver);
3741 	hnae3_unregister_client(&client);
3742 }
3743 module_exit(hns3_exit_module);
3744 
3745 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
3746 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3747 MODULE_LICENSE("GPL");
3748 MODULE_ALIAS("pci:hns-nic");
3749 MODULE_VERSION(HNS3_MOD_VERSION);
3750