1 /*
2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include "mt76x2.h"
19 #include "mt76x2_eeprom.h"
20
21 #define CCK_RATE(_idx, _rate) { \
22 .bitrate = _rate, \
23 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
24 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
25 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
26 }
27
28 #define OFDM_RATE(_idx, _rate) { \
29 .bitrate = _rate, \
30 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
31 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
32 }
33
34 struct ieee80211_rate mt76x2_rates[] = {
35 CCK_RATE(0, 10),
36 CCK_RATE(1, 20),
37 CCK_RATE(2, 55),
38 CCK_RATE(3, 110),
39 OFDM_RATE(0, 60),
40 OFDM_RATE(1, 90),
41 OFDM_RATE(2, 120),
42 OFDM_RATE(3, 180),
43 OFDM_RATE(4, 240),
44 OFDM_RATE(5, 360),
45 OFDM_RATE(6, 480),
46 OFDM_RATE(7, 540),
47 };
48 EXPORT_SYMBOL_GPL(mt76x2_rates);
49
50 struct mt76x2_reg_pair {
51 u32 reg;
52 u32 value;
53 };
54
55 static void
mt76x2_set_wlan_state(struct mt76x2_dev * dev,bool enable)56 mt76x2_set_wlan_state(struct mt76x2_dev *dev, bool enable)
57 {
58 u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
59
60 if (enable)
61 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
62 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
63 else
64 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
65 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
66
67 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
68 udelay(20);
69 }
70
mt76x2_reset_wlan(struct mt76x2_dev * dev,bool enable)71 void mt76x2_reset_wlan(struct mt76x2_dev *dev, bool enable)
72 {
73 u32 val;
74
75 if (!enable)
76 goto out;
77
78 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
79
80 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
81
82 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
83 val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
84 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
85 udelay(20);
86
87 val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
88 }
89
90 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
91 udelay(20);
92
93 out:
94 mt76x2_set_wlan_state(dev, enable);
95 }
96 EXPORT_SYMBOL_GPL(mt76x2_reset_wlan);
97
98 static void
mt76x2_write_reg_pairs(struct mt76x2_dev * dev,const struct mt76x2_reg_pair * data,int len)99 mt76x2_write_reg_pairs(struct mt76x2_dev *dev,
100 const struct mt76x2_reg_pair *data, int len)
101 {
102 while (len > 0) {
103 mt76_wr(dev, data->reg, data->value);
104 len--;
105 data++;
106 }
107 }
108
mt76_write_mac_initvals(struct mt76x2_dev * dev)109 void mt76_write_mac_initvals(struct mt76x2_dev *dev)
110 {
111 #define DEFAULT_PROT_CFG_CCK \
112 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \
113 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
114 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
115 MT_PROT_CFG_RTS_THRESH)
116
117 #define DEFAULT_PROT_CFG_OFDM \
118 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
119 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
120 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
121 MT_PROT_CFG_RTS_THRESH)
122
123 #define DEFAULT_PROT_CFG_20 \
124 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
125 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
126 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
127 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
128
129 #define DEFAULT_PROT_CFG_40 \
130 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \
131 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
132 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
133 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
134
135 static const struct mt76x2_reg_pair vals[] = {
136 /* Copied from MediaTek reference source */
137 { MT_PBF_SYS_CTRL, 0x00080c00 },
138 { MT_PBF_CFG, 0x1efebcff },
139 { MT_FCE_PSE_CTRL, 0x00000001 },
140 { MT_MAC_SYS_CTRL, 0x0000000c },
141 { MT_MAX_LEN_CFG, 0x003e3f00 },
142 { MT_AMPDU_MAX_LEN_20M1S, 0xaaa99887 },
143 { MT_AMPDU_MAX_LEN_20M2S, 0x000000aa },
144 { MT_XIFS_TIME_CFG, 0x33a40d0a },
145 { MT_BKOFF_SLOT_CFG, 0x00000209 },
146 { MT_TBTT_SYNC_CFG, 0x00422010 },
147 { MT_PWR_PIN_CFG, 0x00000000 },
148 { 0x1238, 0x001700c8 },
149 { MT_TX_SW_CFG0, 0x00101001 },
150 { MT_TX_SW_CFG1, 0x00010000 },
151 { MT_TX_SW_CFG2, 0x00000000 },
152 { MT_TXOP_CTRL_CFG, 0x0400583f },
153 { MT_TX_RTS_CFG, 0x00100020 },
154 { MT_TX_TIMEOUT_CFG, 0x000a2290 },
155 { MT_TX_RETRY_CFG, 0x47f01f0f },
156 { MT_EXP_ACK_TIME, 0x002c00dc },
157 { MT_TX_PROT_CFG6, 0xe3f42004 },
158 { MT_TX_PROT_CFG7, 0xe3f42084 },
159 { MT_TX_PROT_CFG8, 0xe3f42104 },
160 { MT_PIFS_TX_CFG, 0x00060fff },
161 { MT_RX_FILTR_CFG, 0x00015f97 },
162 { MT_LEGACY_BASIC_RATE, 0x0000017f },
163 { MT_HT_BASIC_RATE, 0x00004003 },
164 { MT_PN_PAD_MODE, 0x00000003 },
165 { MT_TXOP_HLDR_ET, 0x00000002 },
166 { 0xa44, 0x00000000 },
167 { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
168 { MT_TSO_CTRL, 0x00000000 },
169 { MT_AUX_CLK_CFG, 0x00000000 },
170 { MT_DACCLK_EN_DLY_CFG, 0x00000000 },
171 { MT_TX_ALC_CFG_4, 0x00000000 },
172 { MT_TX_ALC_VGA3, 0x00000000 },
173 { MT_TX_PWR_CFG_0, 0x3a3a3a3a },
174 { MT_TX_PWR_CFG_1, 0x3a3a3a3a },
175 { MT_TX_PWR_CFG_2, 0x3a3a3a3a },
176 { MT_TX_PWR_CFG_3, 0x3a3a3a3a },
177 { MT_TX_PWR_CFG_4, 0x3a3a3a3a },
178 { MT_TX_PWR_CFG_7, 0x3a3a3a3a },
179 { MT_TX_PWR_CFG_8, 0x0000003a },
180 { MT_TX_PWR_CFG_9, 0x0000003a },
181 { MT_EFUSE_CTRL, 0x0000d000 },
182 { MT_PAUSE_ENABLE_CONTROL1, 0x0000000a },
183 { MT_FCE_WLAN_FLOW_CONTROL1, 0x60401c18 },
184 { MT_WPDMA_DELAY_INT_CFG, 0x94ff0000 },
185 { MT_TX_SW_CFG3, 0x00000004 },
186 { MT_HT_FBK_TO_LEGACY, 0x00001818 },
187 { MT_VHT_HT_FBK_CFG1, 0xedcba980 },
188 { MT_PROT_AUTO_TX_CFG, 0x00830083 },
189 { MT_HT_CTRL_CFG, 0x000001ff },
190 };
191 struct mt76x2_reg_pair prot_vals[] = {
192 { MT_CCK_PROT_CFG, DEFAULT_PROT_CFG_CCK },
193 { MT_OFDM_PROT_CFG, DEFAULT_PROT_CFG_OFDM },
194 { MT_MM20_PROT_CFG, DEFAULT_PROT_CFG_20 },
195 { MT_MM40_PROT_CFG, DEFAULT_PROT_CFG_40 },
196 { MT_GF20_PROT_CFG, DEFAULT_PROT_CFG_20 },
197 { MT_GF40_PROT_CFG, DEFAULT_PROT_CFG_40 },
198 };
199
200 mt76x2_write_reg_pairs(dev, vals, ARRAY_SIZE(vals));
201 mt76x2_write_reg_pairs(dev, prot_vals, ARRAY_SIZE(prot_vals));
202 }
203 EXPORT_SYMBOL_GPL(mt76_write_mac_initvals);
204
mt76x2_init_device(struct mt76x2_dev * dev)205 void mt76x2_init_device(struct mt76x2_dev *dev)
206 {
207 struct ieee80211_hw *hw = mt76_hw(dev);
208
209 hw->queues = 4;
210 hw->max_rates = 1;
211 hw->max_report_rates = 7;
212 hw->max_rate_tries = 1;
213 hw->extra_tx_headroom = 2;
214
215 hw->sta_data_size = sizeof(struct mt76x2_sta);
216 hw->vif_data_size = sizeof(struct mt76x2_vif);
217
218 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
219 ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER);
220
221 dev->mt76.sband_2g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
222 dev->mt76.sband_5g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
223
224 dev->chainmask = 0x202;
225 dev->global_wcid.idx = 255;
226 dev->global_wcid.hw_key_idx = -1;
227 dev->slottime = 9;
228
229 /* init antenna configuration */
230 dev->mt76.antenna_mask = 3;
231 }
232 EXPORT_SYMBOL_GPL(mt76x2_init_device);
233
mt76x2_init_txpower(struct mt76x2_dev * dev,struct ieee80211_supported_band * sband)234 void mt76x2_init_txpower(struct mt76x2_dev *dev,
235 struct ieee80211_supported_band *sband)
236 {
237 struct ieee80211_channel *chan;
238 struct mt76x2_tx_power_info txp;
239 struct mt76_rate_power t = {};
240 int target_power;
241 int i;
242
243 for (i = 0; i < sband->n_channels; i++) {
244 chan = &sband->channels[i];
245
246 mt76x2_get_power_info(dev, &txp, chan);
247
248 target_power = max_t(int, (txp.chain[0].target_power +
249 txp.chain[0].delta),
250 (txp.chain[1].target_power +
251 txp.chain[1].delta));
252
253 mt76x2_get_rate_power(dev, &t, chan);
254
255 chan->max_power = mt76x2_get_max_rate_power(&t) +
256 target_power;
257 chan->max_power /= 2;
258
259 /* convert to combined output power on 2x2 devices */
260 chan->max_power += 3;
261 }
262 }
263 EXPORT_SYMBOL_GPL(mt76x2_init_txpower);
264