1 /*
2 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "mt76x2u.h"
18 #include "mt76x2_eeprom.h"
19
mt76x2u_mac_reset_counters(struct mt76x2_dev * dev)20 static void mt76x2u_mac_reset_counters(struct mt76x2_dev *dev)
21 {
22 mt76_rr(dev, MT_RX_STAT_0);
23 mt76_rr(dev, MT_RX_STAT_1);
24 mt76_rr(dev, MT_RX_STAT_2);
25 mt76_rr(dev, MT_TX_STA_0);
26 mt76_rr(dev, MT_TX_STA_1);
27 mt76_rr(dev, MT_TX_STA_2);
28 }
29
mt76x2u_mac_fixup_xtal(struct mt76x2_dev * dev)30 static void mt76x2u_mac_fixup_xtal(struct mt76x2_dev *dev)
31 {
32 s8 offset = 0;
33 u16 eep_val;
34
35 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
36
37 offset = eep_val & 0x7f;
38 if ((eep_val & 0xff) == 0xff)
39 offset = 0;
40 else if (eep_val & 0x80)
41 offset = 0 - offset;
42
43 eep_val >>= 8;
44 if (eep_val == 0x00 || eep_val == 0xff) {
45 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
46 eep_val &= 0xff;
47
48 if (eep_val == 0x00 || eep_val == 0xff)
49 eep_val = 0x14;
50 }
51
52 eep_val &= 0x7f;
53 mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5),
54 MT_XO_CTRL5_C2_VAL, eep_val + offset);
55 mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL);
56
57 mt76_wr(dev, 0x504, 0x06000000);
58 mt76_wr(dev, 0x50c, 0x08800000);
59 mdelay(5);
60 mt76_wr(dev, 0x504, 0x0);
61
62 /* decrease SIFS from 16us to 13us */
63 mt76_rmw_field(dev, MT_XIFS_TIME_CFG,
64 MT_XIFS_TIME_CFG_OFDM_SIFS, 0xd);
65 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, MT_BKOFF_SLOT_CFG_CC_DELAY, 1);
66
67 /* init fce */
68 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
69
70 eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
71 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
72 case 0:
73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
74 break;
75 case 1:
76 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
77 break;
78 default:
79 break;
80 }
81 }
82
mt76x2u_mac_reset(struct mt76x2_dev * dev)83 int mt76x2u_mac_reset(struct mt76x2_dev *dev)
84 {
85 mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5));
86
87 /* init pbf regs */
88 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
89 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
90
91 mt76_write_mac_initvals(dev);
92
93 mt76_wr(dev, MT_TX_LINK_CFG, 0x1020);
94 mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13);
95 mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00);
96 mt76_wr(dev, MT_TX_RTS_CFG, 0x92b20);
97
98 mt76_wr(dev, MT_WMM_AIFSN, 0x2273);
99 mt76_wr(dev, MT_WMM_CWMIN, 0x2344);
100 mt76_wr(dev, MT_WMM_CWMAX, 0x34aa);
101
102 mt76_clear(dev, MT_MAC_SYS_CTRL,
103 MT_MAC_SYS_CTRL_RESET_CSR |
104 MT_MAC_SYS_CTRL_RESET_BBP);
105
106 if (is_mt7612(dev))
107 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
108
109 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000);
110 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
111
112 mt76x2u_mac_fixup_xtal(dev);
113
114 return 0;
115 }
116
mt76x2u_mac_start(struct mt76x2_dev * dev)117 int mt76x2u_mac_start(struct mt76x2_dev *dev)
118 {
119 mt76x2u_mac_reset_counters(dev);
120
121 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
122 wait_for_wpdma(dev);
123 usleep_range(50, 100);
124
125 mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
126
127 mt76_wr(dev, MT_MAC_SYS_CTRL,
128 MT_MAC_SYS_CTRL_ENABLE_TX |
129 MT_MAC_SYS_CTRL_ENABLE_RX);
130
131 return 0;
132 }
133
mt76x2u_mac_stop(struct mt76x2_dev * dev)134 int mt76x2u_mac_stop(struct mt76x2_dev *dev)
135 {
136 int i, count = 0, val;
137 bool stopped = false;
138 u32 rts_cfg;
139
140 if (test_bit(MT76_REMOVED, &dev->mt76.state))
141 return -EIO;
142
143 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
144 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
145
146 mt76_clear(dev, MT_TXOP_CTRL_CFG, BIT(20));
147 mt76_clear(dev, MT_TXOP_HLDR_ET, BIT(1));
148
149 /* wait tx dma to stop */
150 for (i = 0; i < 2000; i++) {
151 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
152 if (!(val & MT_USB_DMA_CFG_TX_BUSY) && i > 10)
153 break;
154 usleep_range(50, 100);
155 }
156
157 /* page count on TxQ */
158 for (i = 0; i < 200; i++) {
159 if (!(mt76_rr(dev, 0x0438) & 0xffffffff) &&
160 !(mt76_rr(dev, 0x0a30) & 0x000000ff) &&
161 !(mt76_rr(dev, 0x0a34) & 0xff00ff00))
162 break;
163 usleep_range(10, 20);
164 }
165
166 /* disable tx-rx */
167 mt76_clear(dev, MT_MAC_SYS_CTRL,
168 MT_MAC_SYS_CTRL_ENABLE_RX |
169 MT_MAC_SYS_CTRL_ENABLE_TX);
170
171 /* Wait for MAC to become idle */
172 for (i = 0; i < 1000; i++) {
173 if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) &&
174 !mt76_rr(dev, MT_BBP(IBI, 12))) {
175 stopped = true;
176 break;
177 }
178 usleep_range(10, 20);
179 }
180
181 if (!stopped) {
182 mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
183 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
184
185 mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
186 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
187 }
188
189 /* page count on RxQ */
190 for (i = 0; i < 200; i++) {
191 if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) &&
192 !(mt76_rr(dev, 0x0a30) & 0xffffffff) &&
193 !(mt76_rr(dev, 0x0a34) & 0xffffffff) &&
194 ++count > 10)
195 break;
196 msleep(50);
197 }
198
199 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 2000))
200 dev_warn(dev->mt76.dev, "MAC RX failed to stop\n");
201
202 /* wait rx dma to stop */
203 for (i = 0; i < 2000; i++) {
204 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
205 if (!(val & MT_USB_DMA_CFG_RX_BUSY) && i > 10)
206 break;
207 usleep_range(50, 100);
208 }
209
210 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
211
212 return 0;
213 }
214
mt76x2u_mac_resume(struct mt76x2_dev * dev)215 void mt76x2u_mac_resume(struct mt76x2_dev *dev)
216 {
217 mt76_wr(dev, MT_MAC_SYS_CTRL,
218 MT_MAC_SYS_CTRL_ENABLE_TX |
219 MT_MAC_SYS_CTRL_ENABLE_RX);
220 mt76_set(dev, MT_TXOP_CTRL_CFG, BIT(20));
221 mt76_set(dev, MT_TXOP_HLDR_ET, BIT(1));
222 }
223
mt76x2u_mac_setaddr(struct mt76x2_dev * dev,u8 * addr)224 void mt76x2u_mac_setaddr(struct mt76x2_dev *dev, u8 *addr)
225 {
226 ether_addr_copy(dev->mt76.macaddr, addr);
227
228 if (!is_valid_ether_addr(dev->mt76.macaddr)) {
229 eth_random_addr(dev->mt76.macaddr);
230 dev_info(dev->mt76.dev,
231 "Invalid MAC address, using random address %pM\n",
232 dev->mt76.macaddr);
233 }
234
235 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr));
236 mt76_wr(dev, MT_MAC_ADDR_DW1,
237 get_unaligned_le16(dev->mt76.macaddr + 4) |
238 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));
239 }
240
241