1 /*
2 * Copyright (C) 2014-2017 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 /*
15 * This file contains the Broadcom Iproc GPIO driver that supports 3
16 * GPIO controllers on Iproc including the ASIU GPIO controller, the
17 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
18 * PINCONF such as bias pull up/down, and drive strength are also supported
19 * in this driver.
20 *
21 * It provides the functionality where pins from the GPIO can be
22 * individually muxed to GPIO function, if individual pad
23 * configuration is supported, through the interaction with respective
24 * SoCs IOMUX controller.
25 */
26
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/gpio/driver.h>
32 #include <linux/ioport.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38
39 #include "../pinctrl-utils.h"
40
41 #define IPROC_GPIO_DATA_IN_OFFSET 0x00
42 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04
43 #define IPROC_GPIO_OUT_EN_OFFSET 0x08
44 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
45 #define IPROC_GPIO_INT_DE_OFFSET 0x10
46 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14
47 #define IPROC_GPIO_INT_MSK_OFFSET 0x18
48 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c
49 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
50 #define IPROC_GPIO_INT_CLR_OFFSET 0x24
51 #define IPROC_GPIO_PAD_RES_OFFSET 0x34
52 #define IPROC_GPIO_RES_EN_OFFSET 0x38
53
54 /* drive strength control for ASIU GPIO */
55 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
56
57 /* pinconf for CCM GPIO */
58 #define IPROC_GPIO_PULL_DN_OFFSET 0x10
59 #define IPROC_GPIO_PULL_UP_OFFSET 0x14
60
61 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
62 #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
63
64 #define GPIO_BANK_SIZE 0x200
65 #define NGPIOS_PER_BANK 32
66 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
67
68 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
69 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
70
71 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20
72 #define GPIO_DRV_STRENGTH_BITS 3
73 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
74
75 enum iproc_pinconf_param {
76 IPROC_PINCONF_DRIVE_STRENGTH = 0,
77 IPROC_PINCONF_BIAS_DISABLE,
78 IPROC_PINCONF_BIAS_PULL_UP,
79 IPROC_PINCONF_BIAS_PULL_DOWN,
80 IPROC_PINCON_MAX,
81 };
82
83 enum iproc_pinconf_ctrl_type {
84 IOCTRL_TYPE_AON = 1,
85 IOCTRL_TYPE_CDRU,
86 IOCTRL_TYPE_INVALID,
87 };
88
89 /*
90 * Iproc GPIO core
91 *
92 * @dev: pointer to device
93 * @base: I/O register base for Iproc GPIO controller
94 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
95 * has the PINCONF support implemented outside of the GPIO block
96 * @lock: lock to protect access to I/O registers
97 * @gc: GPIO chip
98 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
99 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
100 * that can be individually muxed to GPIO
101 * @pinconf_disable: contains a list of PINCONF parameters that need to be
102 * disabled
103 * @nr_pinconf_disable: total number of PINCONF parameters that need to be
104 * disabled
105 * @pctl: pointer to pinctrl_dev
106 * @pctldesc: pinctrl descriptor
107 */
108 struct iproc_gpio {
109 struct device *dev;
110
111 void __iomem *base;
112 void __iomem *io_ctrl;
113 enum iproc_pinconf_ctrl_type io_ctrl_type;
114
115 raw_spinlock_t lock;
116
117 struct gpio_chip gc;
118 unsigned num_banks;
119
120 bool pinmux_is_supported;
121
122 enum pin_config_param *pinconf_disable;
123 unsigned int nr_pinconf_disable;
124
125 struct pinctrl_dev *pctl;
126 struct pinctrl_desc pctldesc;
127 };
128
129 /*
130 * Mapping from PINCONF pins to GPIO pins is 1-to-1
131 */
iproc_pin_to_gpio(unsigned pin)132 static inline unsigned iproc_pin_to_gpio(unsigned pin)
133 {
134 return pin;
135 }
136
137 /**
138 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
139 * Iproc GPIO register
140 *
141 * @iproc_gpio: Iproc GPIO device
142 * @reg: register offset
143 * @gpio: GPIO pin
144 * @set: set or clear
145 */
iproc_set_bit(struct iproc_gpio * chip,unsigned int reg,unsigned gpio,bool set)146 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
147 unsigned gpio, bool set)
148 {
149 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
150 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
151 u32 val;
152
153 val = readl(chip->base + offset);
154 if (set)
155 val |= BIT(shift);
156 else
157 val &= ~BIT(shift);
158 writel(val, chip->base + offset);
159 }
160
iproc_get_bit(struct iproc_gpio * chip,unsigned int reg,unsigned gpio)161 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
162 unsigned gpio)
163 {
164 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
165 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
166
167 return !!(readl(chip->base + offset) & BIT(shift));
168 }
169
iproc_gpio_irq_handler(struct irq_desc * desc)170 static void iproc_gpio_irq_handler(struct irq_desc *desc)
171 {
172 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
173 struct iproc_gpio *chip = gpiochip_get_data(gc);
174 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
175 int i, bit;
176
177 chained_irq_enter(irq_chip, desc);
178
179 /* go through the entire GPIO banks and handle all interrupts */
180 for (i = 0; i < chip->num_banks; i++) {
181 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
182 IPROC_GPIO_INT_MSTAT_OFFSET);
183
184 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
185 unsigned pin = NGPIOS_PER_BANK * i + bit;
186 int child_irq = irq_find_mapping(gc->irq.domain, pin);
187
188 /*
189 * Clear the interrupt before invoking the
190 * handler, so we do not leave any window
191 */
192 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
193 IPROC_GPIO_INT_CLR_OFFSET);
194
195 generic_handle_irq(child_irq);
196 }
197 }
198
199 chained_irq_exit(irq_chip, desc);
200 }
201
202
iproc_gpio_irq_ack(struct irq_data * d)203 static void iproc_gpio_irq_ack(struct irq_data *d)
204 {
205 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
206 struct iproc_gpio *chip = gpiochip_get_data(gc);
207 unsigned gpio = d->hwirq;
208 unsigned int offset = IPROC_GPIO_REG(gpio,
209 IPROC_GPIO_INT_CLR_OFFSET);
210 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
211 u32 val = BIT(shift);
212
213 writel(val, chip->base + offset);
214 }
215
216 /**
217 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
218 *
219 * @d: IRQ chip data
220 * @unmask: mask/unmask GPIO interrupt
221 */
iproc_gpio_irq_set_mask(struct irq_data * d,bool unmask)222 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
223 {
224 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
225 struct iproc_gpio *chip = gpiochip_get_data(gc);
226 unsigned gpio = d->hwirq;
227
228 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
229 }
230
iproc_gpio_irq_mask(struct irq_data * d)231 static void iproc_gpio_irq_mask(struct irq_data *d)
232 {
233 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
234 struct iproc_gpio *chip = gpiochip_get_data(gc);
235 unsigned long flags;
236
237 raw_spin_lock_irqsave(&chip->lock, flags);
238 iproc_gpio_irq_set_mask(d, false);
239 raw_spin_unlock_irqrestore(&chip->lock, flags);
240 }
241
iproc_gpio_irq_unmask(struct irq_data * d)242 static void iproc_gpio_irq_unmask(struct irq_data *d)
243 {
244 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
245 struct iproc_gpio *chip = gpiochip_get_data(gc);
246 unsigned long flags;
247
248 raw_spin_lock_irqsave(&chip->lock, flags);
249 iproc_gpio_irq_set_mask(d, true);
250 raw_spin_unlock_irqrestore(&chip->lock, flags);
251 }
252
iproc_gpio_irq_set_type(struct irq_data * d,unsigned int type)253 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
254 {
255 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
256 struct iproc_gpio *chip = gpiochip_get_data(gc);
257 unsigned gpio = d->hwirq;
258 bool level_triggered = false;
259 bool dual_edge = false;
260 bool rising_or_high = false;
261 unsigned long flags;
262
263 switch (type & IRQ_TYPE_SENSE_MASK) {
264 case IRQ_TYPE_EDGE_RISING:
265 rising_or_high = true;
266 break;
267
268 case IRQ_TYPE_EDGE_FALLING:
269 break;
270
271 case IRQ_TYPE_EDGE_BOTH:
272 dual_edge = true;
273 break;
274
275 case IRQ_TYPE_LEVEL_HIGH:
276 level_triggered = true;
277 rising_or_high = true;
278 break;
279
280 case IRQ_TYPE_LEVEL_LOW:
281 level_triggered = true;
282 break;
283
284 default:
285 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
286 type);
287 return -EINVAL;
288 }
289
290 raw_spin_lock_irqsave(&chip->lock, flags);
291 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
292 level_triggered);
293 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
294 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
295 rising_or_high);
296 raw_spin_unlock_irqrestore(&chip->lock, flags);
297
298 dev_dbg(chip->dev,
299 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
300 gpio, level_triggered, dual_edge, rising_or_high);
301
302 return 0;
303 }
304
305 static struct irq_chip iproc_gpio_irq_chip = {
306 .name = "bcm-iproc-gpio",
307 .irq_ack = iproc_gpio_irq_ack,
308 .irq_mask = iproc_gpio_irq_mask,
309 .irq_unmask = iproc_gpio_irq_unmask,
310 .irq_set_type = iproc_gpio_irq_set_type,
311 };
312
313 /*
314 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
315 */
iproc_gpio_request(struct gpio_chip * gc,unsigned offset)316 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
317 {
318 struct iproc_gpio *chip = gpiochip_get_data(gc);
319 unsigned gpio = gc->base + offset;
320
321 /* not all Iproc GPIO pins can be muxed individually */
322 if (!chip->pinmux_is_supported)
323 return 0;
324
325 return pinctrl_gpio_request(gpio);
326 }
327
iproc_gpio_free(struct gpio_chip * gc,unsigned offset)328 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
329 {
330 struct iproc_gpio *chip = gpiochip_get_data(gc);
331 unsigned gpio = gc->base + offset;
332
333 if (!chip->pinmux_is_supported)
334 return;
335
336 pinctrl_gpio_free(gpio);
337 }
338
iproc_gpio_direction_input(struct gpio_chip * gc,unsigned gpio)339 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
340 {
341 struct iproc_gpio *chip = gpiochip_get_data(gc);
342 unsigned long flags;
343
344 raw_spin_lock_irqsave(&chip->lock, flags);
345 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
346 raw_spin_unlock_irqrestore(&chip->lock, flags);
347
348 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
349
350 return 0;
351 }
352
iproc_gpio_direction_output(struct gpio_chip * gc,unsigned gpio,int val)353 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
354 int val)
355 {
356 struct iproc_gpio *chip = gpiochip_get_data(gc);
357 unsigned long flags;
358
359 raw_spin_lock_irqsave(&chip->lock, flags);
360 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
361 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
362 raw_spin_unlock_irqrestore(&chip->lock, flags);
363
364 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
365
366 return 0;
367 }
368
iproc_gpio_set(struct gpio_chip * gc,unsigned gpio,int val)369 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
370 {
371 struct iproc_gpio *chip = gpiochip_get_data(gc);
372 unsigned long flags;
373
374 raw_spin_lock_irqsave(&chip->lock, flags);
375 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
376 raw_spin_unlock_irqrestore(&chip->lock, flags);
377
378 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
379 }
380
iproc_gpio_get(struct gpio_chip * gc,unsigned gpio)381 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
382 {
383 struct iproc_gpio *chip = gpiochip_get_data(gc);
384 unsigned int offset = IPROC_GPIO_REG(gpio,
385 IPROC_GPIO_DATA_IN_OFFSET);
386 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
387
388 return !!(readl(chip->base + offset) & BIT(shift));
389 }
390
391 /*
392 * Mapping of the iProc PINCONF parameters to the generic pin configuration
393 * parameters
394 */
395 static const enum pin_config_param iproc_pinconf_disable_map[] = {
396 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
397 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
398 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
399 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
400 };
401
iproc_pinconf_param_is_disabled(struct iproc_gpio * chip,enum pin_config_param param)402 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
403 enum pin_config_param param)
404 {
405 unsigned int i;
406
407 if (!chip->nr_pinconf_disable)
408 return false;
409
410 for (i = 0; i < chip->nr_pinconf_disable; i++)
411 if (chip->pinconf_disable[i] == param)
412 return true;
413
414 return false;
415 }
416
iproc_pinconf_disable_map_create(struct iproc_gpio * chip,unsigned long disable_mask)417 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
418 unsigned long disable_mask)
419 {
420 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
421 unsigned int bit, nbits = 0;
422
423 /* figure out total number of PINCONF parameters to disable */
424 for_each_set_bit(bit, &disable_mask, map_size)
425 nbits++;
426
427 if (!nbits)
428 return 0;
429
430 /*
431 * Allocate an array to store PINCONF parameters that need to be
432 * disabled
433 */
434 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
435 sizeof(*chip->pinconf_disable),
436 GFP_KERNEL);
437 if (!chip->pinconf_disable)
438 return -ENOMEM;
439
440 chip->nr_pinconf_disable = nbits;
441
442 /* now store these parameters */
443 nbits = 0;
444 for_each_set_bit(bit, &disable_mask, map_size)
445 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
446
447 return 0;
448 }
449
iproc_get_groups_count(struct pinctrl_dev * pctldev)450 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
451 {
452 return 1;
453 }
454
455 /*
456 * Only one group: "gpio_grp", since this local pinctrl device only performs
457 * GPIO specific PINCONF configurations
458 */
iproc_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)459 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
460 unsigned selector)
461 {
462 return "gpio_grp";
463 }
464
465 static const struct pinctrl_ops iproc_pctrl_ops = {
466 .get_groups_count = iproc_get_groups_count,
467 .get_group_name = iproc_get_group_name,
468 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
469 .dt_free_map = pinctrl_utils_free_map,
470 };
471
iproc_gpio_set_pull(struct iproc_gpio * chip,unsigned gpio,bool disable,bool pull_up)472 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
473 bool disable, bool pull_up)
474 {
475 void __iomem *base;
476 unsigned long flags;
477 unsigned int shift;
478 u32 val_1, val_2;
479
480 raw_spin_lock_irqsave(&chip->lock, flags);
481 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
482 base = chip->io_ctrl;
483 shift = IPROC_GPIO_SHIFT(gpio);
484
485 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
486 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
487 if (disable) {
488 /* no pull-up or pull-down */
489 val_1 &= ~BIT(shift);
490 val_2 &= ~BIT(shift);
491 } else if (pull_up) {
492 val_1 |= BIT(shift);
493 val_2 &= ~BIT(shift);
494 } else {
495 val_1 &= ~BIT(shift);
496 val_2 |= BIT(shift);
497 }
498 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
499 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
500 } else {
501 if (disable) {
502 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
503 false);
504 } else {
505 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
506 pull_up);
507 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
508 true);
509 }
510 }
511
512 raw_spin_unlock_irqrestore(&chip->lock, flags);
513 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
514
515 return 0;
516 }
517
iproc_gpio_get_pull(struct iproc_gpio * chip,unsigned gpio,bool * disable,bool * pull_up)518 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
519 bool *disable, bool *pull_up)
520 {
521 void __iomem *base;
522 unsigned long flags;
523 unsigned int shift;
524 u32 val_1, val_2;
525
526 raw_spin_lock_irqsave(&chip->lock, flags);
527 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
528 base = chip->io_ctrl;
529 shift = IPROC_GPIO_SHIFT(gpio);
530
531 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
532 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
533
534 *pull_up = val_1 ? true : false;
535 *disable = (val_1 | val_2) ? false : true;
536
537 } else {
538 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
539 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
540 }
541 raw_spin_unlock_irqrestore(&chip->lock, flags);
542 }
543
544 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
545 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
546 ((type) == IOCTRL_TYPE_CDRU) ? \
547 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
548 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
549
iproc_gpio_set_strength(struct iproc_gpio * chip,unsigned gpio,unsigned strength)550 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
551 unsigned strength)
552 {
553 void __iomem *base;
554 unsigned int i, offset, shift;
555 u32 val;
556 unsigned long flags;
557
558 /* make sure drive strength is supported */
559 if (strength < 2 || strength > 16 || (strength % 2))
560 return -ENOTSUPP;
561
562 if (chip->io_ctrl) {
563 base = chip->io_ctrl;
564 } else {
565 base = chip->base;
566 }
567
568 shift = IPROC_GPIO_SHIFT(gpio);
569
570 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
571 strength);
572
573 raw_spin_lock_irqsave(&chip->lock, flags);
574 strength = (strength / 2) - 1;
575 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
576 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
577 val = readl(base + offset);
578 val &= ~BIT(shift);
579 val |= ((strength >> i) & 0x1) << shift;
580 writel(val, base + offset);
581 }
582 raw_spin_unlock_irqrestore(&chip->lock, flags);
583
584 return 0;
585 }
586
iproc_gpio_get_strength(struct iproc_gpio * chip,unsigned gpio,u16 * strength)587 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
588 u16 *strength)
589 {
590 void __iomem *base;
591 unsigned int i, offset, shift;
592 u32 val;
593 unsigned long flags;
594
595 if (chip->io_ctrl) {
596 base = chip->io_ctrl;
597 } else {
598 base = chip->base;
599 }
600
601 shift = IPROC_GPIO_SHIFT(gpio);
602
603 raw_spin_lock_irqsave(&chip->lock, flags);
604 *strength = 0;
605 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
606 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
607 val = readl(base + offset) & BIT(shift);
608 val >>= shift;
609 *strength += (val << i);
610 }
611
612 /* convert to mA */
613 *strength = (*strength + 1) * 2;
614 raw_spin_unlock_irqrestore(&chip->lock, flags);
615
616 return 0;
617 }
618
iproc_pin_config_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)619 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
620 unsigned long *config)
621 {
622 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
623 enum pin_config_param param = pinconf_to_config_param(*config);
624 unsigned gpio = iproc_pin_to_gpio(pin);
625 u16 arg;
626 bool disable, pull_up;
627 int ret;
628
629 if (iproc_pinconf_param_is_disabled(chip, param))
630 return -ENOTSUPP;
631
632 switch (param) {
633 case PIN_CONFIG_BIAS_DISABLE:
634 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
635 if (disable)
636 return 0;
637 else
638 return -EINVAL;
639
640 case PIN_CONFIG_BIAS_PULL_UP:
641 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
642 if (!disable && pull_up)
643 return 0;
644 else
645 return -EINVAL;
646
647 case PIN_CONFIG_BIAS_PULL_DOWN:
648 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
649 if (!disable && !pull_up)
650 return 0;
651 else
652 return -EINVAL;
653
654 case PIN_CONFIG_DRIVE_STRENGTH:
655 ret = iproc_gpio_get_strength(chip, gpio, &arg);
656 if (ret)
657 return ret;
658 *config = pinconf_to_config_packed(param, arg);
659
660 return 0;
661
662 default:
663 return -ENOTSUPP;
664 }
665
666 return -ENOTSUPP;
667 }
668
iproc_pin_config_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)669 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
670 unsigned long *configs, unsigned num_configs)
671 {
672 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
673 enum pin_config_param param;
674 u32 arg;
675 unsigned i, gpio = iproc_pin_to_gpio(pin);
676 int ret = -ENOTSUPP;
677
678 for (i = 0; i < num_configs; i++) {
679 param = pinconf_to_config_param(configs[i]);
680
681 if (iproc_pinconf_param_is_disabled(chip, param))
682 return -ENOTSUPP;
683
684 arg = pinconf_to_config_argument(configs[i]);
685
686 switch (param) {
687 case PIN_CONFIG_BIAS_DISABLE:
688 ret = iproc_gpio_set_pull(chip, gpio, true, false);
689 if (ret < 0)
690 goto out;
691 break;
692
693 case PIN_CONFIG_BIAS_PULL_UP:
694 ret = iproc_gpio_set_pull(chip, gpio, false, true);
695 if (ret < 0)
696 goto out;
697 break;
698
699 case PIN_CONFIG_BIAS_PULL_DOWN:
700 ret = iproc_gpio_set_pull(chip, gpio, false, false);
701 if (ret < 0)
702 goto out;
703 break;
704
705 case PIN_CONFIG_DRIVE_STRENGTH:
706 ret = iproc_gpio_set_strength(chip, gpio, arg);
707 if (ret < 0)
708 goto out;
709 break;
710
711 default:
712 dev_err(chip->dev, "invalid configuration\n");
713 return -ENOTSUPP;
714 }
715 } /* for each config */
716
717 out:
718 return ret;
719 }
720
721 static const struct pinconf_ops iproc_pconf_ops = {
722 .is_generic = true,
723 .pin_config_get = iproc_pin_config_get,
724 .pin_config_set = iproc_pin_config_set,
725 };
726
727 /*
728 * Iproc GPIO controller supports some PINCONF related configurations such as
729 * pull up, pull down, and drive strength, when the pin is configured to GPIO
730 *
731 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
732 * local GPIO pins
733 */
iproc_gpio_register_pinconf(struct iproc_gpio * chip)734 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
735 {
736 struct pinctrl_desc *pctldesc = &chip->pctldesc;
737 struct pinctrl_pin_desc *pins;
738 struct gpio_chip *gc = &chip->gc;
739 int i;
740
741 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
742 if (!pins)
743 return -ENOMEM;
744
745 for (i = 0; i < gc->ngpio; i++) {
746 pins[i].number = i;
747 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
748 "gpio-%d", i);
749 if (!pins[i].name)
750 return -ENOMEM;
751 }
752
753 pctldesc->name = dev_name(chip->dev);
754 pctldesc->pctlops = &iproc_pctrl_ops;
755 pctldesc->pins = pins;
756 pctldesc->npins = gc->ngpio;
757 pctldesc->confops = &iproc_pconf_ops;
758
759 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
760 if (IS_ERR(chip->pctl)) {
761 dev_err(chip->dev, "unable to register pinctrl device\n");
762 return PTR_ERR(chip->pctl);
763 }
764
765 return 0;
766 }
767
768 static const struct of_device_id iproc_gpio_of_match[] = {
769 { .compatible = "brcm,iproc-gpio" },
770 { .compatible = "brcm,cygnus-ccm-gpio" },
771 { .compatible = "brcm,cygnus-asiu-gpio" },
772 { .compatible = "brcm,cygnus-crmu-gpio" },
773 { .compatible = "brcm,iproc-nsp-gpio" },
774 { .compatible = "brcm,iproc-stingray-gpio" },
775 { /* sentinel */ }
776 };
777
iproc_gpio_probe(struct platform_device * pdev)778 static int iproc_gpio_probe(struct platform_device *pdev)
779 {
780 struct device *dev = &pdev->dev;
781 struct resource *res;
782 struct iproc_gpio *chip;
783 struct gpio_chip *gc;
784 u32 ngpios, pinconf_disable_mask = 0;
785 int irq, ret;
786 bool no_pinconf = false;
787 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
788
789 /* NSP does not support drive strength config */
790 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
791 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
792 /* Stingray does not support pinconf in this controller */
793 else if (of_device_is_compatible(dev->of_node,
794 "brcm,iproc-stingray-gpio"))
795 no_pinconf = true;
796
797 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
798 if (!chip)
799 return -ENOMEM;
800
801 chip->dev = dev;
802 platform_set_drvdata(pdev, chip);
803
804 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
805 chip->base = devm_ioremap_resource(dev, res);
806 if (IS_ERR(chip->base)) {
807 dev_err(dev, "unable to map I/O memory\n");
808 return PTR_ERR(chip->base);
809 }
810
811 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
812 if (res) {
813 chip->io_ctrl = devm_ioremap_resource(dev, res);
814 if (IS_ERR(chip->io_ctrl)) {
815 dev_err(dev, "unable to map I/O memory\n");
816 return PTR_ERR(chip->io_ctrl);
817 }
818 if (of_device_is_compatible(dev->of_node,
819 "brcm,cygnus-ccm-gpio"))
820 io_ctrl_type = IOCTRL_TYPE_CDRU;
821 else
822 io_ctrl_type = IOCTRL_TYPE_AON;
823 }
824
825 chip->io_ctrl_type = io_ctrl_type;
826
827 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
828 dev_err(&pdev->dev, "missing ngpios DT property\n");
829 return -ENODEV;
830 }
831
832 raw_spin_lock_init(&chip->lock);
833
834 gc = &chip->gc;
835 gc->base = -1;
836 gc->ngpio = ngpios;
837 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
838 gc->label = dev_name(dev);
839 gc->parent = dev;
840 gc->of_node = dev->of_node;
841 gc->request = iproc_gpio_request;
842 gc->free = iproc_gpio_free;
843 gc->direction_input = iproc_gpio_direction_input;
844 gc->direction_output = iproc_gpio_direction_output;
845 gc->set = iproc_gpio_set;
846 gc->get = iproc_gpio_get;
847
848 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
849 "gpio-ranges");
850
851 ret = gpiochip_add_data(gc, chip);
852 if (ret < 0) {
853 dev_err(dev, "unable to add GPIO chip\n");
854 return ret;
855 }
856
857 if (!no_pinconf) {
858 ret = iproc_gpio_register_pinconf(chip);
859 if (ret) {
860 dev_err(dev, "unable to register pinconf\n");
861 goto err_rm_gpiochip;
862 }
863
864 if (pinconf_disable_mask) {
865 ret = iproc_pinconf_disable_map_create(chip,
866 pinconf_disable_mask);
867 if (ret) {
868 dev_err(dev,
869 "unable to create pinconf disable map\n");
870 goto err_rm_gpiochip;
871 }
872 }
873 }
874
875 /* optional GPIO interrupt support */
876 irq = platform_get_irq(pdev, 0);
877 if (irq) {
878 ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0,
879 handle_simple_irq, IRQ_TYPE_NONE);
880 if (ret) {
881 dev_err(dev, "no GPIO irqchip\n");
882 goto err_rm_gpiochip;
883 }
884
885 gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq,
886 iproc_gpio_irq_handler);
887 }
888
889 return 0;
890
891 err_rm_gpiochip:
892 gpiochip_remove(gc);
893
894 return ret;
895 }
896
897 static struct platform_driver iproc_gpio_driver = {
898 .driver = {
899 .name = "iproc-gpio",
900 .of_match_table = iproc_gpio_of_match,
901 },
902 .probe = iproc_gpio_probe,
903 };
904
iproc_gpio_init(void)905 static int __init iproc_gpio_init(void)
906 {
907 return platform_driver_register(&iproc_gpio_driver);
908 }
909 arch_initcall_sync(iproc_gpio_init);
910