1 /*
2 * HiSilicon Hixxxx UFS Driver
3 *
4 * Copyright (c) 2016-2017 Linaro Ltd.
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
6 *
7 * Released under the GPLv2 only.
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11 #include <linux/time.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17
18 #include "ufshcd.h"
19 #include "ufshcd-pltfrm.h"
20 #include "unipro.h"
21 #include "ufs-hisi.h"
22 #include "ufshci.h"
23 #include "ufs_quirks.h"
24
ufs_hisi_check_hibern8(struct ufs_hba * hba)25 static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
26 {
27 int err = 0;
28 u32 tx_fsm_val_0 = 0;
29 u32 tx_fsm_val_1 = 0;
30 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
31
32 do {
33 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
34 &tx_fsm_val_0);
35 err |= ufshcd_dme_get(hba,
36 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
37 if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
38 tx_fsm_val_1 == TX_FSM_HIBERN8))
39 break;
40
41 /* sleep for max. 200us */
42 usleep_range(100, 200);
43 } while (time_before(jiffies, timeout));
44
45 /*
46 * we might have scheduled out for long during polling so
47 * check the state again.
48 */
49 if (time_after(jiffies, timeout)) {
50 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
51 &tx_fsm_val_0);
52 err |= ufshcd_dme_get(hba,
53 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
54 }
55
56 if (err) {
57 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
58 __func__, err);
59 } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
60 tx_fsm_val_1 != TX_FSM_HIBERN8) {
61 err = -1;
62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
63 __func__, tx_fsm_val_0, tx_fsm_val_1);
64 }
65
66 return err;
67 }
68
ufs_hi3660_clk_init(struct ufs_hba * hba)69 static void ufs_hi3660_clk_init(struct ufs_hba *hba)
70 {
71 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
72
73 ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
74 if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN)
75 mdelay(1);
76 /* use abb clk */
77 ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL);
78 ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN);
79 /* open mphy ref clk */
80 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
81 }
82
ufs_hi3660_soc_init(struct ufs_hba * hba)83 static void ufs_hi3660_soc_init(struct ufs_hba *hba)
84 {
85 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
86 u32 reg;
87
88 if (!IS_ERR(host->rst))
89 reset_control_assert(host->rst);
90
91 /* HC_PSW powerup */
92 ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL);
93 udelay(10);
94 /* notify PWR ready */
95 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL);
96 ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0,
97 UFS_DEVICE_RESET_CTRL);
98
99 reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL);
100 reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK;
101 /* set cfg clk freq */
102 ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL);
103 /* set ref clk freq */
104 ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL);
105 /* bypass ufs clk gate */
106 ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS,
107 CLOCK_GATE_BYPASS);
108 ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL);
109
110 /* open psw clk */
111 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL);
112 /* disable ufshc iso */
113 ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL);
114 /* disable phy iso */
115 ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN);
116 /* notice iso disable */
117 ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL);
118
119 /* disable lp_reset_n */
120 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN);
121 mdelay(1);
122
123 ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET,
124 UFS_DEVICE_RESET_CTRL);
125
126 msleep(20);
127
128 /*
129 * enable the fix of linereset recovery,
130 * and enable rx_reset/tx_rest beat
131 * enable ref_clk_en override(bit5) &
132 * override value = 1(bit4), with mask
133 */
134 ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL);
135
136 if (!IS_ERR(host->rst))
137 reset_control_deassert(host->rst);
138 }
139
ufs_hisi_link_startup_pre_change(struct ufs_hba * hba)140 static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
141 {
142 int err;
143 uint32_t value;
144 uint32_t reg;
145
146 /* Unipro VS_mphy_disable */
147 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1);
148 /* PA_HSSeries */
149 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2);
150 /* MPHY CBRATESEL */
151 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1);
152 /* MPHY CBOVRCTRL2 */
153 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
154 /* MPHY CBOVRCTRL3 */
155 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
156 /* Unipro VS_MphyCfgUpdt */
157 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
158 /* MPHY RXOVRCTRL4 rx0 */
159 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58);
160 /* MPHY RXOVRCTRL4 rx1 */
161 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58);
162 /* MPHY RXOVRCTRL5 rx0 */
163 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB);
164 /* MPHY RXOVRCTRL5 rx1 */
165 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB);
166 /* MPHY RXSQCONTROL rx0 */
167 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1);
168 /* MPHY RXSQCONTROL rx1 */
169 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1);
170 /* Unipro VS_MphyCfgUpdt */
171 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
172
173 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
174 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
175
176 /* Tactive RX */
177 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
178 /* Tactive RX */
179 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
180
181 /* Gear3 Synclength */
182 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
183 /* Gear3 Synclength */
184 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4F);
185 /* Gear2 Synclength */
186 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4F);
187 /* Gear2 Synclength */
188 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4F);
189 /* Gear1 Synclength */
190 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x4), 0x4F);
191 /* Gear1 Synclength */
192 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x5), 0x4F);
193 /* Thibernate Tx */
194 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5);
195 /* Thibernate Tx */
196 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5);
197
198 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
199 /* Unipro VS_mphy_disable */
200 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value);
201 if (value != 0x1)
202 dev_info(hba->dev,
203 "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value);
204
205 /* Unipro VS_mphy_disable */
206 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
207 err = ufs_hisi_check_hibern8(hba);
208 if (err)
209 dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
210
211 ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
212
213 /* disable auto H8 */
214 reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
215 reg = reg & (~UFS_AHIT_AH8ITV_MASK);
216 ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
217
218 /* Unipro PA_Local_TX_LCC_Enable */
219 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x155E, 0x0), 0x0);
220 /* close Unipro VS_Mk2ExtnSupport */
221 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0);
222 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value);
223 if (value != 0) {
224 /* Ensure close success */
225 dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n");
226 }
227
228 return err;
229 }
230
ufs_hisi_link_startup_post_change(struct ufs_hba * hba)231 static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
232 {
233 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
234
235 /* Unipro DL_AFC0CreditThreshold */
236 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0);
237 /* Unipro DL_TC0OutAckThreshold */
238 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0);
239 /* Unipro DL_TC0TXFCThreshold */
240 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9);
241
242 /* not bypass ufs clk gate */
243 ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS,
244 CLOCK_GATE_BYPASS);
245 ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS,
246 UFS_SYSCTRL);
247
248 /* select received symbol cnt */
249 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000);
250 /* reset counter0 and enable */
251 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005);
252
253 return 0;
254 }
255
ufs_hi3660_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)256 static int ufs_hi3660_link_startup_notify(struct ufs_hba *hba,
257 enum ufs_notify_change_status status)
258 {
259 int err = 0;
260
261 switch (status) {
262 case PRE_CHANGE:
263 err = ufs_hisi_link_startup_pre_change(hba);
264 break;
265 case POST_CHANGE:
266 err = ufs_hisi_link_startup_post_change(hba);
267 break;
268 default:
269 break;
270 }
271
272 return err;
273 }
274
275 struct ufs_hisi_dev_params {
276 u32 pwm_rx_gear; /* pwm rx gear to work in */
277 u32 pwm_tx_gear; /* pwm tx gear to work in */
278 u32 hs_rx_gear; /* hs rx gear to work in */
279 u32 hs_tx_gear; /* hs tx gear to work in */
280 u32 rx_lanes; /* number of rx lanes */
281 u32 tx_lanes; /* number of tx lanes */
282 u32 rx_pwr_pwm; /* rx pwm working pwr */
283 u32 tx_pwr_pwm; /* tx pwm working pwr */
284 u32 rx_pwr_hs; /* rx hs working pwr */
285 u32 tx_pwr_hs; /* tx hs working pwr */
286 u32 hs_rate; /* rate A/B to work in HS */
287 u32 desired_working_mode;
288 };
289
ufs_hisi_get_pwr_dev_param(struct ufs_hisi_dev_params * hisi_param,struct ufs_pa_layer_attr * dev_max,struct ufs_pa_layer_attr * agreed_pwr)290 static int ufs_hisi_get_pwr_dev_param(
291 struct ufs_hisi_dev_params *hisi_param,
292 struct ufs_pa_layer_attr *dev_max,
293 struct ufs_pa_layer_attr *agreed_pwr)
294 {
295 int min_hisi_gear;
296 int min_dev_gear;
297 bool is_dev_sup_hs = false;
298 bool is_hisi_max_hs = false;
299
300 if (dev_max->pwr_rx == FASTAUTO_MODE || dev_max->pwr_rx == FAST_MODE)
301 is_dev_sup_hs = true;
302
303 if (hisi_param->desired_working_mode == FAST) {
304 is_hisi_max_hs = true;
305 min_hisi_gear = min_t(u32, hisi_param->hs_rx_gear,
306 hisi_param->hs_tx_gear);
307 } else {
308 min_hisi_gear = min_t(u32, hisi_param->pwm_rx_gear,
309 hisi_param->pwm_tx_gear);
310 }
311
312 /*
313 * device doesn't support HS but
314 * hisi_param->desired_working_mode is HS,
315 * thus device and hisi_param don't agree
316 */
317 if (!is_dev_sup_hs && is_hisi_max_hs) {
318 pr_err("%s: device not support HS\n", __func__);
319 return -ENOTSUPP;
320 } else if (is_dev_sup_hs && is_hisi_max_hs) {
321 /*
322 * since device supports HS, it supports FAST_MODE.
323 * since hisi_param->desired_working_mode is also HS
324 * then final decision (FAST/FASTAUTO) is done according
325 * to hisi_params as it is the restricting factor
326 */
327 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
328 hisi_param->rx_pwr_hs;
329 } else {
330 /*
331 * here hisi_param->desired_working_mode is PWM.
332 * it doesn't matter whether device supports HS or PWM,
333 * in both cases hisi_param->desired_working_mode will
334 * determine the mode
335 */
336 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
337 hisi_param->rx_pwr_pwm;
338 }
339
340 /*
341 * we would like tx to work in the minimum number of lanes
342 * between device capability and vendor preferences.
343 * the same decision will be made for rx
344 */
345 agreed_pwr->lane_tx =
346 min_t(u32, dev_max->lane_tx, hisi_param->tx_lanes);
347 agreed_pwr->lane_rx =
348 min_t(u32, dev_max->lane_rx, hisi_param->rx_lanes);
349
350 /* device maximum gear is the minimum between device rx and tx gears */
351 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
352
353 /*
354 * if both device capabilities and vendor pre-defined preferences are
355 * both HS or both PWM then set the minimum gear to be the chosen
356 * working gear.
357 * if one is PWM and one is HS then the one that is PWM get to decide
358 * what is the gear, as it is the one that also decided previously what
359 * pwr the device will be configured to.
360 */
361 if ((is_dev_sup_hs && is_hisi_max_hs) ||
362 (!is_dev_sup_hs && !is_hisi_max_hs))
363 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
364 min_t(u32, min_dev_gear, min_hisi_gear);
365 else
366 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_hisi_gear;
367
368 agreed_pwr->hs_rate = hisi_param->hs_rate;
369
370 pr_info("ufs final power mode: gear = %d, lane = %d, pwr = %d, rate = %d\n",
371 agreed_pwr->gear_rx, agreed_pwr->lane_rx, agreed_pwr->pwr_rx,
372 agreed_pwr->hs_rate);
373 return 0;
374 }
375
ufs_hisi_set_dev_cap(struct ufs_hisi_dev_params * hisi_param)376 static void ufs_hisi_set_dev_cap(struct ufs_hisi_dev_params *hisi_param)
377 {
378 hisi_param->rx_lanes = UFS_HISI_LIMIT_NUM_LANES_RX;
379 hisi_param->tx_lanes = UFS_HISI_LIMIT_NUM_LANES_TX;
380 hisi_param->hs_rx_gear = UFS_HISI_LIMIT_HSGEAR_RX;
381 hisi_param->hs_tx_gear = UFS_HISI_LIMIT_HSGEAR_TX;
382 hisi_param->pwm_rx_gear = UFS_HISI_LIMIT_PWMGEAR_RX;
383 hisi_param->pwm_tx_gear = UFS_HISI_LIMIT_PWMGEAR_TX;
384 hisi_param->rx_pwr_pwm = UFS_HISI_LIMIT_RX_PWR_PWM;
385 hisi_param->tx_pwr_pwm = UFS_HISI_LIMIT_TX_PWR_PWM;
386 hisi_param->rx_pwr_hs = UFS_HISI_LIMIT_RX_PWR_HS;
387 hisi_param->tx_pwr_hs = UFS_HISI_LIMIT_TX_PWR_HS;
388 hisi_param->hs_rate = UFS_HISI_LIMIT_HS_RATE;
389 hisi_param->desired_working_mode = UFS_HISI_LIMIT_DESIRED_MODE;
390 }
391
ufs_hisi_pwr_change_pre_change(struct ufs_hba * hba)392 static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
393 {
394 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
395 pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
396 /* VS_DebugSaveConfigTime */
397 ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10);
398 /* sync length */
399 ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48);
400 }
401
402 /* update */
403 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1);
404 /* PA_TxSkip */
405 ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0);
406 /*PA_PWRModeUserData0 = 8191, default is 0*/
407 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191);
408 /*PA_PWRModeUserData1 = 65535, default is 0*/
409 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535);
410 /*PA_PWRModeUserData2 = 32767, default is 0*/
411 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767);
412 /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/
413 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191);
414 /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/
415 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535);
416 /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/
417 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767);
418 /*PA_PWRModeUserData3 = 8191, default is 0*/
419 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191);
420 /*PA_PWRModeUserData4 = 65535, default is 0*/
421 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535);
422 /*PA_PWRModeUserData5 = 32767, default is 0*/
423 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767);
424 /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/
425 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191);
426 /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/
427 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535);
428 /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/
429 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
430 }
431
ufs_hi3660_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)432 static int ufs_hi3660_pwr_change_notify(struct ufs_hba *hba,
433 enum ufs_notify_change_status status,
434 struct ufs_pa_layer_attr *dev_max_params,
435 struct ufs_pa_layer_attr *dev_req_params)
436 {
437 struct ufs_hisi_dev_params ufs_hisi_cap;
438 int ret = 0;
439
440 if (!dev_req_params) {
441 dev_err(hba->dev,
442 "%s: incoming dev_req_params is NULL\n", __func__);
443 ret = -EINVAL;
444 goto out;
445 }
446
447 switch (status) {
448 case PRE_CHANGE:
449 ufs_hisi_set_dev_cap(&ufs_hisi_cap);
450 ret = ufs_hisi_get_pwr_dev_param(
451 &ufs_hisi_cap, dev_max_params, dev_req_params);
452 if (ret) {
453 dev_err(hba->dev,
454 "%s: failed to determine capabilities\n", __func__);
455 goto out;
456 }
457
458 ufs_hisi_pwr_change_pre_change(hba);
459 break;
460 case POST_CHANGE:
461 break;
462 default:
463 ret = -EINVAL;
464 break;
465 }
466 out:
467 return ret;
468 }
469
ufs_hisi_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)470 static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
471 {
472 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
473
474 if (ufshcd_is_runtime_pm(pm_op))
475 return 0;
476
477 if (host->in_suspend) {
478 WARN_ON(1);
479 return 0;
480 }
481
482 ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
483 udelay(10);
484 /* set ref_dig_clk override of PHY PCS to 0 */
485 ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL);
486
487 host->in_suspend = true;
488
489 return 0;
490 }
491
ufs_hisi_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)492 static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
493 {
494 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
495
496 if (!host->in_suspend)
497 return 0;
498
499 /* set ref_dig_clk override of PHY PCS to 1 */
500 ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL);
501 udelay(10);
502 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
503
504 host->in_suspend = false;
505 return 0;
506 }
507
ufs_hisi_get_resource(struct ufs_hisi_host * host)508 static int ufs_hisi_get_resource(struct ufs_hisi_host *host)
509 {
510 struct resource *mem_res;
511 struct device *dev = host->hba->dev;
512 struct platform_device *pdev = to_platform_device(dev);
513
514 /* get resource of ufs sys ctrl */
515 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
516 host->ufs_sys_ctrl = devm_ioremap_resource(dev, mem_res);
517 if (IS_ERR(host->ufs_sys_ctrl))
518 return PTR_ERR(host->ufs_sys_ctrl);
519
520 return 0;
521 }
522
ufs_hisi_set_pm_lvl(struct ufs_hba * hba)523 static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba)
524 {
525 hba->rpm_lvl = UFS_PM_LVL_1;
526 hba->spm_lvl = UFS_PM_LVL_3;
527 }
528
529 /**
530 * ufs_hisi_init_common
531 * @hba: host controller instance
532 */
ufs_hisi_init_common(struct ufs_hba * hba)533 static int ufs_hisi_init_common(struct ufs_hba *hba)
534 {
535 int err = 0;
536 struct device *dev = hba->dev;
537 struct ufs_hisi_host *host;
538
539 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
540 if (!host)
541 return -ENOMEM;
542
543 host->hba = hba;
544 ufshcd_set_variant(hba, host);
545
546 host->rst = devm_reset_control_get(dev, "rst");
547 if (IS_ERR(host->rst)) {
548 dev_err(dev, "%s: failed to get reset control\n", __func__);
549 return PTR_ERR(host->rst);
550 }
551
552 ufs_hisi_set_pm_lvl(hba);
553
554 err = ufs_hisi_get_resource(host);
555 if (err) {
556 ufshcd_set_variant(hba, NULL);
557 return err;
558 }
559
560 return 0;
561 }
562
ufs_hi3660_init(struct ufs_hba * hba)563 static int ufs_hi3660_init(struct ufs_hba *hba)
564 {
565 int ret = 0;
566 struct device *dev = hba->dev;
567
568 ret = ufs_hisi_init_common(hba);
569 if (ret) {
570 dev_err(dev, "%s: ufs common init fail\n", __func__);
571 return ret;
572 }
573
574 ufs_hi3660_clk_init(hba);
575
576 ufs_hi3660_soc_init(hba);
577
578 return 0;
579 }
580
581 static struct ufs_hba_variant_ops ufs_hba_hisi_vops = {
582 .name = "hi3660",
583 .init = ufs_hi3660_init,
584 .link_startup_notify = ufs_hi3660_link_startup_notify,
585 .pwr_change_notify = ufs_hi3660_pwr_change_notify,
586 .suspend = ufs_hisi_suspend,
587 .resume = ufs_hisi_resume,
588 };
589
ufs_hisi_probe(struct platform_device * pdev)590 static int ufs_hisi_probe(struct platform_device *pdev)
591 {
592 return ufshcd_pltfrm_init(pdev, &ufs_hba_hisi_vops);
593 }
594
ufs_hisi_remove(struct platform_device * pdev)595 static int ufs_hisi_remove(struct platform_device *pdev)
596 {
597 struct ufs_hba *hba = platform_get_drvdata(pdev);
598
599 ufshcd_remove(hba);
600 return 0;
601 }
602
603 static const struct of_device_id ufs_hisi_of_match[] = {
604 { .compatible = "hisilicon,hi3660-ufs" },
605 {},
606 };
607
608 MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
609
610 static const struct dev_pm_ops ufs_hisi_pm_ops = {
611 .suspend = ufshcd_pltfrm_suspend,
612 .resume = ufshcd_pltfrm_resume,
613 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
614 .runtime_resume = ufshcd_pltfrm_runtime_resume,
615 .runtime_idle = ufshcd_pltfrm_runtime_idle,
616 };
617
618 static struct platform_driver ufs_hisi_pltform = {
619 .probe = ufs_hisi_probe,
620 .remove = ufs_hisi_remove,
621 .shutdown = ufshcd_pltfrm_shutdown,
622 .driver = {
623 .name = "ufshcd-hisi",
624 .pm = &ufs_hisi_pm_ops,
625 .of_match_table = of_match_ptr(ufs_hisi_of_match),
626 },
627 };
628 module_platform_driver(ufs_hisi_pltform);
629
630 MODULE_LICENSE("GPL");
631 MODULE_ALIAS("platform:ufshcd-hisi");
632 MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver");
633