1/* 2 * Copyright © 2014-2017 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16 17#include "pm.h" 18 19 .text 20 .align 3 21 22#define AON_CTRL_REG r10 23#define DDR_PHY_STATUS_REG r11 24 25/* 26 * r0: AON_CTRL base address 27 * r1: DDRY PHY PLL status register address 28 */ 29ENTRY(brcmstb_pm_do_s2) 30 stmfd sp!, {r4-r11, lr} 31 mov AON_CTRL_REG, r0 32 mov DDR_PHY_STATUS_REG, r1 33 34 /* Flush memory transactions */ 35 dsb 36 37 /* Cache DDR_PHY_STATUS_REG translation */ 38 ldr r0, [DDR_PHY_STATUS_REG] 39 40 /* power down request */ 41 ldr r0, =PM_S2_COMMAND 42 ldr r1, =0 43 str r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 44 ldr r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 45 str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 46 ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 47 48 /* Wait for interrupt */ 49 wfi 50 nop 51 52 /* Bring MEMC back up */ 531: ldr r0, [DDR_PHY_STATUS_REG] 54 ands r0, #1 55 beq 1b 56 57 /* Power-up handshake */ 58 ldr r0, =1 59 str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS] 60 ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS] 61 62 ldr r0, =0 63 str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 64 ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] 65 66 /* Return to caller */ 67 ldr r0, =0 68 ldmfd sp!, {r4-r11, pc} 69 70 ENDPROC(brcmstb_pm_do_s2) 71 72 /* Place literal pool here */ 73 .ltorg 74 75ENTRY(brcmstb_pm_do_s2_sz) 76 .word . - brcmstb_pm_do_s2 77