1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* AM43x EPOS EVM */ 10 11/dts-v1/; 12 13#include "am4372.dtsi" 14#include <dt-bindings/pinctrl/am43xx.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pwm/pwm.h> 17#include <dt-bindings/sound/tlv320aic31xx-micbias.h> 18 19/ { 20 model = "TI AM43x EPOS EVM"; 21 compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; 22 23 aliases { 24 display0 = &lcd0; 25 }; 26 27 chosen { 28 stdout-path = &uart0; 29 }; 30 31 vmmcsd_fixed: fixedregulator-sd { 32 compatible = "regulator-fixed"; 33 regulator-name = "vmmcsd_fixed"; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 enable-active-high; 37 }; 38 39 vbat: fixedregulator0 { 40 compatible = "regulator-fixed"; 41 regulator-name = "vbat"; 42 regulator-min-microvolt = <5000000>; 43 regulator-max-microvolt = <5000000>; 44 regulator-boot-on; 45 }; 46 47 lcd0: display { 48 compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; 49 label = "lcd"; 50 51 backlight = <&lcd_bl>; 52 53 panel-timing { 54 clock-frequency = <33000000>; 55 hactive = <800>; 56 vactive = <480>; 57 hfront-porch = <210>; 58 hback-porch = <16>; 59 hsync-len = <30>; 60 vback-porch = <10>; 61 vfront-porch = <22>; 62 vsync-len = <13>; 63 hsync-active = <0>; 64 vsync-active = <0>; 65 de-active = <1>; 66 pixelclk-active = <1>; 67 }; 68 69 port { 70 lcd_in: endpoint { 71 remote-endpoint = <&dpi_out>; 72 }; 73 }; 74 }; 75 76 matrix_keypad: matrix_keypad0 { 77 compatible = "gpio-matrix-keypad"; 78 debounce-delay-ms = <5>; 79 col-scan-delay-us = <2>; 80 pinctrl-names = "default", "sleep"; 81 pinctrl-0 = <&matrix_keypad_default>; 82 pinctrl-1 = <&matrix_keypad_sleep>; 83 84 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ 85 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ 86 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ 87 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ 88 89 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ 90 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ 91 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ 92 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ 93 94 linux,keymap = <0x00000201 /* P1 */ 95 0x01000204 /* P4 */ 96 0x02000207 /* P7 */ 97 0x0300020a /* NUMERIC_STAR */ 98 0x00010202 /* P2 */ 99 0x01010205 /* P5 */ 100 0x02010208 /* P8 */ 101 0x03010200 /* P0 */ 102 0x00020203 /* P3 */ 103 0x01020206 /* P6 */ 104 0x02020209 /* P9 */ 105 0x0302020b /* NUMERIC_POUND */ 106 0x00030067 /* UP */ 107 0x0103006a /* RIGHT */ 108 0x0203006c /* DOWN */ 109 0x03030069>; /* LEFT */ 110 }; 111 112 lcd_bl: backlight { 113 compatible = "pwm-backlight"; 114 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 115 brightness-levels = <0 51 53 56 62 75 101 152 255>; 116 default-brightness-level = <8>; 117 }; 118 119 sound0: sound0 { 120 compatible = "simple-audio-card"; 121 simple-audio-card,name = "AM43-EPOS-EVM"; 122 simple-audio-card,widgets = 123 "Microphone", "Microphone Jack", 124 "Headphone", "Headphone Jack", 125 "Speaker", "Speaker"; 126 simple-audio-card,routing = 127 "MIC1LP", "Microphone Jack", 128 "MIC1RP", "Microphone Jack", 129 "MIC1LP", "MICBIAS", 130 "MIC1RP", "MICBIAS", 131 "Headphone Jack", "HPL", 132 "Headphone Jack", "HPR", 133 "Speaker", "SPL", 134 "Speaker", "SPR"; 135 simple-audio-card,format = "dsp_b"; 136 simple-audio-card,bitclock-master = <&sound0_master>; 137 simple-audio-card,frame-master = <&sound0_master>; 138 simple-audio-card,bitclock-inversion; 139 140 simple-audio-card,cpu { 141 sound-dai = <&mcasp1>; 142 system-clock-frequency = <12000000>; 143 }; 144 145 sound0_master: simple-audio-card,codec { 146 sound-dai = <&tlv320aic3111>; 147 system-clock-frequency = <12000000>; 148 }; 149 }; 150}; 151 152&am43xx_pinmux { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&unused_pins>; 155 156 unused_pins: unused_pins { 157 pinctrl-single,pins = < 158 AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 159 AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 160 AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 161 AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 162 AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 163 AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 164 AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 165 AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 166 AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 167 AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 168 AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 169 AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 170 AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 171 AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 172 AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 173 AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 174 AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 175 AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 176 AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 177 AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 178 AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 179 AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 180 AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 181 AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 182 AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 183 AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 184 AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 185 AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 186 AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 187 >; 188 }; 189 190 cpsw_default: cpsw_default { 191 pinctrl-single,pins = < 192 /* Slave 1 */ 193 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 194 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 195 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 196 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ 197 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 198 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 199 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 200 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 201 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ 202 >; 203 }; 204 205 cpsw_sleep: cpsw_sleep { 206 pinctrl-single,pins = < 207 /* Slave 1 reset value */ 208 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) 209 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) 210 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) 211 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) 212 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) 213 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) 214 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) 215 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) 216 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) 217 >; 218 }; 219 220 davinci_mdio_default: davinci_mdio_default { 221 pinctrl-single,pins = < 222 /* MDIO */ 223 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 224 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 225 >; 226 }; 227 228 davinci_mdio_sleep: davinci_mdio_sleep { 229 pinctrl-single,pins = < 230 /* MDIO reset value */ 231 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) 232 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) 233 >; 234 }; 235 236 i2c0_pins: pinmux_i2c0_pins { 237 pinctrl-single,pins = < 238 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 239 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 240 >; 241 }; 242 243 nand_flash_x8_default: nand_flash_x8_default { 244 pinctrl-single,pins = < 245 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ 246 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 247 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 248 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 249 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 250 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 251 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 252 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 253 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 254 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 255 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 256 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 257 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 258 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 259 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 260 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 261 >; 262 }; 263 264 nand_flash_x8_sleep: nand_flash_x8_sleep { 265 pinctrl-single,pins = < 266 AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 267 AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 268 AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 269 AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 270 AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 271 AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 272 AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 273 AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 274 AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 275 AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 276 AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 277 AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 278 AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 279 AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 280 AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 281 AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 282 >; 283 }; 284 285 ecap0_pins_default: backlight_pins_default { 286 pinctrl-single,pins = < 287 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 288 >; 289 }; 290 291 ecap0_pins_sleep: backlight_pins_sleep { 292 pinctrl-single,pins = < 293 AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 294 >; 295 }; 296 297 i2c2_pins: pinmux_i2c2_pins { 298 pinctrl-single,pins = < 299 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ 300 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ 301 >; 302 }; 303 304 spi0_pins_default: pinmux_spi0_pins_default { 305 pinctrl-single,pins = < 306 AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ 307 AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ 308 AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ 309 AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ 310 >; 311 }; 312 313 spi0_pins_sleep: pinmux_spi0_pins_sleep { 314 pinctrl-single,pins = < 315 AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 316 AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 317 AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 318 AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 319 >; 320 }; 321 322 spi1_pins_default: pinmux_spi1_pins_default { 323 pinctrl-single,pins = < 324 AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ 325 AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 326 AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 327 AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 328 >; 329 }; 330 331 spi1_pins_sleep: pinmux_spi1_pins_sleep { 332 pinctrl-single,pins = < 333 AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 334 AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 335 AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 336 AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 337 >; 338 }; 339 340 mmc1_pins_default: pinmux_mmc1_pins_default { 341 pinctrl-single,pins = < 342 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 343 >; 344 }; 345 346 mmc1_pins_sleep: pinmux_mmc1_pins_sleep { 347 pinctrl-single,pins = < 348 AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) 349 >; 350 }; 351 352 matrix_keypad_default: matrix_keypad_default { 353 pinctrl-single,pins = < 354 AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ 355 AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ 356 AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ 357 AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ 358 AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ 359 AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ 360 AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ 361 AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ 362 >; 363 }; 364 365 matrix_keypad_sleep: matrix_keypad_sleep { 366 pinctrl-single,pins = < 367 AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) 368 AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) 369 AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) 370 AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) 371 AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) 372 AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) 373 AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) 374 AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) 375 >; 376 }; 377 378 qspi1_pins_default: qspi1_pins_default { 379 pinctrl-single,pins = < 380 AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) 381 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) 382 AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) 383 AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) 384 AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) 385 AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) 386 >; 387 }; 388 389 qspi1_pins_sleep: qspi1_pins_sleep { 390 pinctrl-single,pins = < 391 AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 392 AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 393 AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 394 AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 395 AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 396 AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 397 >; 398 }; 399 400 pixcir_ts_pins_default: pixcir_ts_pins_default { 401 pinctrl-single,pins = < 402 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 403 >; 404 }; 405 406 pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { 407 pinctrl-single,pins = < 408 AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 409 >; 410 }; 411 412 hdq_pins: pinmux_hdq_pins { 413 pinctrl-single,pins = < 414 AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ 415 >; 416 }; 417 418 dss_pins: dss_pins { 419 pinctrl-single,pins = < 420 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 421 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) 422 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) 423 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) 424 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) 425 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) 426 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) 427 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 428 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 429 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) 430 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) 431 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) 432 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) 433 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) 434 AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) 435 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) 436 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) 437 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) 438 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) 439 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) 440 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) 441 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) 442 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) 443 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 444 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 445 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 446 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 447 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 448 >; 449 }; 450 451 display_mux_pins: display_mux_pins { 452 pinctrl-single,pins = < 453 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ 454 AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) 455 >; 456 }; 457 458 vpfe1_pins_default: vpfe1_pins_default { 459 pinctrl-single,pins = < 460 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ 461 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ 462 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ 463 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ 464 AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ 465 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ 466 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ 467 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ 468 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ 469 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ 470 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ 471 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ 472 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ 473 >; 474 }; 475 476 vpfe1_pins_sleep: vpfe1_pins_sleep { 477 pinctrl-single,pins = < 478 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 479 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 480 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 481 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 482 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 483 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 484 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 485 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 486 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 487 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 488 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 489 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 490 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 491 >; 492 }; 493 494 uart0_pins_default: uart0_pins_default { 495 pinctrl-single,pins = < 496 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ 497 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ 498 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 499 AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ 500 >; 501 }; 502 503 uart0_pins_sleep: uart0_pins_sleep { 504 pinctrl-single,pins = < 505 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 506 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 507 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) 508 AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) 509 >; 510 }; 511 512 usb2_phy1_default: usb2_phy1_default { 513 pinctrl-single,pins = < 514 AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) 515 >; 516 }; 517 518 usb2_phy1_sleep: usb2_phy1_sleep { 519 pinctrl-single,pins = < 520 AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) 521 >; 522 }; 523 524 usb2_phy2_default: usb2_phy2_default { 525 pinctrl-single,pins = < 526 AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) 527 >; 528 }; 529 530 usb2_phy2_sleep: usb2_phy2_sleep { 531 pinctrl-single,pins = < 532 AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) 533 >; 534 }; 535 536 mcasp1_pins: mcasp1_pins { 537 pinctrl-single,pins = < 538 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ 539 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ 540 AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ 541 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ 542 >; 543 }; 544 545 mcasp1_sleep_pins: mcasp1_sleep_pins { 546 pinctrl-single,pins = < 547 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) 548 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) 549 AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) 550 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) 551 >; 552 }; 553}; 554 555&mmc1 { 556 status = "okay"; 557 vmmc-supply = <&vmmcsd_fixed>; 558 bus-width = <4>; 559 pinctrl-names = "default", "sleep"; 560 pinctrl-0 = <&mmc1_pins_default>; 561 pinctrl-1 = <&mmc1_pins_sleep>; 562 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 563}; 564 565&mac { 566 pinctrl-names = "default", "sleep"; 567 pinctrl-0 = <&cpsw_default>; 568 pinctrl-1 = <&cpsw_sleep>; 569 status = "okay"; 570 slaves = <1>; 571}; 572 573&davinci_mdio { 574 pinctrl-names = "default", "sleep"; 575 pinctrl-0 = <&davinci_mdio_default>; 576 pinctrl-1 = <&davinci_mdio_sleep>; 577 status = "okay"; 578}; 579 580&cpsw_emac0 { 581 phy_id = <&davinci_mdio>, <16>; 582 phy-mode = "rmii"; 583}; 584 585&phy_sel { 586 rmii-clock-ext; 587}; 588 589&i2c0 { 590 status = "okay"; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&i2c0_pins>; 593 clock-frequency = <400000>; 594 595 tps65218: tps65218@24 { 596 reg = <0x24>; 597 compatible = "ti,tps65218"; 598 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */ 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 602 dcdc1: regulator-dcdc1 { 603 regulator-name = "vdd_core"; 604 regulator-min-microvolt = <912000>; 605 regulator-max-microvolt = <1144000>; 606 regulator-boot-on; 607 regulator-always-on; 608 }; 609 610 dcdc2: regulator-dcdc2 { 611 regulator-name = "vdd_mpu"; 612 regulator-min-microvolt = <912000>; 613 regulator-max-microvolt = <1378000>; 614 regulator-boot-on; 615 regulator-always-on; 616 }; 617 618 dcdc3: regulator-dcdc3 { 619 regulator-name = "vdcdc3"; 620 regulator-boot-on; 621 regulator-always-on; 622 }; 623 624 dcdc4: regulator-dcdc4 { 625 regulator-name = "vdcdc4"; 626 regulator-min-microvolt = <3300000>; 627 regulator-max-microvolt = <3300000>; 628 regulator-boot-on; 629 regulator-always-on; 630 }; 631 632 dcdc5: regulator-dcdc5 { 633 regulator-name = "v1_0bat"; 634 regulator-min-microvolt = <1000000>; 635 regulator-max-microvolt = <1000000>; 636 }; 637 638 dcdc6: regulator-dcdc6 { 639 regulator-name = "v1_8bat"; 640 regulator-min-microvolt = <1800000>; 641 regulator-max-microvolt = <1800000>; 642 }; 643 644 ldo1: regulator-ldo1 { 645 regulator-min-microvolt = <1800000>; 646 regulator-max-microvolt = <1800000>; 647 regulator-boot-on; 648 regulator-always-on; 649 }; 650 }; 651 652 at24@50 { 653 compatible = "atmel,24c256"; 654 pagesize = <64>; 655 reg = <0x50>; 656 }; 657 658 pixcir_ts@5c { 659 compatible = "pixcir,pixcir_tangoc"; 660 pinctrl-names = "default", "sleep"; 661 pinctrl-0 = <&pixcir_ts_pins_default>; 662 pinctrl-1 = <&pixcir_ts_pins_sleep>; 663 664 reg = <0x5c>; 665 interrupt-parent = <&gpio1>; 666 interrupts = <17 IRQ_TYPE_EDGE_FALLING>; 667 668 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 669 670 touchscreen-size-x = <1024>; 671 touchscreen-size-y = <600>; 672 }; 673 674 tlv320aic3111: tlv320aic3111@18 { 675 #sound-dai-cells = <0>; 676 compatible = "ti,tlv320aic3111"; 677 reg = <0x18>; 678 status = "okay"; 679 680 ai31xx-micbias-vg = <MICBIAS_2_0V>; 681 682 /* Regulators */ 683 HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 684 SPRVDD-supply = <&vbat>; /* vbat */ 685 SPLVDD-supply = <&vbat>; /* vbat */ 686 AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 687 IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ 688 DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ 689 }; 690}; 691 692&i2c2 { 693 pinctrl-names = "default"; 694 pinctrl-0 = <&i2c2_pins>; 695 status = "okay"; 696}; 697 698&gpio0 { 699 status = "okay"; 700}; 701 702&gpio1 { 703 status = "okay"; 704}; 705 706&gpio2 { 707 pinctrl-names = "default"; 708 pinctrl-0 = <&display_mux_pins>; 709 status = "okay"; 710 711 p1 { 712 /* 713 * SelLCDorHDMI selects between display and audio paths: 714 * Low: HDMI display with audio via HDMI 715 * High: LCD display with analog audio via aic3111 codec 716 */ 717 gpio-hog; 718 gpios = <1 GPIO_ACTIVE_HIGH>; 719 output-high; 720 line-name = "SelLCDorHDMI"; 721 }; 722}; 723 724&gpio3 { 725 status = "okay"; 726}; 727 728&elm { 729 status = "okay"; 730}; 731 732&gpmc { 733 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 734 pinctrl-names = "default", "sleep"; 735 pinctrl-0 = <&nand_flash_x8_default>; 736 pinctrl-1 = <&nand_flash_x8_sleep>; 737 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 738 nand@0,0 { 739 compatible = "ti,omap2-nand"; 740 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 741 interrupt-parent = <&gpmc>; 742 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 743 <1 IRQ_TYPE_NONE>; /* termcount */ 744 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 745 ti,nand-xfer-type = "prefetch-dma"; 746 ti,nand-ecc-opt = "bch16"; 747 ti,elm-id = <&elm>; 748 nand-bus-width = <8>; 749 gpmc,device-width = <1>; 750 gpmc,sync-clk-ps = <0>; 751 gpmc,cs-on-ns = <0>; 752 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ 753 gpmc,cs-wr-off-ns = <40>; 754 gpmc,adv-on-ns = <0>; /* cs-on-ns */ 755 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ 756 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ 757 gpmc,we-on-ns = <0>; /* cs-on-ns */ 758 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ 759 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ 760 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ 761 gpmc,access-ns = <30>; /* tCEA + 4*/ 762 gpmc,rd-cycle-ns = <40>; 763 gpmc,wr-cycle-ns = <40>; 764 gpmc,bus-turnaround-ns = <0>; 765 gpmc,cycle2cycle-delay-ns = <0>; 766 gpmc,clk-activation-ns = <0>; 767 gpmc,wr-access-ns = <40>; 768 gpmc,wr-data-mux-bus-ns = <0>; 769 /* MTD partition table */ 770 /* All SPL-* partitions are sized to minimal length 771 * which can be independently programmable. For 772 * NAND flash this is equal to size of erase-block */ 773 #address-cells = <1>; 774 #size-cells = <1>; 775 partition@0 { 776 label = "NAND.SPL"; 777 reg = <0x00000000 0x00040000>; 778 }; 779 partition@1 { 780 label = "NAND.SPL.backup1"; 781 reg = <0x00040000 0x00040000>; 782 }; 783 partition@2 { 784 label = "NAND.SPL.backup2"; 785 reg = <0x00080000 0x00040000>; 786 }; 787 partition@3 { 788 label = "NAND.SPL.backup3"; 789 reg = <0x000C0000 0x00040000>; 790 }; 791 partition@4 { 792 label = "NAND.u-boot-spl-os"; 793 reg = <0x00100000 0x00080000>; 794 }; 795 partition@5 { 796 label = "NAND.u-boot"; 797 reg = <0x00180000 0x00100000>; 798 }; 799 partition@6 { 800 label = "NAND.u-boot-env"; 801 reg = <0x00280000 0x00040000>; 802 }; 803 partition@7 { 804 label = "NAND.u-boot-env.backup1"; 805 reg = <0x002C0000 0x00040000>; 806 }; 807 partition@8 { 808 label = "NAND.kernel"; 809 reg = <0x00300000 0x00700000>; 810 }; 811 partition@9 { 812 label = "NAND.file-system"; 813 reg = <0x00a00000 0x1f600000>; 814 }; 815 }; 816}; 817 818&epwmss0 { 819 status = "okay"; 820}; 821 822&tscadc { 823 status = "okay"; 824 825 adc { 826 ti,adc-channels = <0 1 2 3 4 5 6 7>; 827 }; 828}; 829 830&ecap0 { 831 status = "okay"; 832 pinctrl-names = "default", "sleep"; 833 pinctrl-0 = <&ecap0_pins_default>; 834 pinctrl-1 = <&ecap0_pins_sleep>; 835}; 836 837&spi0 { 838 status = "okay"; 839 pinctrl-names = "default", "sleep"; 840 pinctrl-0 = <&spi0_pins_default>; 841 pinctrl-1 = <&spi0_pins_sleep>; 842 ti,pindir-d0-out-d1-in = <1>; 843}; 844 845&spi1 { 846 status = "okay"; 847 pinctrl-names = "default", "sleep"; 848 pinctrl-0 = <&spi1_pins_default>; 849 pinctrl-1 = <&spi1_pins_sleep>; 850 ti,pindir-d0-out-d1-in = <1>; 851}; 852 853&usb2_phy1 { 854 status = "okay"; 855 pinctrl-names = "default", "sleep"; 856 pinctrl-0 = <&usb2_phy1_default>; 857 pinctrl-1 = <&usb2_phy1_sleep>; 858}; 859 860&usb1 { 861 dr_mode = "otg"; 862 status = "okay"; 863}; 864 865&usb2_phy2 { 866 status = "okay"; 867 pinctrl-names = "default", "sleep"; 868 pinctrl-0 = <&usb2_phy2_default>; 869 pinctrl-1 = <&usb2_phy2_sleep>; 870}; 871 872&usb2 { 873 dr_mode = "host"; 874 status = "okay"; 875}; 876 877&qspi { 878 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ 879 pinctrl-names = "default", "sleep"; 880 pinctrl-0 = <&qspi1_pins_default>; 881 pinctrl-1 = <&qspi1_pins_sleep>; 882 883 spi-max-frequency = <48000000>; 884 m25p80@0 { 885 compatible = "mx66l51235l"; 886 spi-max-frequency = <48000000>; 887 reg = <0>; 888 spi-cpol; 889 spi-cpha; 890 spi-tx-bus-width = <1>; 891 spi-rx-bus-width = <4>; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 895 /* MTD partition table. 896 * The ROM checks the first 512KiB 897 * for a valid file to boot(XIP). 898 */ 899 partition@0 { 900 label = "QSPI.U_BOOT"; 901 reg = <0x00000000 0x000080000>; 902 }; 903 partition@1 { 904 label = "QSPI.U_BOOT.backup"; 905 reg = <0x00080000 0x00080000>; 906 }; 907 partition@2 { 908 label = "QSPI.U-BOOT-SPL_OS"; 909 reg = <0x00100000 0x00010000>; 910 }; 911 partition@3 { 912 label = "QSPI.U_BOOT_ENV"; 913 reg = <0x00110000 0x00010000>; 914 }; 915 partition@4 { 916 label = "QSPI.U-BOOT-ENV.backup"; 917 reg = <0x00120000 0x00010000>; 918 }; 919 partition@5 { 920 label = "QSPI.KERNEL"; 921 reg = <0x00130000 0x0800000>; 922 }; 923 partition@6 { 924 label = "QSPI.FILESYSTEM"; 925 reg = <0x00930000 0x36D0000>; 926 }; 927 }; 928}; 929 930&hdq { 931 status = "okay"; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&hdq_pins>; 934}; 935 936&dss { 937 status = "ok"; 938 939 pinctrl-names = "default"; 940 pinctrl-0 = <&dss_pins>; 941 942 port { 943 dpi_out: endpoint { 944 remote-endpoint = <&lcd_in>; 945 data-lines = <24>; 946 }; 947 }; 948}; 949 950&vpfe1 { 951 status = "okay"; 952 pinctrl-names = "default", "sleep"; 953 pinctrl-0 = <&vpfe1_pins_default>; 954 pinctrl-1 = <&vpfe1_pins_sleep>; 955 956 port { 957 vpfe1_ep: endpoint { 958 /* remote-endpoint = <&sensor>; add once we have it */ 959 ti,am437x-vpfe-interface = <0>; 960 bus-width = <8>; 961 hsync-active = <0>; 962 vsync-active = <0>; 963 }; 964 }; 965}; 966 967&uart0 { 968 status = "okay"; 969 pinctrl-names = "default", "sleep"; 970 pinctrl-0 = <&uart0_pins_default>; 971 pinctrl-1 = <&uart0_pins_sleep>; 972}; 973 974&mcasp1 { 975 #sound-dai-cells = <0>; 976 pinctrl-names = "default", "sleep"; 977 pinctrl-0 = <&mcasp1_pins>; 978 pinctrl-1 = <&mcasp1_sleep_pins>; 979 980 status = "okay"; 981 982 op-mode = <0>; /* MCASP_IIS_MODE */ 983 tdm-slots = <2>; 984 /* 4 serializer */ 985 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 986 1 2 0 0 987 >; 988 tx-num-evt = <32>; 989 rx-num-evt = <32>; 990}; 991 992&mux_synctimer32k_ck { 993 assigned-clocks = <&mux_synctimer32k_ck>; 994 assigned-clock-parents = <&clkdiv32k_ick>; 995}; 996 997&cpu { 998 cpu0-supply = <&dcdc2>; 999}; 1000