1/* 2 * Copyright 2016 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23#include <dt-bindings/interrupt-controller/irq.h> 24#include <dt-bindings/gpio/gpio.h> 25#include "skeleton.dtsi" 26 27/ { 28 compatible = "arm,realview-pbx"; 29 30 chosen { }; 31 32 aliases { 33 serial0 = &serial0; 34 serial1 = &serial1; 35 serial2 = &serial2; 36 serial3 = &serial3; 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 }; 40 41 memory { 42 /* 128 MiB memory @ 0x0 */ 43 reg = <0x00000000 0x08000000>; 44 }; 45 46 /* The voltage to the MMC card is hardwired at 3.3V */ 47 vmmc: regulator-vmmc { 48 compatible = "regulator-fixed"; 49 regulator-name = "vmmc"; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 regulator-boot-on; 53 }; 54 55 veth: regulator-veth { 56 compatible = "regulator-fixed"; 57 regulator-name = "veth"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 regulator-boot-on; 61 }; 62 63 xtal24mhz: xtal24mhz@24M { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <24000000>; 67 }; 68 69 refclk32khz: refclk32khz { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 timclk: timclk@1M { 76 #clock-cells = <0>; 77 compatible = "fixed-factor-clock"; 78 clock-div = <24>; 79 clock-mult = <1>; 80 clocks = <&xtal24mhz>; 81 }; 82 83 mclk: mclk@24M { 84 #clock-cells = <0>; 85 compatible = "fixed-factor-clock"; 86 clock-div = <1>; 87 clock-mult = <1>; 88 clocks = <&xtal24mhz>; 89 }; 90 91 kmiclk: kmiclk@24M { 92 #clock-cells = <0>; 93 compatible = "fixed-factor-clock"; 94 clock-div = <1>; 95 clock-mult = <1>; 96 clocks = <&xtal24mhz>; 97 }; 98 99 sspclk: sspclk@24M { 100 #clock-cells = <0>; 101 compatible = "fixed-factor-clock"; 102 clock-div = <1>; 103 clock-mult = <1>; 104 clocks = <&xtal24mhz>; 105 }; 106 107 uartclk: uartclk@24M { 108 #clock-cells = <0>; 109 compatible = "fixed-factor-clock"; 110 clock-div = <1>; 111 clock-mult = <1>; 112 clocks = <&xtal24mhz>; 113 }; 114 115 wdogclk: wdogclk@24M { 116 #clock-cells = <0>; 117 compatible = "fixed-factor-clock"; 118 clock-div = <1>; 119 clock-mult = <1>; 120 clocks = <&xtal24mhz>; 121 }; 122 123 /* FIXME: this actually hangs off the PLL clocks */ 124 pclk: pclk@0 { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 clock-frequency = <0>; 128 }; 129 130 flash0@40000000 { 131 /* 2 * 32MiB NOR Flash memory */ 132 compatible = "arm,versatile-flash", "cfi-flash"; 133 reg = <0x40000000 0x04000000>; 134 bank-width = <4>; 135 }; 136 137 flash1@44000000 { 138 /* 2 * 32MiB NOR Flash memory */ 139 compatible = "arm,versatile-flash", "cfi-flash"; 140 reg = <0x44000000 0x04000000>; 141 bank-width = <4>; 142 }; 143 144 /* SMSC 9118 ethernet with PHY and EEPROM */ 145 ethernet: ethernet@4e000000 { 146 compatible = "smsc,lan9118", "smsc,lan9115"; 147 reg = <0x4e000000 0x10000>; 148 phy-mode = "mii"; 149 reg-io-width = <4>; 150 smsc,irq-active-high; 151 smsc,irq-push-pull; 152 vdd33a-supply = <&veth>; 153 vddvario-supply = <&veth>; 154 }; 155 156 usb: usb@4f000000 { 157 compatible = "nxp,usb-isp1761"; 158 reg = <0x4f000000 0x20000>; 159 port1-otg; 160 }; 161 162 bridge { 163 compatible = "ti,ths8134a", "ti,ths8134"; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 ports { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 port@0 { 172 reg = <0>; 173 174 vga_bridge_in: endpoint { 175 remote-endpoint = <&clcd_pads>; 176 }; 177 }; 178 179 port@1 { 180 reg = <1>; 181 182 vga_bridge_out: endpoint { 183 remote-endpoint = <&vga_con_in>; 184 }; 185 }; 186 }; 187 }; 188 189 vga { 190 /* 191 * This DDC I2C is connected directly to the DVI portions 192 * of the connector, so it's not really working when the 193 * monitor is connected to the VGA connector. 194 */ 195 compatible = "vga-connector"; 196 ddc-i2c-bus = <&i2c1>; 197 198 port { 199 vga_con_in: endpoint { 200 remote-endpoint = <&vga_bridge_out>; 201 }; 202 }; 203 }; 204 205 soc: soc@0 { 206 compatible = "arm,realview-pbx-soc", "simple-bus"; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 regmap = <&syscon>; 210 ranges; 211 212 syscon: syscon@10000000 { 213 compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; 214 reg = <0x10000000 0x1000>; 215 216 led@08.0 { 217 compatible = "register-bit-led"; 218 offset = <0x08>; 219 mask = <0x01>; 220 label = "versatile:0"; 221 linux,default-trigger = "heartbeat"; 222 default-state = "on"; 223 }; 224 led@08.1 { 225 compatible = "register-bit-led"; 226 offset = <0x08>; 227 mask = <0x02>; 228 label = "versatile:1"; 229 linux,default-trigger = "mmc0"; 230 default-state = "off"; 231 }; 232 led@08.2 { 233 compatible = "register-bit-led"; 234 offset = <0x08>; 235 mask = <0x04>; 236 label = "versatile:2"; 237 linux,default-trigger = "cpu0"; 238 default-state = "off"; 239 }; 240 led@08.3 { 241 compatible = "register-bit-led"; 242 offset = <0x08>; 243 mask = <0x08>; 244 label = "versatile:3"; 245 default-state = "off"; 246 }; 247 led@08.4 { 248 compatible = "register-bit-led"; 249 offset = <0x08>; 250 mask = <0x10>; 251 label = "versatile:4"; 252 default-state = "off"; 253 }; 254 led@08.5 { 255 compatible = "register-bit-led"; 256 offset = <0x08>; 257 mask = <0x20>; 258 label = "versatile:5"; 259 default-state = "off"; 260 }; 261 led@08.6 { 262 compatible = "register-bit-led"; 263 offset = <0x08>; 264 mask = <0x40>; 265 label = "versatile:6"; 266 default-state = "off"; 267 }; 268 led@08.7 { 269 compatible = "register-bit-led"; 270 offset = <0x08>; 271 mask = <0x80>; 272 label = "versatile:7"; 273 default-state = "off"; 274 }; 275 oscclk0: osc0@0c { 276 compatible = "arm,syscon-icst307"; 277 #clock-cells = <0>; 278 lock-offset = <0x20>; 279 vco-offset = <0x0C>; 280 clocks = <&xtal24mhz>; 281 }; 282 oscclk1: osc1@10 { 283 compatible = "arm,syscon-icst307"; 284 #clock-cells = <0>; 285 lock-offset = <0x20>; 286 vco-offset = <0x10>; 287 clocks = <&xtal24mhz>; 288 }; 289 oscclk2: osc2@14 { 290 compatible = "arm,syscon-icst307"; 291 #clock-cells = <0>; 292 lock-offset = <0x20>; 293 vco-offset = <0x14>; 294 clocks = <&xtal24mhz>; 295 }; 296 oscclk3: osc3@18 { 297 compatible = "arm,syscon-icst307"; 298 #clock-cells = <0>; 299 lock-offset = <0x20>; 300 vco-offset = <0x18>; 301 clocks = <&xtal24mhz>; 302 }; 303 oscclk4: osc4@1c { 304 compatible = "arm,syscon-icst307"; 305 #clock-cells = <0>; 306 lock-offset = <0x20>; 307 vco-offset = <0x1c>; 308 clocks = <&xtal24mhz>; 309 }; 310 }; 311 312 sp810_syscon0: sysctl@10001000 { 313 compatible = "arm,sp810", "arm,primecell"; 314 reg = <0x10001000 0x1000>; 315 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 316 clock-names = "refclk", "timclk", "apb_pclk"; 317 #clock-cells = <1>; 318 clock-output-names = "timerclk0", 319 "timerclk1", 320 "timerclk2", 321 "timerclk3"; 322 assigned-clocks = <&sp810_syscon0 0>, 323 <&sp810_syscon0 1>, 324 <&sp810_syscon0 2>, 325 <&sp810_syscon0 3>; 326 assigned-clock-parents = <&timclk>, 327 <&timclk>, 328 <&timclk>, 329 <&timclk>; 330 }; 331 332 i2c0: i2c@10002000 { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 compatible = "arm,versatile-i2c"; 336 reg = <0x10002000 0x1000>; 337 338 rtc@68 { 339 compatible = "dallas,ds1338"; 340 reg = <0x68>; 341 }; 342 }; 343 344 serial0: serial@10009000 { 345 compatible = "arm,pl011", "arm,primecell"; 346 reg = <0x10009000 0x1000>; 347 clocks = <&uartclk>, <&pclk>; 348 clock-names = "uartclk", "apb_pclk"; 349 }; 350 351 serial1: serial@1000a000 { 352 compatible = "arm,pl011", "arm,primecell"; 353 reg = <0x1000a000 0x1000>; 354 clocks = <&uartclk>, <&pclk>; 355 clock-names = "uartclk", "apb_pclk"; 356 }; 357 358 serial2: serial@1000b000 { 359 compatible = "arm,pl011", "arm,primecell"; 360 reg = <0x1000b000 0x1000>; 361 clocks = <&uartclk>, <&pclk>; 362 clock-names = "uartclk", "apb_pclk"; 363 }; 364 365 ssp: spi@1000d000 { 366 compatible = "arm,pl022", "arm,primecell"; 367 reg = <0x1000d000 0x1000>; 368 clocks = <&sspclk>, <&pclk>; 369 clock-names = "SSPCLK", "apb_pclk"; 370 }; 371 372 wdog0: watchdog@1000f000 { 373 compatible = "arm,sp805", "arm,primecell"; 374 reg = <0x1000f000 0x1000>; 375 clocks = <&wdogclk>, <&pclk>; 376 clock-names = "wdogclk", "apb_pclk"; 377 status = "disabled"; 378 }; 379 380 wdog1: watchdog@10010000 { 381 compatible = "arm,sp805", "arm,primecell"; 382 reg = <0x10010000 0x1000>; 383 clocks = <&wdogclk>, <&pclk>; 384 clock-names = "wdogclk", "apb_pclk"; 385 status = "disabled"; 386 }; 387 388 timer01: timer@10011000 { 389 compatible = "arm,sp804", "arm,primecell"; 390 reg = <0x10011000 0x1000>; 391 clocks = <&sp810_syscon0 0>, 392 <&sp810_syscon0 1>, 393 <&pclk>; 394 clock-names = "timerclk0", 395 "timerclk1", 396 "apb_pclk"; 397 }; 398 399 timer23: timer@10012000 { 400 compatible = "arm,sp804", "arm,primecell"; 401 reg = <0x10012000 0x1000>; 402 clocks = <&sp810_syscon0 2>, 403 <&sp810_syscon0 3>, 404 <&pclk>; 405 clock-names = "timerclk2", 406 "timerclk3", 407 "apb_pclk"; 408 }; 409 410 gpio0: gpio@10013000 { 411 compatible = "arm,pl061", "arm,primecell"; 412 reg = <0x10013000 0x1000>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 clocks = <&pclk>; 418 clock-names = "apb_pclk"; 419 }; 420 421 gpio1: gpio@10014000 { 422 compatible = "arm,pl061", "arm,primecell"; 423 reg = <0x10014000 0x1000>; 424 gpio-controller; 425 #gpio-cells = <2>; 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 clocks = <&pclk>; 429 clock-names = "apb_pclk"; 430 }; 431 432 gpio2: gpio@10015000 { 433 compatible = "arm,pl061", "arm,primecell"; 434 reg = <0x10015000 0x1000>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 clocks = <&pclk>; 440 clock-names = "apb_pclk"; 441 }; 442 443 i2c1: i2c@10016000 { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 compatible = "arm,versatile-i2c"; 447 reg = <0x10016000 0x1000>; 448 }; 449 450 rtc: rtc@10017000 { 451 compatible = "arm,pl031", "arm,primecell"; 452 reg = <0x10017000 0x1000>; 453 clocks = <&pclk>; 454 clock-names = "apb_pclk"; 455 }; 456 457 timer45: timer@10018000 { 458 compatible = "arm,sp804", "arm,primecell"; 459 reg = <0x10018000 0x1000>; 460 clocks = <&timclk>, <&timclk>, <&pclk>; 461 clock-names = "timerclk4", "timerclk5", "apb_pclk"; 462 }; 463 464 timer67: timer@10019000 { 465 compatible = "arm,sp804", "arm,primecell"; 466 reg = <0x10019000 0x1000>; 467 clocks = <&timclk>, <&timclk>, <&pclk>; 468 clock-names = "timerclk6", "timerclk7", "apb_pclk"; 469 }; 470 471 sp810_syscon1: sysctl@1001a000 { 472 compatible = "arm,sp810", "arm,primecell"; 473 reg = <0x1001a000 0x1000>; 474 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 475 clock-names = "refclk", "timclk", "apb_pclk"; 476 #clock-cells = <1>; 477 clock-output-names = "timerclk4", 478 "timerclk5", 479 "timerclk6", 480 "timerclk7"; 481 assigned-clocks = <&sp810_syscon1 0>, 482 <&sp810_syscon1 1>, 483 <&sp810_syscon1 2>, 484 <&sp810_syscon1 3>; 485 assigned-clock-parents = <&timclk>, 486 <&timclk>, 487 <&timclk>, 488 <&timclk>; 489 }; 490 }; 491 492 493 /* These peripherals are inside the FPGA */ 494 fpga { 495 #address-cells = <1>; 496 #size-cells = <1>; 497 compatible = "simple-bus"; 498 ranges; 499 500 aaci: aaci@10004000 { 501 compatible = "arm,pl041", "arm,primecell"; 502 reg = <0x10004000 0x1000>; 503 clocks = <&pclk>; 504 clock-names = "apb_pclk"; 505 }; 506 507 mmc: mmcsd@10005000 { 508 compatible = "arm,pl18x", "arm,primecell"; 509 reg = <0x10005000 0x1000>; 510 511 /* Due to frequent FIFO overruns, use just 500 kHz */ 512 max-frequency = <500000>; 513 bus-width = <4>; 514 cap-sd-highspeed; 515 cap-mmc-highspeed; 516 clocks = <&mclk>, <&pclk>; 517 clock-names = "mclk", "apb_pclk"; 518 vmmc-supply = <&vmmc>; 519 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 520 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 521 }; 522 523 kmi0: kmi@10006000 { 524 compatible = "arm,pl050", "arm,primecell"; 525 reg = <0x10006000 0x1000>; 526 clocks = <&kmiclk>, <&pclk>; 527 clock-names = "KMIREFCLK", "apb_pclk"; 528 }; 529 530 kmi1: kmi@10007000 { 531 compatible = "arm,pl050", "arm,primecell"; 532 reg = <0x10007000 0x1000>; 533 clocks = <&kmiclk>, <&pclk>; 534 clock-names = "KMIREFCLK", "apb_pclk"; 535 }; 536 537 serial3: serial@1000c000 { 538 compatible = "arm,pl011", "arm,primecell"; 539 reg = <0x1000c000 0x1000>; 540 clocks = <&uartclk>, <&pclk>; 541 clock-names = "uartclk", "apb_pclk"; 542 }; 543 }; 544 545 /* These peripherals are inside the NEC ISSP */ 546 issp { 547 #address-cells = <1>; 548 #size-cells = <1>; 549 compatible = "simple-bus"; 550 ranges; 551 552 clcd: clcd@10020000 { 553 compatible = "arm,pl111", "arm,primecell"; 554 reg = <0x10020000 0x1000>; 555 interrupt-names = "combined"; 556 clocks = <&oscclk4>, <&pclk>; 557 clock-names = "clcdclk", "apb_pclk"; 558 /* 1024x768 16bpp @65MHz works fine */ 559 max-memory-bandwidth = <95000000>; 560 561 port { 562 clcd_pads: endpoint { 563 remote-endpoint = <&vga_bridge_in>; 564 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 565 }; 566 }; 567 }; 568 }; 569}; 570