1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos4210 SoC device tree source 4 * 5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Copyright (c) 2010-2011 Linaro Ltd. 8 * www.linaro.org 9 * 10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 11 * based board files can include this file and provide values for board specfic 12 * bindings. 13 * 14 * Note: This file does not include device nodes for all the controllers in 15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional 16 * nodes can be added to this file. 17 */ 18 19#include "exynos4.dtsi" 20#include "exynos4-cpu-thermal.dtsi" 21 22/ { 23 compatible = "samsung,exynos4210", "samsung,exynos4"; 24 25 aliases { 26 pinctrl0 = &pinctrl_0; 27 pinctrl1 = &pinctrl_1; 28 pinctrl2 = &pinctrl_2; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@900 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a9"; 38 reg = <0x900>; 39 clocks = <&clock CLK_ARM_CLK>; 40 clock-names = "cpu"; 41 clock-latency = <160000>; 42 43 operating-points = < 44 1200000 1250000 45 1000000 1150000 46 800000 1075000 47 500000 975000 48 400000 975000 49 200000 950000 50 >; 51 #cooling-cells = <2>; /* min followed by max */ 52 }; 53 54 cpu@901 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a9"; 57 reg = <0x901>; 58 clocks = <&clock CLK_ARM_CLK>; 59 clock-names = "cpu"; 60 clock-latency = <160000>; 61 62 operating-points = < 63 1200000 1250000 64 1000000 1150000 65 800000 1075000 66 500000 975000 67 400000 975000 68 200000 950000 69 >; 70 #cooling-cells = <2>; /* min followed by max */ 71 }; 72 }; 73 74 soc: soc { 75 sysram: sysram@2020000 { 76 compatible = "mmio-sram"; 77 reg = <0x02020000 0x20000>; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges = <0 0x02020000 0x20000>; 81 82 smp-sysram@0 { 83 compatible = "samsung,exynos4210-sysram"; 84 reg = <0x0 0x1000>; 85 }; 86 87 smp-sysram@1f000 { 88 compatible = "samsung,exynos4210-sysram-ns"; 89 reg = <0x1f000 0x1000>; 90 }; 91 }; 92 93 pd_lcd1: lcd1-power-domain@10023ca0 { 94 compatible = "samsung,exynos4210-pd"; 95 reg = <0x10023CA0 0x20>; 96 #power-domain-cells = <0>; 97 label = "LCD1"; 98 }; 99 100 l2c: l2-cache-controller@10502000 { 101 compatible = "arm,pl310-cache"; 102 reg = <0x10502000 0x1000>; 103 cache-unified; 104 cache-level = <2>; 105 arm,tag-latency = <2 2 1>; 106 arm,data-latency = <2 2 1>; 107 }; 108 109 mct: mct@10050000 { 110 compatible = "samsung,exynos4210-mct"; 111 reg = <0x10050000 0x800>; 112 interrupt-parent = <&mct_map>; 113 interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 114 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 115 clock-names = "fin_pll", "mct"; 116 117 mct_map: mct-map { 118 #interrupt-cells = <1>; 119 #address-cells = <0>; 120 #size-cells = <0>; 121 interrupt-map = 122 <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 123 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, 124 <2 &combiner 12 6>, 125 <3 &combiner 12 7>, 126 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, 127 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; 128 }; 129 }; 130 131 watchdog: watchdog@10060000 { 132 compatible = "samsung,s3c6410-wdt"; 133 reg = <0x10060000 0x100>; 134 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&clock CLK_WDT>; 136 clock-names = "watchdog"; 137 }; 138 139 clock: clock-controller@10030000 { 140 compatible = "samsung,exynos4210-clock"; 141 reg = <0x10030000 0x20000>; 142 #clock-cells = <1>; 143 }; 144 145 pinctrl_0: pinctrl@11400000 { 146 compatible = "samsung,exynos4210-pinctrl"; 147 reg = <0x11400000 0x1000>; 148 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 149 }; 150 151 pinctrl_1: pinctrl@11000000 { 152 compatible = "samsung,exynos4210-pinctrl"; 153 reg = <0x11000000 0x1000>; 154 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 155 156 wakup_eint: wakeup-interrupt-controller { 157 compatible = "samsung,exynos4210-wakeup-eint"; 158 interrupt-parent = <&gic>; 159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 }; 162 163 pinctrl_2: pinctrl@3860000 { 164 compatible = "samsung,exynos4210-pinctrl"; 165 reg = <0x03860000 0x1000>; 166 }; 167 168 g2d: g2d@12800000 { 169 compatible = "samsung,s5pv210-g2d"; 170 reg = <0x12800000 0x1000>; 171 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 173 clock-names = "sclk_fimg2d", "fimg2d"; 174 power-domains = <&pd_lcd0>; 175 iommus = <&sysmmu_g2d>; 176 }; 177 178 ppmu_acp: ppmu_acp@10ae0000 { 179 compatible = "samsung,exynos-ppmu"; 180 reg = <0x10ae0000 0x2000>; 181 status = "disabled"; 182 }; 183 184 ppmu_lcd1: ppmu_lcd1@12240000 { 185 compatible = "samsung,exynos-ppmu"; 186 reg = <0x12240000 0x2000>; 187 clocks = <&clock CLK_PPMULCD1>; 188 clock-names = "ppmu"; 189 status = "disabled"; 190 }; 191 192 sysmmu_g2d: sysmmu@12a20000 { 193 compatible = "samsung,exynos-sysmmu"; 194 reg = <0x12A20000 0x1000>; 195 interrupt-parent = <&combiner>; 196 interrupts = <4 7>; 197 clock-names = "sysmmu", "master"; 198 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 199 power-domains = <&pd_lcd0>; 200 #iommu-cells = <0>; 201 }; 202 203 sysmmu_fimd1: sysmmu@12220000 { 204 compatible = "samsung,exynos-sysmmu"; 205 interrupt-parent = <&combiner>; 206 reg = <0x12220000 0x1000>; 207 interrupts = <5 3>; 208 clock-names = "sysmmu", "master"; 209 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 210 power-domains = <&pd_lcd1>; 211 #iommu-cells = <0>; 212 }; 213 214 bus_dmc: bus_dmc { 215 compatible = "samsung,exynos-bus"; 216 clocks = <&clock CLK_DIV_DMC>; 217 clock-names = "bus"; 218 operating-points-v2 = <&bus_dmc_opp_table>; 219 status = "disabled"; 220 }; 221 222 bus_acp: bus_acp { 223 compatible = "samsung,exynos-bus"; 224 clocks = <&clock CLK_DIV_ACP>; 225 clock-names = "bus"; 226 operating-points-v2 = <&bus_acp_opp_table>; 227 status = "disabled"; 228 }; 229 230 bus_peri: bus_peri { 231 compatible = "samsung,exynos-bus"; 232 clocks = <&clock CLK_ACLK100>; 233 clock-names = "bus"; 234 operating-points-v2 = <&bus_peri_opp_table>; 235 status = "disabled"; 236 }; 237 238 bus_fsys: bus_fsys { 239 compatible = "samsung,exynos-bus"; 240 clocks = <&clock CLK_ACLK133>; 241 clock-names = "bus"; 242 operating-points-v2 = <&bus_fsys_opp_table>; 243 status = "disabled"; 244 }; 245 246 bus_display: bus_display { 247 compatible = "samsung,exynos-bus"; 248 clocks = <&clock CLK_ACLK160>; 249 clock-names = "bus"; 250 operating-points-v2 = <&bus_display_opp_table>; 251 status = "disabled"; 252 }; 253 254 bus_lcd0: bus_lcd0 { 255 compatible = "samsung,exynos-bus"; 256 clocks = <&clock CLK_ACLK200>; 257 clock-names = "bus"; 258 operating-points-v2 = <&bus_leftbus_opp_table>; 259 status = "disabled"; 260 }; 261 262 bus_leftbus: bus_leftbus { 263 compatible = "samsung,exynos-bus"; 264 clocks = <&clock CLK_DIV_GDL>; 265 clock-names = "bus"; 266 operating-points-v2 = <&bus_leftbus_opp_table>; 267 status = "disabled"; 268 }; 269 270 bus_rightbus: bus_rightbus { 271 compatible = "samsung,exynos-bus"; 272 clocks = <&clock CLK_DIV_GDR>; 273 clock-names = "bus"; 274 operating-points-v2 = <&bus_leftbus_opp_table>; 275 status = "disabled"; 276 }; 277 278 bus_mfc: bus_mfc { 279 compatible = "samsung,exynos-bus"; 280 clocks = <&clock CLK_SCLK_MFC>; 281 clock-names = "bus"; 282 operating-points-v2 = <&bus_leftbus_opp_table>; 283 status = "disabled"; 284 }; 285 286 bus_dmc_opp_table: opp_table1 { 287 compatible = "operating-points-v2"; 288 opp-shared; 289 290 opp-134000000 { 291 opp-hz = /bits/ 64 <134000000>; 292 opp-microvolt = <1025000>; 293 }; 294 opp-267000000 { 295 opp-hz = /bits/ 64 <267000000>; 296 opp-microvolt = <1050000>; 297 }; 298 opp-400000000 { 299 opp-hz = /bits/ 64 <400000000>; 300 opp-microvolt = <1150000>; 301 }; 302 }; 303 304 bus_acp_opp_table: opp_table2 { 305 compatible = "operating-points-v2"; 306 opp-shared; 307 308 opp-134000000 { 309 opp-hz = /bits/ 64 <134000000>; 310 }; 311 opp-160000000 { 312 opp-hz = /bits/ 64 <160000000>; 313 }; 314 opp-200000000 { 315 opp-hz = /bits/ 64 <200000000>; 316 }; 317 }; 318 319 bus_peri_opp_table: opp_table3 { 320 compatible = "operating-points-v2"; 321 opp-shared; 322 323 opp-5000000 { 324 opp-hz = /bits/ 64 <5000000>; 325 }; 326 opp-100000000 { 327 opp-hz = /bits/ 64 <100000000>; 328 }; 329 }; 330 331 bus_fsys_opp_table: opp_table4 { 332 compatible = "operating-points-v2"; 333 opp-shared; 334 335 opp-10000000 { 336 opp-hz = /bits/ 64 <10000000>; 337 }; 338 opp-134000000 { 339 opp-hz = /bits/ 64 <134000000>; 340 }; 341 }; 342 343 bus_display_opp_table: opp_table5 { 344 compatible = "operating-points-v2"; 345 opp-shared; 346 347 opp-100000000 { 348 opp-hz = /bits/ 64 <100000000>; 349 }; 350 opp-134000000 { 351 opp-hz = /bits/ 64 <134000000>; 352 }; 353 opp-160000000 { 354 opp-hz = /bits/ 64 <160000000>; 355 }; 356 }; 357 358 bus_leftbus_opp_table: opp_table6 { 359 compatible = "operating-points-v2"; 360 opp-shared; 361 362 opp-100000000 { 363 opp-hz = /bits/ 64 <100000000>; 364 }; 365 opp-160000000 { 366 opp-hz = /bits/ 64 <160000000>; 367 }; 368 opp-200000000 { 369 opp-hz = /bits/ 64 <200000000>; 370 }; 371 }; 372 }; 373 374 thermal-zones { 375 cpu_thermal: cpu-thermal { 376 polling-delay-passive = <0>; 377 polling-delay = <0>; 378 thermal-sensors = <&tmu 0>; 379 380 trips { 381 cpu_alert0: cpu-alert-0 { 382 temperature = <85000>; /* millicelsius */ 383 }; 384 cpu_alert1: cpu-alert-1 { 385 temperature = <100000>; /* millicelsius */ 386 }; 387 cpu_alert2: cpu-alert-2 { 388 temperature = <110000>; /* millicelsius */ 389 }; 390 }; 391 }; 392 }; 393}; 394 395&gic { 396 cpu-offset = <0x8000>; 397}; 398 399&camera { 400 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 401 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 402 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 403}; 404 405&combiner { 406 samsung,combiner-nr = <16>; 407 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 423}; 424 425&fimc_0 { 426 samsung,pix-limits = <4224 8192 1920 4224>; 427 samsung,mainscaler-ext; 428 samsung,cam-if; 429}; 430 431&fimc_1 { 432 samsung,pix-limits = <4224 8192 1920 4224>; 433 samsung,mainscaler-ext; 434 samsung,cam-if; 435}; 436 437&fimc_2 { 438 samsung,pix-limits = <4224 8192 1920 4224>; 439 samsung,mainscaler-ext; 440 samsung,lcd-wb; 441}; 442 443&fimc_3 { 444 samsung,pix-limits = <1920 8192 1366 1920>; 445 samsung,rotators = <0>; 446 samsung,mainscaler-ext; 447 samsung,lcd-wb; 448}; 449 450&mdma1 { 451 power-domains = <&pd_lcd0>; 452}; 453 454&mixer { 455 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", 456 "sclk_mixer"; 457 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 458 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, 459 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; 460}; 461 462&pmu_system_controller { 463 clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 464 "clkout4", "clkout8", "clkout9"; 465 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 466 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 467 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 468 #clock-cells = <1>; 469}; 470 471&rotator { 472 power-domains = <&pd_lcd0>; 473}; 474 475&sysmmu_rotator { 476 power-domains = <&pd_lcd0>; 477}; 478 479&tmu { 480 compatible = "samsung,exynos4210-tmu"; 481 clocks = <&clock CLK_TMU_APBIF>; 482 clock-names = "tmu_apbif"; 483 samsung,tmu_gain = <15>; 484 samsung,tmu_reference_voltage = <7>; 485}; 486 487#include "exynos4210-pinctrl.dtsi" 488