1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos4412 SoC device tree source 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 9 * based board files can include this file and provide values for board specfic 10 * bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional 14 * nodes can be added to this file. 15 */ 16 17#include "exynos4.dtsi" 18 19#include "exynos4-cpu-thermal.dtsi" 20 21/ { 22 compatible = "samsung,exynos4412", "samsung,exynos4"; 23 24 aliases { 25 pinctrl0 = &pinctrl_0; 26 pinctrl1 = &pinctrl_1; 27 pinctrl2 = &pinctrl_2; 28 pinctrl3 = &pinctrl_3; 29 fimc-lite0 = &fimc_lite_0; 30 fimc-lite1 = &fimc_lite_1; 31 mshc0 = &mshc_0; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu0: cpu@a00 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 reg = <0xA00>; 42 clocks = <&clock CLK_ARM_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu0_opp_table>; 45 #cooling-cells = <2>; /* min followed by max */ 46 }; 47 48 cpu@a01 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a9"; 51 reg = <0xA01>; 52 clocks = <&clock CLK_ARM_CLK>; 53 clock-names = "cpu"; 54 operating-points-v2 = <&cpu0_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu@a02 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a9"; 61 reg = <0xA02>; 62 clocks = <&clock CLK_ARM_CLK>; 63 clock-names = "cpu"; 64 operating-points-v2 = <&cpu0_opp_table>; 65 #cooling-cells = <2>; /* min followed by max */ 66 }; 67 68 cpu@a03 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a9"; 71 reg = <0xA03>; 72 clocks = <&clock CLK_ARM_CLK>; 73 clock-names = "cpu"; 74 operating-points-v2 = <&cpu0_opp_table>; 75 #cooling-cells = <2>; /* min followed by max */ 76 }; 77 }; 78 79 cpu0_opp_table: opp_table0 { 80 compatible = "operating-points-v2"; 81 opp-shared; 82 83 opp-200000000 { 84 opp-hz = /bits/ 64 <200000000>; 85 opp-microvolt = <900000>; 86 clock-latency-ns = <200000>; 87 }; 88 opp-300000000 { 89 opp-hz = /bits/ 64 <300000000>; 90 opp-microvolt = <900000>; 91 clock-latency-ns = <200000>; 92 }; 93 opp-400000000 { 94 opp-hz = /bits/ 64 <400000000>; 95 opp-microvolt = <925000>; 96 clock-latency-ns = <200000>; 97 }; 98 opp-500000000 { 99 opp-hz = /bits/ 64 <500000000>; 100 opp-microvolt = <950000>; 101 clock-latency-ns = <200000>; 102 }; 103 opp-600000000 { 104 opp-hz = /bits/ 64 <600000000>; 105 opp-microvolt = <975000>; 106 clock-latency-ns = <200000>; 107 }; 108 opp-700000000 { 109 opp-hz = /bits/ 64 <700000000>; 110 opp-microvolt = <987500>; 111 clock-latency-ns = <200000>; 112 }; 113 opp-800000000 { 114 opp-hz = /bits/ 64 <800000000>; 115 opp-microvolt = <1000000>; 116 clock-latency-ns = <200000>; 117 opp-suspend; 118 }; 119 opp-900000000 { 120 opp-hz = /bits/ 64 <900000000>; 121 opp-microvolt = <1037500>; 122 clock-latency-ns = <200000>; 123 }; 124 opp-1000000000 { 125 opp-hz = /bits/ 64 <1000000000>; 126 opp-microvolt = <1087500>; 127 clock-latency-ns = <200000>; 128 }; 129 opp-1100000000 { 130 opp-hz = /bits/ 64 <1100000000>; 131 opp-microvolt = <1137500>; 132 clock-latency-ns = <200000>; 133 }; 134 opp-1200000000 { 135 opp-hz = /bits/ 64 <1200000000>; 136 opp-microvolt = <1187500>; 137 clock-latency-ns = <200000>; 138 }; 139 opp-1300000000 { 140 opp-hz = /bits/ 64 <1300000000>; 141 opp-microvolt = <1250000>; 142 clock-latency-ns = <200000>; 143 }; 144 opp-1400000000 { 145 opp-hz = /bits/ 64 <1400000000>; 146 opp-microvolt = <1287500>; 147 clock-latency-ns = <200000>; 148 }; 149 cpu0_opp_1500: opp-1500000000 { 150 opp-hz = /bits/ 64 <1500000000>; 151 opp-microvolt = <1350000>; 152 clock-latency-ns = <200000>; 153 turbo-mode; 154 }; 155 }; 156 157 158 soc: soc { 159 160 pinctrl_0: pinctrl@11400000 { 161 compatible = "samsung,exynos4x12-pinctrl"; 162 reg = <0x11400000 0x1000>; 163 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 pinctrl_1: pinctrl@11000000 { 167 compatible = "samsung,exynos4x12-pinctrl"; 168 reg = <0x11000000 0x1000>; 169 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 170 171 wakup_eint: wakeup-interrupt-controller { 172 compatible = "samsung,exynos4210-wakeup-eint"; 173 interrupt-parent = <&gic>; 174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 }; 177 178 pinctrl_2: pinctrl@3860000 { 179 compatible = "samsung,exynos4x12-pinctrl"; 180 reg = <0x03860000 0x1000>; 181 interrupt-parent = <&combiner>; 182 interrupts = <10 0>; 183 }; 184 185 pinctrl_3: pinctrl@106e0000 { 186 compatible = "samsung,exynos4x12-pinctrl"; 187 reg = <0x106E0000 0x1000>; 188 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 sysram@2020000 { 192 compatible = "mmio-sram"; 193 reg = <0x02020000 0x40000>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 ranges = <0 0x02020000 0x40000>; 197 198 smp-sysram@0 { 199 compatible = "samsung,exynos4210-sysram"; 200 reg = <0x0 0x1000>; 201 }; 202 203 smp-sysram@2f000 { 204 compatible = "samsung,exynos4210-sysram-ns"; 205 reg = <0x2f000 0x1000>; 206 }; 207 }; 208 209 pd_isp: isp-power-domain@10023ca0 { 210 compatible = "samsung,exynos4210-pd"; 211 reg = <0x10023CA0 0x20>; 212 #power-domain-cells = <0>; 213 label = "ISP"; 214 }; 215 216 l2c: l2-cache-controller@10502000 { 217 compatible = "arm,pl310-cache"; 218 reg = <0x10502000 0x1000>; 219 cache-unified; 220 cache-level = <2>; 221 arm,tag-latency = <2 2 1>; 222 arm,data-latency = <3 2 1>; 223 arm,double-linefill = <1>; 224 arm,double-linefill-incr = <0>; 225 arm,double-linefill-wrap = <1>; 226 arm,prefetch-drop = <1>; 227 arm,prefetch-offset = <7>; 228 }; 229 230 clock: clock-controller@10030000 { 231 compatible = "samsung,exynos4412-clock"; 232 reg = <0x10030000 0x18000>; 233 #clock-cells = <1>; 234 }; 235 236 isp_clock: clock-controller@10048000 { 237 compatible = "samsung,exynos4412-isp-clock"; 238 reg = <0x10048000 0x1000>; 239 #clock-cells = <1>; 240 power-domains = <&pd_isp>; 241 clocks = <&clock CLK_ACLK200>, 242 <&clock CLK_ACLK400_MCUISP>; 243 clock-names = "aclk200", "aclk400_mcuisp"; 244 }; 245 246 mct@10050000 { 247 compatible = "samsung,exynos4412-mct"; 248 reg = <0x10050000 0x800>; 249 interrupt-parent = <&mct_map>; 250 interrupts = <0>, <1>, <2>, <3>, <4>; 251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 252 clock-names = "fin_pll", "mct"; 253 254 mct_map: mct-map { 255 #interrupt-cells = <1>; 256 #address-cells = <0>; 257 #size-cells = <0>; 258 interrupt-map = 259 <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 260 <1 &combiner 12 5>, 261 <2 &combiner 12 6>, 262 <3 &combiner 12 7>, 263 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; 264 }; 265 }; 266 267 watchdog: watchdog@10060000 { 268 compatible = "samsung,exynos5250-wdt"; 269 reg = <0x10060000 0x100>; 270 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&clock CLK_WDT>; 272 clock-names = "watchdog"; 273 samsung,syscon-phandle = <&pmu_system_controller>; 274 }; 275 276 adc: adc@126c0000 { 277 compatible = "samsung,exynos-adc-v1"; 278 reg = <0x126C0000 0x100>; 279 interrupt-parent = <&combiner>; 280 interrupts = <10 3>; 281 clocks = <&clock CLK_TSADC>; 282 clock-names = "adc"; 283 #io-channel-cells = <1>; 284 io-channel-ranges; 285 samsung,syscon-phandle = <&pmu_system_controller>; 286 status = "disabled"; 287 }; 288 289 g2d: g2d@10800000 { 290 compatible = "samsung,exynos4212-g2d"; 291 reg = <0x10800000 0x1000>; 292 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 294 clock-names = "sclk_fimg2d", "fimg2d"; 295 iommus = <&sysmmu_g2d>; 296 }; 297 298 mshc_0: mmc@12550000 { 299 compatible = "samsung,exynos4412-dw-mshc"; 300 reg = <0x12550000 0x1000>; 301 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 fifo-depth = <0x80>; 305 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; 306 clock-names = "biu", "ciu"; 307 status = "disabled"; 308 }; 309 310 sysmmu_g2d: sysmmu@10a40000 { 311 compatible = "samsung,exynos-sysmmu"; 312 reg = <0x10A40000 0x1000>; 313 interrupt-parent = <&combiner>; 314 interrupts = <4 7>; 315 clock-names = "sysmmu", "master"; 316 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 317 #iommu-cells = <0>; 318 }; 319 320 sysmmu_fimc_isp: sysmmu@12260000 { 321 compatible = "samsung,exynos-sysmmu"; 322 reg = <0x12260000 0x1000>; 323 interrupt-parent = <&combiner>; 324 interrupts = <16 2>; 325 power-domains = <&pd_isp>; 326 clock-names = "sysmmu"; 327 clocks = <&isp_clock CLK_ISP_SMMU_ISP>; 328 #iommu-cells = <0>; 329 }; 330 331 sysmmu_fimc_drc: sysmmu@12270000 { 332 compatible = "samsung,exynos-sysmmu"; 333 reg = <0x12270000 0x1000>; 334 interrupt-parent = <&combiner>; 335 interrupts = <16 3>; 336 power-domains = <&pd_isp>; 337 clock-names = "sysmmu"; 338 clocks = <&isp_clock CLK_ISP_SMMU_DRC>; 339 #iommu-cells = <0>; 340 }; 341 342 sysmmu_fimc_fd: sysmmu@122a0000 { 343 compatible = "samsung,exynos-sysmmu"; 344 reg = <0x122A0000 0x1000>; 345 interrupt-parent = <&combiner>; 346 interrupts = <16 4>; 347 power-domains = <&pd_isp>; 348 clock-names = "sysmmu"; 349 clocks = <&isp_clock CLK_ISP_SMMU_FD>; 350 #iommu-cells = <0>; 351 }; 352 353 sysmmu_fimc_mcuctl: sysmmu@122b0000 { 354 compatible = "samsung,exynos-sysmmu"; 355 reg = <0x122B0000 0x1000>; 356 interrupt-parent = <&combiner>; 357 interrupts = <16 5>; 358 power-domains = <&pd_isp>; 359 clock-names = "sysmmu"; 360 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; 361 #iommu-cells = <0>; 362 }; 363 364 sysmmu_fimc_lite0: sysmmu@123b0000 { 365 compatible = "samsung,exynos-sysmmu"; 366 reg = <0x123B0000 0x1000>; 367 interrupt-parent = <&combiner>; 368 interrupts = <16 0>; 369 power-domains = <&pd_isp>; 370 clock-names = "sysmmu", "master"; 371 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, 372 <&isp_clock CLK_ISP_FIMC_LITE0>; 373 #iommu-cells = <0>; 374 }; 375 376 sysmmu_fimc_lite1: sysmmu@123c0000 { 377 compatible = "samsung,exynos-sysmmu"; 378 reg = <0x123C0000 0x1000>; 379 interrupt-parent = <&combiner>; 380 interrupts = <16 1>; 381 power-domains = <&pd_isp>; 382 clock-names = "sysmmu", "master"; 383 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, 384 <&isp_clock CLK_ISP_FIMC_LITE1>; 385 #iommu-cells = <0>; 386 }; 387 388 bus_dmc: bus_dmc { 389 compatible = "samsung,exynos-bus"; 390 clocks = <&clock CLK_DIV_DMC>; 391 clock-names = "bus"; 392 operating-points-v2 = <&bus_dmc_opp_table>; 393 status = "disabled"; 394 }; 395 396 bus_acp: bus_acp { 397 compatible = "samsung,exynos-bus"; 398 clocks = <&clock CLK_DIV_ACP>; 399 clock-names = "bus"; 400 operating-points-v2 = <&bus_acp_opp_table>; 401 status = "disabled"; 402 }; 403 404 bus_c2c: bus_c2c { 405 compatible = "samsung,exynos-bus"; 406 clocks = <&clock CLK_DIV_C2C>; 407 clock-names = "bus"; 408 operating-points-v2 = <&bus_dmc_opp_table>; 409 status = "disabled"; 410 }; 411 412 bus_dmc_opp_table: opp_table1 { 413 compatible = "operating-points-v2"; 414 opp-shared; 415 416 opp-100000000 { 417 opp-hz = /bits/ 64 <100000000>; 418 opp-microvolt = <900000>; 419 }; 420 opp-134000000 { 421 opp-hz = /bits/ 64 <134000000>; 422 opp-microvolt = <900000>; 423 }; 424 opp-160000000 { 425 opp-hz = /bits/ 64 <160000000>; 426 opp-microvolt = <900000>; 427 }; 428 opp-267000000 { 429 opp-hz = /bits/ 64 <267000000>; 430 opp-microvolt = <950000>; 431 }; 432 opp-400000000 { 433 opp-hz = /bits/ 64 <400000000>; 434 opp-microvolt = <1050000>; 435 }; 436 }; 437 438 bus_acp_opp_table: opp_table2 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 opp-100000000 { 443 opp-hz = /bits/ 64 <100000000>; 444 }; 445 opp-134000000 { 446 opp-hz = /bits/ 64 <134000000>; 447 }; 448 opp-160000000 { 449 opp-hz = /bits/ 64 <160000000>; 450 }; 451 opp-267000000 { 452 opp-hz = /bits/ 64 <267000000>; 453 }; 454 }; 455 456 bus_leftbus: bus_leftbus { 457 compatible = "samsung,exynos-bus"; 458 clocks = <&clock CLK_DIV_GDL>; 459 clock-names = "bus"; 460 operating-points-v2 = <&bus_leftbus_opp_table>; 461 status = "disabled"; 462 }; 463 464 bus_rightbus: bus_rightbus { 465 compatible = "samsung,exynos-bus"; 466 clocks = <&clock CLK_DIV_GDR>; 467 clock-names = "bus"; 468 operating-points-v2 = <&bus_leftbus_opp_table>; 469 status = "disabled"; 470 }; 471 472 bus_display: bus_display { 473 compatible = "samsung,exynos-bus"; 474 clocks = <&clock CLK_ACLK160>; 475 clock-names = "bus"; 476 operating-points-v2 = <&bus_display_opp_table>; 477 status = "disabled"; 478 }; 479 480 bus_fsys: bus_fsys { 481 compatible = "samsung,exynos-bus"; 482 clocks = <&clock CLK_ACLK133>; 483 clock-names = "bus"; 484 operating-points-v2 = <&bus_fsys_opp_table>; 485 status = "disabled"; 486 }; 487 488 bus_peri: bus_peri { 489 compatible = "samsung,exynos-bus"; 490 clocks = <&clock CLK_ACLK100>; 491 clock-names = "bus"; 492 operating-points-v2 = <&bus_peri_opp_table>; 493 status = "disabled"; 494 }; 495 496 bus_mfc: bus_mfc { 497 compatible = "samsung,exynos-bus"; 498 clocks = <&clock CLK_SCLK_MFC>; 499 clock-names = "bus"; 500 operating-points-v2 = <&bus_leftbus_opp_table>; 501 status = "disabled"; 502 }; 503 504 bus_leftbus_opp_table: opp_table3 { 505 compatible = "operating-points-v2"; 506 opp-shared; 507 508 opp-100000000 { 509 opp-hz = /bits/ 64 <100000000>; 510 opp-microvolt = <900000>; 511 }; 512 opp-134000000 { 513 opp-hz = /bits/ 64 <134000000>; 514 opp-microvolt = <925000>; 515 }; 516 opp-160000000 { 517 opp-hz = /bits/ 64 <160000000>; 518 opp-microvolt = <950000>; 519 }; 520 opp-200000000 { 521 opp-hz = /bits/ 64 <200000000>; 522 opp-microvolt = <1000000>; 523 }; 524 }; 525 526 bus_display_opp_table: opp_table4 { 527 compatible = "operating-points-v2"; 528 opp-shared; 529 530 opp-160000000 { 531 opp-hz = /bits/ 64 <160000000>; 532 }; 533 opp-200000000 { 534 opp-hz = /bits/ 64 <200000000>; 535 }; 536 }; 537 538 bus_fsys_opp_table: opp_table5 { 539 compatible = "operating-points-v2"; 540 opp-shared; 541 542 opp-100000000 { 543 opp-hz = /bits/ 64 <100000000>; 544 }; 545 opp-134000000 { 546 opp-hz = /bits/ 64 <134000000>; 547 }; 548 }; 549 550 bus_peri_opp_table: opp_table6 { 551 compatible = "operating-points-v2"; 552 opp-shared; 553 554 opp-50000000 { 555 opp-hz = /bits/ 64 <50000000>; 556 }; 557 opp-100000000 { 558 opp-hz = /bits/ 64 <100000000>; 559 }; 560 }; 561 }; 562}; 563 564&combiner { 565 samsung,combiner-nr = <20>; 566 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 586}; 587 588&camera { 589 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 590 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 591 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 592 593 /* fimc_[0-3] are configured outside, under phandles */ 594 fimc_lite_0: fimc-lite@12390000 { 595 compatible = "samsung,exynos4212-fimc-lite"; 596 reg = <0x12390000 0x1000>; 597 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 598 power-domains = <&pd_isp>; 599 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; 600 clock-names = "flite"; 601 iommus = <&sysmmu_fimc_lite0>; 602 status = "disabled"; 603 }; 604 605 fimc_lite_1: fimc-lite@123a0000 { 606 compatible = "samsung,exynos4212-fimc-lite"; 607 reg = <0x123A0000 0x1000>; 608 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 609 power-domains = <&pd_isp>; 610 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; 611 clock-names = "flite"; 612 iommus = <&sysmmu_fimc_lite1>; 613 status = "disabled"; 614 }; 615 616 fimc_is: fimc-is@12000000 { 617 compatible = "samsung,exynos4212-fimc-is"; 618 reg = <0x12000000 0x260000>; 619 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 621 power-domains = <&pd_isp>; 622 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, 623 <&isp_clock CLK_ISP_FIMC_LITE1>, 624 <&isp_clock CLK_ISP_PPMUISPX>, 625 <&isp_clock CLK_ISP_PPMUISPMX>, 626 <&isp_clock CLK_ISP_FIMC_ISP>, 627 <&isp_clock CLK_ISP_FIMC_DRC>, 628 <&isp_clock CLK_ISP_FIMC_FD>, 629 <&isp_clock CLK_ISP_MCUISP>, 630 <&isp_clock CLK_ISP_GICISP>, 631 <&isp_clock CLK_ISP_MCUCTL_ISP>, 632 <&isp_clock CLK_ISP_PWM_ISP>, 633 <&isp_clock CLK_ISP_DIV_ISP0>, 634 <&isp_clock CLK_ISP_DIV_ISP1>, 635 <&isp_clock CLK_ISP_DIV_MCUISP0>, 636 <&isp_clock CLK_ISP_DIV_MCUISP1>, 637 <&clock CLK_MOUT_MPLL_USER_T>, 638 <&clock CLK_ACLK200>, 639 <&clock CLK_ACLK400_MCUISP>, 640 <&clock CLK_DIV_ACLK200>, 641 <&clock CLK_DIV_ACLK400_MCUISP>, 642 <&clock CLK_UART_ISP_SCLK>; 643 clock-names = "lite0", "lite1", "ppmuispx", 644 "ppmuispmx", "isp", 645 "drc", "fd", "mcuisp", 646 "gicisp", "mcuctl_isp", "pwm_isp", 647 "ispdiv0", "ispdiv1", "mcuispdiv0", 648 "mcuispdiv1", "mpll", "aclk200", 649 "aclk400mcuisp", "div_aclk200", 650 "div_aclk400mcuisp", "uart"; 651 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 652 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 653 iommu-names = "isp", "drc", "fd", "mcuctl"; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 ranges; 657 status = "disabled"; 658 659 pmu@10020000 { 660 reg = <0x10020000 0x3000>; 661 }; 662 663 i2c1_isp: i2c-isp@12140000 { 664 compatible = "samsung,exynos4212-i2c-isp"; 665 reg = <0x12140000 0x100>; 666 clocks = <&isp_clock CLK_ISP_I2C1_ISP>; 667 clock-names = "i2c_isp"; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 }; 671 }; 672}; 673 674&exynos_usbphy { 675 compatible = "samsung,exynos4x12-usb2-phy"; 676 samsung,sysreg-phandle = <&sys_reg>; 677}; 678 679&fimc_0 { 680 compatible = "samsung,exynos4212-fimc"; 681 samsung,pix-limits = <4224 8192 1920 4224>; 682 samsung,mainscaler-ext; 683 samsung,isp-wb; 684 samsung,cam-if; 685}; 686 687&fimc_1 { 688 compatible = "samsung,exynos4212-fimc"; 689 samsung,pix-limits = <4224 8192 1920 4224>; 690 samsung,mainscaler-ext; 691 samsung,isp-wb; 692 samsung,cam-if; 693}; 694 695&fimc_2 { 696 compatible = "samsung,exynos4212-fimc"; 697 samsung,pix-limits = <4224 8192 1920 4224>; 698 samsung,mainscaler-ext; 699 samsung,isp-wb; 700 samsung,lcd-wb; 701 samsung,cam-if; 702}; 703 704&fimc_3 { 705 compatible = "samsung,exynos4212-fimc"; 706 samsung,pix-limits = <1920 8192 1366 1920>; 707 samsung,rotators = <0>; 708 samsung,mainscaler-ext; 709 samsung,isp-wb; 710 samsung,lcd-wb; 711}; 712 713&gic { 714 cpu-offset = <0x4000>; 715}; 716 717&hdmi { 718 compatible = "samsung,exynos4212-hdmi"; 719}; 720 721&jpeg_codec { 722 compatible = "samsung,exynos4212-jpeg"; 723}; 724 725&rotator { 726 compatible = "samsung,exynos4212-rotator"; 727}; 728 729&mixer { 730 compatible = "samsung,exynos4212-mixer"; 731 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; 732 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 733 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; 734}; 735 736&pmu { 737 interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 738}; 739 740&pmu_system_controller { 741 compatible = "samsung,exynos4412-pmu", "syscon"; 742 clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 743 "clkout4", "clkout8", "clkout9"; 744 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 745 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 746 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 747 #clock-cells = <1>; 748}; 749 750&tmu { 751 compatible = "samsung,exynos4412-tmu"; 752 interrupt-parent = <&combiner>; 753 interrupts = <2 4>; 754 reg = <0x100C0000 0x100>; 755 clocks = <&clock 383>; 756 clock-names = "tmu_apbif"; 757 status = "disabled"; 758}; 759 760#include "exynos4412-pinctrl.dtsi" 761