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1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/pinctrl/omap.h>
13#include <dt-bindings/clock/omap5.h>
14
15/ {
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	compatible = "ti,omap5";
20	interrupt-parent = <&wakeupgen>;
21	chosen { };
22
23	aliases {
24		i2c0 = &i2c1;
25		i2c1 = &i2c2;
26		i2c2 = &i2c3;
27		i2c3 = &i2c4;
28		i2c4 = &i2c5;
29		serial0 = &uart1;
30		serial1 = &uart2;
31		serial2 = &uart3;
32		serial3 = &uart4;
33		serial4 = &uart5;
34		serial5 = &uart6;
35	};
36
37	cpus {
38		#address-cells = <1>;
39		#size-cells = <0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a15";
44			reg = <0x0>;
45
46			operating-points = <
47				/* kHz    uV */
48				1000000 1060000
49				1500000 1250000
50			>;
51
52			clocks = <&dpll_mpu_ck>;
53			clock-names = "cpu";
54
55			clock-latency = <300000>; /* From omap-cpufreq driver */
56
57			/* cooling options */
58			#cooling-cells = <2>; /* min followed by max */
59		};
60		cpu@1 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a15";
63			reg = <0x1>;
64
65			operating-points = <
66				/* kHz    uV */
67				1000000 1060000
68				1500000 1250000
69			>;
70
71			clocks = <&dpll_mpu_ck>;
72			clock-names = "cpu";
73
74			clock-latency = <300000>; /* From omap-cpufreq driver */
75
76			/* cooling options */
77			#cooling-cells = <2>; /* min followed by max */
78		};
79	};
80
81	thermal-zones {
82		#include "omap4-cpu-thermal.dtsi"
83		#include "omap5-gpu-thermal.dtsi"
84		#include "omap5-core-thermal.dtsi"
85	};
86
87	timer {
88		compatible = "arm,armv7-timer";
89		/* PPI secure/nonsecure IRQ */
90		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
93			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
94		interrupt-parent = <&gic>;
95	};
96
97	pmu {
98		compatible = "arm,cortex-a15-pmu";
99		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
100			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
101	};
102
103	gic: interrupt-controller@48211000 {
104		compatible = "arm,cortex-a15-gic";
105		interrupt-controller;
106		#interrupt-cells = <3>;
107		reg = <0 0x48211000 0 0x1000>,
108		      <0 0x48212000 0 0x2000>,
109		      <0 0x48214000 0 0x2000>,
110		      <0 0x48216000 0 0x2000>;
111		interrupt-parent = <&gic>;
112	};
113
114	wakeupgen: interrupt-controller@48281000 {
115		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
116		interrupt-controller;
117		#interrupt-cells = <3>;
118		reg = <0 0x48281000 0 0x1000>;
119		interrupt-parent = <&gic>;
120	};
121
122	/*
123	 * The soc node represents the soc top level view. It is used for IPs
124	 * that are not memory mapped in the MPU view or for the MPU itself.
125	 */
126	soc {
127		compatible = "ti,omap-infra";
128		mpu {
129			compatible = "ti,omap4-mpu";
130			ti,hwmods = "mpu";
131			sram = <&ocmcram>;
132		};
133	};
134
135	/*
136	 * XXX: Use a flat representation of the OMAP3 interconnect.
137	 * The real OMAP interconnect network is quite complex.
138	 * Since it will not bring real advantage to represent that in DT for
139	 * the moment, just use a fake OCP bus entry to represent the whole bus
140	 * hierarchy.
141	 */
142	ocp {
143		compatible = "ti,omap5-l3-noc", "simple-bus";
144		#address-cells = <1>;
145		#size-cells = <1>;
146		ranges = <0 0 0 0xc0000000>;
147		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
148		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
149		reg = <0 0x44000000 0 0x2000>,
150		      <0 0x44800000 0 0x3000>,
151		      <0 0x45000000 0 0x4000>;
152		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
153			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
154
155		l4_cfg: l4@4a000000 {
156			compatible = "ti,omap5-l4-cfg", "simple-bus";
157			#address-cells = <1>;
158			#size-cells = <1>;
159			ranges = <0 0x4a000000 0x22a000>;
160
161			scm_core: scm@2000 {
162				compatible = "ti,omap5-scm-core", "simple-bus";
163				reg = <0x2000 0x1000>;
164				#address-cells = <1>;
165				#size-cells = <1>;
166				ranges = <0 0x2000 0x800>;
167
168				scm_conf: scm_conf@0 {
169					compatible = "syscon";
170					reg = <0x0 0x800>;
171					#address-cells = <1>;
172					#size-cells = <1>;
173				};
174			};
175
176			scm_padconf_core: scm@2800 {
177				compatible = "ti,omap5-scm-padconf-core",
178					     "simple-bus";
179				#address-cells = <1>;
180				#size-cells = <1>;
181				ranges = <0 0x2800 0x800>;
182
183				omap5_pmx_core: pinmux@40 {
184					compatible = "ti,omap5-padconf",
185						     "pinctrl-single";
186					reg = <0x40 0x01b6>;
187					#address-cells = <1>;
188					#size-cells = <0>;
189					#pinctrl-cells = <1>;
190					#interrupt-cells = <1>;
191					interrupt-controller;
192					pinctrl-single,register-width = <16>;
193					pinctrl-single,function-mask = <0x7fff>;
194				};
195
196				omap5_padconf_global: omap5_padconf_global@5a0 {
197					compatible = "syscon",
198						     "simple-bus";
199					reg = <0x5a0 0xec>;
200					#address-cells = <1>;
201					#size-cells = <1>;
202					ranges = <0 0x5a0 0xec>;
203
204					pbias_regulator: pbias_regulator@60 {
205						compatible = "ti,pbias-omap5", "ti,pbias-omap";
206						reg = <0x60 0x4>;
207						syscon = <&omap5_padconf_global>;
208						pbias_mmc_reg: pbias_mmc_omap5 {
209							regulator-name = "pbias_mmc_omap5";
210							regulator-min-microvolt = <1800000>;
211							regulator-max-microvolt = <3300000>;
212						};
213					};
214				};
215			};
216
217			cm_core_aon: cm_core_aon@4000 {
218				compatible = "ti,omap5-cm-core-aon",
219					     "simple-bus";
220				reg = <0x4000 0x2000>;
221				#address-cells = <1>;
222				#size-cells = <1>;
223				ranges = <0 0x4000 0x2000>;
224
225				cm_core_aon_clocks: clocks {
226					#address-cells = <1>;
227					#size-cells = <0>;
228				};
229
230				cm_core_aon_clockdomains: clockdomains {
231				};
232			};
233
234			cm_core: cm_core@8000 {
235				compatible = "ti,omap5-cm-core", "simple-bus";
236				reg = <0x8000 0x3000>;
237				#address-cells = <1>;
238				#size-cells = <1>;
239				ranges = <0 0x8000 0x3000>;
240
241				cm_core_clocks: clocks {
242					#address-cells = <1>;
243					#size-cells = <0>;
244				};
245
246				cm_core_clockdomains: clockdomains {
247				};
248			};
249		};
250
251		l4_wkup: l4@4ae00000 {
252			compatible = "ti,omap5-l4-wkup", "simple-bus";
253			#address-cells = <1>;
254			#size-cells = <1>;
255			ranges = <0 0x4ae00000 0x2b000>;
256
257			counter32k: counter@4000 {
258				compatible = "ti,omap-counter32k";
259				reg = <0x4000 0x40>;
260				ti,hwmods = "counter_32k";
261			};
262
263			prm: prm@6000 {
264				compatible = "ti,omap5-prm", "simple-bus";
265				reg = <0x6000 0x3000>;
266				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
267				#address-cells = <1>;
268				#size-cells = <1>;
269				ranges = <0 0x6000 0x3000>;
270
271				prm_clocks: clocks {
272					#address-cells = <1>;
273					#size-cells = <0>;
274				};
275
276				prm_clockdomains: clockdomains {
277				};
278			};
279
280			scrm: scrm@a000 {
281				compatible = "ti,omap5-scrm";
282				reg = <0xa000 0x2000>;
283
284				scrm_clocks: clocks {
285					#address-cells = <1>;
286					#size-cells = <0>;
287				};
288
289				scrm_clockdomains: clockdomains {
290				};
291			};
292
293			omap5_pmx_wkup: pinmux@c840 {
294				compatible = "ti,omap5-padconf",
295					     "pinctrl-single";
296				reg = <0xc840 0x003c>;
297				#address-cells = <1>;
298				#size-cells = <0>;
299				#pinctrl-cells = <1>;
300				#interrupt-cells = <1>;
301				interrupt-controller;
302				pinctrl-single,register-width = <16>;
303				pinctrl-single,function-mask = <0x7fff>;
304			};
305
306			omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
307				compatible = "ti,omap5-scm-wkup-pad-conf",
308					     "simple-bus";
309				reg = <0xcda0 0x60>;
310				#address-cells = <1>;
311				#size-cells = <1>;
312				ranges = <0 0xcda0 0x60>;
313
314				scm_wkup_pad_conf: scm_conf@0 {
315					compatible = "syscon", "simple-bus";
316					reg = <0x0 0x60>;
317					#address-cells = <1>;
318					#size-cells = <1>;
319					ranges = <0 0x0 0x60>;
320
321					scm_wkup_pad_conf_clocks: clocks@0 {
322						#address-cells = <1>;
323						#size-cells = <0>;
324					};
325				};
326			};
327		};
328
329		ocmcram: ocmcram@40300000 {
330			compatible = "mmio-sram";
331			reg = <0x40300000 0x20000>; /* 128k */
332		};
333
334		sdma: dma-controller@4a056000 {
335			compatible = "ti,omap4430-sdma";
336			reg = <0x4a056000 0x1000>;
337			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
338				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
339				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
340				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
341			#dma-cells = <1>;
342			dma-channels = <32>;
343			dma-requests = <127>;
344			ti,hwmods = "dma_system";
345		};
346
347		gpio1: gpio@4ae10000 {
348			compatible = "ti,omap4-gpio";
349			reg = <0x4ae10000 0x200>;
350			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
351			ti,hwmods = "gpio1";
352			ti,gpio-always-on;
353			gpio-controller;
354			#gpio-cells = <2>;
355			interrupt-controller;
356			#interrupt-cells = <2>;
357		};
358
359		gpio2: gpio@48055000 {
360			compatible = "ti,omap4-gpio";
361			reg = <0x48055000 0x200>;
362			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
363			ti,hwmods = "gpio2";
364			gpio-controller;
365			#gpio-cells = <2>;
366			interrupt-controller;
367			#interrupt-cells = <2>;
368		};
369
370		gpio3: gpio@48057000 {
371			compatible = "ti,omap4-gpio";
372			reg = <0x48057000 0x200>;
373			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
374			ti,hwmods = "gpio3";
375			gpio-controller;
376			#gpio-cells = <2>;
377			interrupt-controller;
378			#interrupt-cells = <2>;
379		};
380
381		gpio4: gpio@48059000 {
382			compatible = "ti,omap4-gpio";
383			reg = <0x48059000 0x200>;
384			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
385			ti,hwmods = "gpio4";
386			gpio-controller;
387			#gpio-cells = <2>;
388			interrupt-controller;
389			#interrupt-cells = <2>;
390		};
391
392		gpio5: gpio@4805b000 {
393			compatible = "ti,omap4-gpio";
394			reg = <0x4805b000 0x200>;
395			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
396			ti,hwmods = "gpio5";
397			gpio-controller;
398			#gpio-cells = <2>;
399			interrupt-controller;
400			#interrupt-cells = <2>;
401		};
402
403		gpio6: gpio@4805d000 {
404			compatible = "ti,omap4-gpio";
405			reg = <0x4805d000 0x200>;
406			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
407			ti,hwmods = "gpio6";
408			gpio-controller;
409			#gpio-cells = <2>;
410			interrupt-controller;
411			#interrupt-cells = <2>;
412		};
413
414		gpio7: gpio@48051000 {
415			compatible = "ti,omap4-gpio";
416			reg = <0x48051000 0x200>;
417			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
418			ti,hwmods = "gpio7";
419			gpio-controller;
420			#gpio-cells = <2>;
421			interrupt-controller;
422			#interrupt-cells = <2>;
423		};
424
425		gpio8: gpio@48053000 {
426			compatible = "ti,omap4-gpio";
427			reg = <0x48053000 0x200>;
428			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
429			ti,hwmods = "gpio8";
430			gpio-controller;
431			#gpio-cells = <2>;
432			interrupt-controller;
433			#interrupt-cells = <2>;
434		};
435
436		gpmc: gpmc@50000000 {
437			compatible = "ti,omap4430-gpmc";
438			reg = <0x50000000 0x1000>;
439			#address-cells = <2>;
440			#size-cells = <1>;
441			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
442			dmas = <&sdma 4>;
443			dma-names = "rxtx";
444			gpmc,num-cs = <8>;
445			gpmc,num-waitpins = <4>;
446			ti,hwmods = "gpmc";
447			clocks = <&l3_iclk_div>;
448			clock-names = "fck";
449			interrupt-controller;
450			#interrupt-cells = <2>;
451			gpio-controller;
452			#gpio-cells = <2>;
453		};
454
455		i2c1: i2c@48070000 {
456			compatible = "ti,omap4-i2c";
457			reg = <0x48070000 0x100>;
458			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
459			#address-cells = <1>;
460			#size-cells = <0>;
461			ti,hwmods = "i2c1";
462		};
463
464		i2c2: i2c@48072000 {
465			compatible = "ti,omap4-i2c";
466			reg = <0x48072000 0x100>;
467			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
468			#address-cells = <1>;
469			#size-cells = <0>;
470			ti,hwmods = "i2c2";
471		};
472
473		i2c3: i2c@48060000 {
474			compatible = "ti,omap4-i2c";
475			reg = <0x48060000 0x100>;
476			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
477			#address-cells = <1>;
478			#size-cells = <0>;
479			ti,hwmods = "i2c3";
480		};
481
482		i2c4: i2c@4807a000 {
483			compatible = "ti,omap4-i2c";
484			reg = <0x4807a000 0x100>;
485			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
486			#address-cells = <1>;
487			#size-cells = <0>;
488			ti,hwmods = "i2c4";
489		};
490
491		i2c5: i2c@4807c000 {
492			compatible = "ti,omap4-i2c";
493			reg = <0x4807c000 0x100>;
494			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
495			#address-cells = <1>;
496			#size-cells = <0>;
497			ti,hwmods = "i2c5";
498		};
499
500		hwspinlock: spinlock@4a0f6000 {
501			compatible = "ti,omap4-hwspinlock";
502			reg = <0x4a0f6000 0x1000>;
503			ti,hwmods = "spinlock";
504			#hwlock-cells = <1>;
505		};
506
507		mcspi1: spi@48098000 {
508			compatible = "ti,omap4-mcspi";
509			reg = <0x48098000 0x200>;
510			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
511			#address-cells = <1>;
512			#size-cells = <0>;
513			ti,hwmods = "mcspi1";
514			ti,spi-num-cs = <4>;
515			dmas = <&sdma 35>,
516			       <&sdma 36>,
517			       <&sdma 37>,
518			       <&sdma 38>,
519			       <&sdma 39>,
520			       <&sdma 40>,
521			       <&sdma 41>,
522			       <&sdma 42>;
523			dma-names = "tx0", "rx0", "tx1", "rx1",
524				    "tx2", "rx2", "tx3", "rx3";
525		};
526
527		mcspi2: spi@4809a000 {
528			compatible = "ti,omap4-mcspi";
529			reg = <0x4809a000 0x200>;
530			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
531			#address-cells = <1>;
532			#size-cells = <0>;
533			ti,hwmods = "mcspi2";
534			ti,spi-num-cs = <2>;
535			dmas = <&sdma 43>,
536			       <&sdma 44>,
537			       <&sdma 45>,
538			       <&sdma 46>;
539			dma-names = "tx0", "rx0", "tx1", "rx1";
540		};
541
542		mcspi3: spi@480b8000 {
543			compatible = "ti,omap4-mcspi";
544			reg = <0x480b8000 0x200>;
545			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
546			#address-cells = <1>;
547			#size-cells = <0>;
548			ti,hwmods = "mcspi3";
549			ti,spi-num-cs = <2>;
550			dmas = <&sdma 15>, <&sdma 16>;
551			dma-names = "tx0", "rx0";
552		};
553
554		mcspi4: spi@480ba000 {
555			compatible = "ti,omap4-mcspi";
556			reg = <0x480ba000 0x200>;
557			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
558			#address-cells = <1>;
559			#size-cells = <0>;
560			ti,hwmods = "mcspi4";
561			ti,spi-num-cs = <1>;
562			dmas = <&sdma 70>, <&sdma 71>;
563			dma-names = "tx0", "rx0";
564		};
565
566		uart1: serial@4806a000 {
567			compatible = "ti,omap4-uart";
568			reg = <0x4806a000 0x100>;
569			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
570			ti,hwmods = "uart1";
571			clock-frequency = <48000000>;
572		};
573
574		uart2: serial@4806c000 {
575			compatible = "ti,omap4-uart";
576			reg = <0x4806c000 0x100>;
577			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
578			ti,hwmods = "uart2";
579			clock-frequency = <48000000>;
580		};
581
582		uart3: serial@48020000 {
583			compatible = "ti,omap4-uart";
584			reg = <0x48020000 0x100>;
585			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
586			ti,hwmods = "uart3";
587			clock-frequency = <48000000>;
588		};
589
590		uart4: serial@4806e000 {
591			compatible = "ti,omap4-uart";
592			reg = <0x4806e000 0x100>;
593			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
594			ti,hwmods = "uart4";
595			clock-frequency = <48000000>;
596		};
597
598		uart5: serial@48066000 {
599			compatible = "ti,omap4-uart";
600			reg = <0x48066000 0x100>;
601			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
602			ti,hwmods = "uart5";
603			clock-frequency = <48000000>;
604		};
605
606		uart6: serial@48068000 {
607			compatible = "ti,omap4-uart";
608			reg = <0x48068000 0x100>;
609			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
610			ti,hwmods = "uart6";
611			clock-frequency = <48000000>;
612		};
613
614		mmc1: mmc@4809c000 {
615			compatible = "ti,omap4-hsmmc";
616			reg = <0x4809c000 0x400>;
617			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
618			ti,hwmods = "mmc1";
619			ti,dual-volt;
620			ti,needs-special-reset;
621			dmas = <&sdma 61>, <&sdma 62>;
622			dma-names = "tx", "rx";
623			pbias-supply = <&pbias_mmc_reg>;
624		};
625
626		mmc2: mmc@480b4000 {
627			compatible = "ti,omap4-hsmmc";
628			reg = <0x480b4000 0x400>;
629			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
630			ti,hwmods = "mmc2";
631			ti,needs-special-reset;
632			dmas = <&sdma 47>, <&sdma 48>;
633			dma-names = "tx", "rx";
634		};
635
636		mmc3: mmc@480ad000 {
637			compatible = "ti,omap4-hsmmc";
638			reg = <0x480ad000 0x400>;
639			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
640			ti,hwmods = "mmc3";
641			ti,needs-special-reset;
642			dmas = <&sdma 77>, <&sdma 78>;
643			dma-names = "tx", "rx";
644		};
645
646		mmc4: mmc@480d1000 {
647			compatible = "ti,omap4-hsmmc";
648			reg = <0x480d1000 0x400>;
649			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
650			ti,hwmods = "mmc4";
651			ti,needs-special-reset;
652			dmas = <&sdma 57>, <&sdma 58>;
653			dma-names = "tx", "rx";
654		};
655
656		mmc5: mmc@480d5000 {
657			compatible = "ti,omap4-hsmmc";
658			reg = <0x480d5000 0x400>;
659			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
660			ti,hwmods = "mmc5";
661			ti,needs-special-reset;
662			dmas = <&sdma 59>, <&sdma 60>;
663			dma-names = "tx", "rx";
664		};
665
666		mmu_dsp: mmu@4a066000 {
667			compatible = "ti,omap4-iommu";
668			reg = <0x4a066000 0x100>;
669			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
670			ti,hwmods = "mmu_dsp";
671			#iommu-cells = <0>;
672		};
673
674		mmu_ipu: mmu@55082000 {
675			compatible = "ti,omap4-iommu";
676			reg = <0x55082000 0x100>;
677			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
678			ti,hwmods = "mmu_ipu";
679			#iommu-cells = <0>;
680			ti,iommu-bus-err-back;
681		};
682
683		keypad: keypad@4ae1c000 {
684			compatible = "ti,omap4-keypad";
685			reg = <0x4ae1c000 0x400>;
686			ti,hwmods = "kbd";
687		};
688
689		mcpdm: mcpdm@40132000 {
690			compatible = "ti,omap4-mcpdm";
691			reg = <0x40132000 0x7f>, /* MPU private access */
692			      <0x49032000 0x7f>; /* L3 Interconnect */
693			reg-names = "mpu", "dma";
694			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
695			ti,hwmods = "mcpdm";
696			dmas = <&sdma 65>,
697			       <&sdma 66>;
698			dma-names = "up_link", "dn_link";
699			status = "disabled";
700		};
701
702		dmic: dmic@4012e000 {
703			compatible = "ti,omap4-dmic";
704			reg = <0x4012e000 0x7f>, /* MPU private access */
705			      <0x4902e000 0x7f>; /* L3 Interconnect */
706			reg-names = "mpu", "dma";
707			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
708			ti,hwmods = "dmic";
709			dmas = <&sdma 67>;
710			dma-names = "up_link";
711			status = "disabled";
712		};
713
714		mcbsp1: mcbsp@40122000 {
715			compatible = "ti,omap4-mcbsp";
716			reg = <0x40122000 0xff>, /* MPU private access */
717			      <0x49022000 0xff>; /* L3 Interconnect */
718			reg-names = "mpu", "dma";
719			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
720			interrupt-names = "common";
721			ti,buffer-size = <128>;
722			ti,hwmods = "mcbsp1";
723			dmas = <&sdma 33>,
724			       <&sdma 34>;
725			dma-names = "tx", "rx";
726			status = "disabled";
727		};
728
729		mcbsp2: mcbsp@40124000 {
730			compatible = "ti,omap4-mcbsp";
731			reg = <0x40124000 0xff>, /* MPU private access */
732			      <0x49024000 0xff>; /* L3 Interconnect */
733			reg-names = "mpu", "dma";
734			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
735			interrupt-names = "common";
736			ti,buffer-size = <128>;
737			ti,hwmods = "mcbsp2";
738			dmas = <&sdma 17>,
739			       <&sdma 18>;
740			dma-names = "tx", "rx";
741			status = "disabled";
742		};
743
744		mcbsp3: mcbsp@40126000 {
745			compatible = "ti,omap4-mcbsp";
746			reg = <0x40126000 0xff>, /* MPU private access */
747			      <0x49026000 0xff>; /* L3 Interconnect */
748			reg-names = "mpu", "dma";
749			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
750			interrupt-names = "common";
751			ti,buffer-size = <128>;
752			ti,hwmods = "mcbsp3";
753			dmas = <&sdma 19>,
754			       <&sdma 20>;
755			dma-names = "tx", "rx";
756			status = "disabled";
757		};
758
759		mailbox: mailbox@4a0f4000 {
760			compatible = "ti,omap4-mailbox";
761			reg = <0x4a0f4000 0x200>;
762			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
763			ti,hwmods = "mailbox";
764			#mbox-cells = <1>;
765			ti,mbox-num-users = <3>;
766			ti,mbox-num-fifos = <8>;
767			mbox_ipu: mbox_ipu {
768				ti,mbox-tx = <0 0 0>;
769				ti,mbox-rx = <1 0 0>;
770			};
771			mbox_dsp: mbox_dsp {
772				ti,mbox-tx = <3 0 0>;
773				ti,mbox-rx = <2 0 0>;
774			};
775		};
776
777		timer1: timer@4ae18000 {
778			compatible = "ti,omap5430-timer";
779			reg = <0x4ae18000 0x80>;
780			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
781			ti,hwmods = "timer1";
782			ti,timer-alwon;
783			clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
784			clock-names = "fck";
785		};
786
787		timer2: timer@48032000 {
788			compatible = "ti,omap5430-timer";
789			reg = <0x48032000 0x80>;
790			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
791			ti,hwmods = "timer2";
792		};
793
794		timer3: timer@48034000 {
795			compatible = "ti,omap5430-timer";
796			reg = <0x48034000 0x80>;
797			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
798			ti,hwmods = "timer3";
799		};
800
801		timer4: timer@48036000 {
802			compatible = "ti,omap5430-timer";
803			reg = <0x48036000 0x80>;
804			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
805			ti,hwmods = "timer4";
806		};
807
808		timer5: timer@40138000 {
809			compatible = "ti,omap5430-timer";
810			reg = <0x40138000 0x80>,
811			      <0x49038000 0x80>;
812			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
813			ti,hwmods = "timer5";
814			ti,timer-dsp;
815			ti,timer-pwm;
816		};
817
818		timer6: timer@4013a000 {
819			compatible = "ti,omap5430-timer";
820			reg = <0x4013a000 0x80>,
821			      <0x4903a000 0x80>;
822			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
823			ti,hwmods = "timer6";
824			ti,timer-dsp;
825			ti,timer-pwm;
826		};
827
828		timer7: timer@4013c000 {
829			compatible = "ti,omap5430-timer";
830			reg = <0x4013c000 0x80>,
831			      <0x4903c000 0x80>;
832			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
833			ti,hwmods = "timer7";
834			ti,timer-dsp;
835		};
836
837		timer8: timer@4013e000 {
838			compatible = "ti,omap5430-timer";
839			reg = <0x4013e000 0x80>,
840			      <0x4903e000 0x80>;
841			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
842			ti,hwmods = "timer8";
843			ti,timer-dsp;
844			ti,timer-pwm;
845		};
846
847		timer9: timer@4803e000 {
848			compatible = "ti,omap5430-timer";
849			reg = <0x4803e000 0x80>;
850			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
851			ti,hwmods = "timer9";
852			ti,timer-pwm;
853		};
854
855		timer10: timer@48086000 {
856			compatible = "ti,omap5430-timer";
857			reg = <0x48086000 0x80>;
858			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
859			ti,hwmods = "timer10";
860			ti,timer-pwm;
861		};
862
863		timer11: timer@48088000 {
864			compatible = "ti,omap5430-timer";
865			reg = <0x48088000 0x80>;
866			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
867			ti,hwmods = "timer11";
868			ti,timer-pwm;
869		};
870
871		wdt2: wdt@4ae14000 {
872			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
873			reg = <0x4ae14000 0x80>;
874			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
875			ti,hwmods = "wd_timer2";
876		};
877
878		dmm@4e000000 {
879			compatible = "ti,omap5-dmm";
880			reg = <0x4e000000 0x800>;
881			interrupts = <0 113 0x4>;
882			ti,hwmods = "dmm";
883		};
884
885		emif1: emif@4c000000 {
886			compatible	= "ti,emif-4d5";
887			ti,hwmods	= "emif1";
888			ti,no-idle-on-init;
889			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
890			reg = <0x4c000000 0x400>;
891			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
892			hw-caps-read-idle-ctrl;
893			hw-caps-ll-interface;
894			hw-caps-temp-alert;
895		};
896
897		emif2: emif@4d000000 {
898			compatible	= "ti,emif-4d5";
899			ti,hwmods	= "emif2";
900			ti,no-idle-on-init;
901			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
902			reg = <0x4d000000 0x400>;
903			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
904			hw-caps-read-idle-ctrl;
905			hw-caps-ll-interface;
906			hw-caps-temp-alert;
907		};
908
909		usb3: omap_dwc3@4a020000 {
910			compatible = "ti,dwc3";
911			ti,hwmods = "usb_otg_ss";
912			reg = <0x4a020000 0x10000>;
913			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
914			#address-cells = <1>;
915			#size-cells = <1>;
916			utmi-mode = <2>;
917			ranges;
918			dwc3: dwc3@4a030000 {
919				compatible = "snps,dwc3";
920				reg = <0x4a030000 0x10000>;
921				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
922					     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
923					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
924				interrupt-names = "peripheral",
925						  "host",
926						  "otg";
927				phys = <&usb2_phy>, <&usb3_phy>;
928				phy-names = "usb2-phy", "usb3-phy";
929				dr_mode = "peripheral";
930			};
931		};
932
933		ocp2scp@4a080000 {
934			compatible = "ti,omap-ocp2scp";
935			#address-cells = <1>;
936			#size-cells = <1>;
937			reg = <0x4a080000 0x20>;
938			ranges;
939			ti,hwmods = "ocp2scp1";
940			usb2_phy: usb2phy@4a084000 {
941				compatible = "ti,omap-usb2";
942				reg = <0x4a084000 0x7c>;
943				syscon-phy-power = <&scm_conf 0x300>;
944				clocks = <&usb_phy_cm_clk32k>,
945					 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
946				clock-names = "wkupclk", "refclk";
947				#phy-cells = <0>;
948			};
949
950			usb3_phy: usb3phy@4a084400 {
951				compatible = "ti,omap-usb3";
952				reg = <0x4a084400 0x80>,
953				      <0x4a084800 0x64>,
954				      <0x4a084c00 0x40>;
955				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
956				syscon-phy-power = <&scm_conf 0x370>;
957				clocks = <&usb_phy_cm_clk32k>,
958					 <&sys_clkin>,
959					 <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
960				clock-names =	"wkupclk",
961						"sysclk",
962						"refclk";
963				#phy-cells = <0>;
964			};
965		};
966
967		usbhstll: usbhstll@4a062000 {
968			compatible = "ti,usbhs-tll";
969			reg = <0x4a062000 0x1000>;
970			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
971			ti,hwmods = "usb_tll_hs";
972		};
973
974		usbhshost: usbhshost@4a064000 {
975			compatible = "ti,usbhs-host";
976			reg = <0x4a064000 0x800>;
977			ti,hwmods = "usb_host_hs";
978			#address-cells = <1>;
979			#size-cells = <1>;
980			ranges;
981			clocks = <&l3init_60m_fclk>,
982				 <&xclk60mhsp1_ck>,
983				 <&xclk60mhsp2_ck>;
984			clock-names = "refclk_60m_int",
985				      "refclk_60m_ext_p1",
986				      "refclk_60m_ext_p2";
987
988			usbhsohci: ohci@4a064800 {
989				compatible = "ti,ohci-omap3";
990				reg = <0x4a064800 0x400>;
991				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
992				remote-wakeup-connected;
993			};
994
995			usbhsehci: ehci@4a064c00 {
996				compatible = "ti,ehci-omap";
997				reg = <0x4a064c00 0x400>;
998				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
999			};
1000		};
1001
1002		bandgap: bandgap@4a0021e0 {
1003			reg = <0x4a0021e0 0xc
1004			       0x4a00232c 0xc
1005			       0x4a002380 0x2c
1006			       0x4a0023C0 0x3c>;
1007			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1008			compatible = "ti,omap5430-bandgap";
1009
1010			#thermal-sensor-cells = <1>;
1011		};
1012
1013		/* OCP2SCP3 */
1014		ocp2scp@4a090000 {
1015			compatible = "ti,omap-ocp2scp";
1016			#address-cells = <1>;
1017			#size-cells = <1>;
1018			reg = <0x4a090000 0x20>;
1019			ranges;
1020			ti,hwmods = "ocp2scp3";
1021			sata_phy: phy@4a096000 {
1022				compatible = "ti,phy-pipe3-sata";
1023				reg = <0x4A096000 0x80>, /* phy_rx */
1024				      <0x4A096400 0x64>, /* phy_tx */
1025				      <0x4A096800 0x40>; /* pll_ctrl */
1026				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1027				syscon-phy-power = <&scm_conf 0x374>;
1028				clocks = <&sys_clkin>,
1029					 <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1030				clock-names = "sysclk", "refclk";
1031				#phy-cells = <0>;
1032			};
1033		};
1034
1035		sata: sata@4a141100 {
1036			compatible = "snps,dwc-ahci";
1037			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1038			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1039			phys = <&sata_phy>;
1040			phy-names = "sata-phy";
1041			clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1042			ti,hwmods = "sata";
1043			ports-implemented = <0x1>;
1044		};
1045
1046		dss: dss@58000000 {
1047			compatible = "ti,omap5-dss";
1048			reg = <0x58000000 0x80>;
1049			status = "disabled";
1050			ti,hwmods = "dss_core";
1051			clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1052			clock-names = "fck";
1053			#address-cells = <1>;
1054			#size-cells = <1>;
1055			ranges;
1056
1057			dispc@58001000 {
1058				compatible = "ti,omap5-dispc";
1059				reg = <0x58001000 0x1000>;
1060				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1061				ti,hwmods = "dss_dispc";
1062				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1063				clock-names = "fck";
1064			};
1065
1066			rfbi: encoder@58002000  {
1067				compatible = "ti,omap5-rfbi";
1068				reg = <0x58002000 0x100>;
1069				status = "disabled";
1070				ti,hwmods = "dss_rfbi";
1071				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1072				clock-names = "fck", "ick";
1073			};
1074
1075			dsi1: encoder@58004000 {
1076				compatible = "ti,omap5-dsi";
1077				reg = <0x58004000 0x200>,
1078				      <0x58004200 0x40>,
1079				      <0x58004300 0x40>;
1080				reg-names = "proto", "phy", "pll";
1081				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1082				status = "disabled";
1083				ti,hwmods = "dss_dsi1";
1084				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1085					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1086				clock-names = "fck", "sys_clk";
1087			};
1088
1089			dsi2: encoder@58005000 {
1090				compatible = "ti,omap5-dsi";
1091				reg = <0x58009000 0x200>,
1092				      <0x58009200 0x40>,
1093				      <0x58009300 0x40>;
1094				reg-names = "proto", "phy", "pll";
1095				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1096				status = "disabled";
1097				ti,hwmods = "dss_dsi2";
1098				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1099					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1100				clock-names = "fck", "sys_clk";
1101			};
1102
1103			hdmi: encoder@58060000 {
1104				compatible = "ti,omap5-hdmi";
1105				reg = <0x58040000 0x200>,
1106				      <0x58040200 0x80>,
1107				      <0x58040300 0x80>,
1108				      <0x58060000 0x19000>;
1109				reg-names = "wp", "pll", "phy", "core";
1110				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1111				status = "disabled";
1112				ti,hwmods = "dss_hdmi";
1113				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1114					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1115				clock-names = "fck", "sys_clk";
1116				dmas = <&sdma 76>;
1117				dma-names = "audio_tx";
1118			};
1119		};
1120
1121		abb_mpu: regulator-abb-mpu {
1122			compatible = "ti,abb-v2";
1123			regulator-name = "abb_mpu";
1124			#address-cells = <0>;
1125			#size-cells = <0>;
1126			clocks = <&sys_clkin>;
1127			ti,settling-time = <50>;
1128			ti,clock-cycles = <16>;
1129
1130			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1131			      <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1132			reg-names = "base-address", "int-address",
1133				    "efuse-address", "ldo-address";
1134			ti,tranxdone-status-mask = <0x80>;
1135			/* LDOVBBMPU_MUX_CTRL */
1136			ti,ldovbb-override-mask = <0x400>;
1137			/* LDOVBBMPU_VSET_OUT */
1138			ti,ldovbb-vset-mask = <0x1F>;
1139
1140			/*
1141			 * NOTE: only FBB mode used but actual vset will
1142			 * determine final biasing
1143			 */
1144			ti,abb_info = <
1145			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1146			1060000		0	0x0	0 0x02000000 0x01F00000
1147			1250000		0	0x4	0 0x02000000 0x01F00000
1148			>;
1149		};
1150
1151		abb_mm: regulator-abb-mm {
1152			compatible = "ti,abb-v2";
1153			regulator-name = "abb_mm";
1154			#address-cells = <0>;
1155			#size-cells = <0>;
1156			clocks = <&sys_clkin>;
1157			ti,settling-time = <50>;
1158			ti,clock-cycles = <16>;
1159
1160			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1161			      <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1162			reg-names = "base-address", "int-address",
1163				    "efuse-address", "ldo-address";
1164			ti,tranxdone-status-mask = <0x80000000>;
1165			/* LDOVBBMM_MUX_CTRL */
1166			ti,ldovbb-override-mask = <0x400>;
1167			/* LDOVBBMM_VSET_OUT */
1168			ti,ldovbb-vset-mask = <0x1F>;
1169
1170			/*
1171			 * NOTE: only FBB mode used but actual vset will
1172			 * determine final biasing
1173			 */
1174			ti,abb_info = <
1175			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
1176			1025000		0	0x0	0 0x02000000 0x01F00000
1177			1120000		0	0x4	0 0x02000000 0x01F00000
1178			>;
1179		};
1180	};
1181};
1182
1183&cpu_thermal {
1184	polling-delay = <500>; /* milliseconds */
1185	coefficients = <65 (-1791)>;
1186};
1187
1188#include "omap54xx-clocks.dtsi"
1189
1190&gpu_thermal {
1191	coefficients = <117 (-2992)>;
1192};
1193
1194&core_thermal {
1195	coefficients = <0 2000>;
1196};
1197