1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77470 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a77470-cpg-mssr.h> 11/ { 12 compatible = "renesas,r8a77470"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a7"; 23 reg = <0>; 24 clock-frequency = <1000000000>; 25 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; 26 power-domains = <&sysc 5>; 27 next-level-cache = <&L2_CA7>; 28 }; 29 30 31 L2_CA7: cache-controller-0 { 32 compatible = "cache"; 33 cache-unified; 34 cache-level = <2>; 35 power-domains = <&sysc 21>; 36 }; 37 }; 38 39 /* External root clock */ 40 extal_clk: extal { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 /* This value must be overridden by the board. */ 44 clock-frequency = <0>; 45 }; 46 47 /* External SCIF clock */ 48 scif_clk: scif { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 /* This value must be overridden by the board. */ 52 clock-frequency = <0>; 53 }; 54 55 soc { 56 compatible = "simple-bus"; 57 interrupt-parent = <&gic>; 58 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 63 cpg: clock-controller@e6150000 { 64 compatible = "renesas,r8a77470-cpg-mssr"; 65 reg = <0 0xe6150000 0 0x1000>; 66 clocks = <&extal_clk>, <&usb_extal_clk>; 67 clock-names = "extal", "usb_extal"; 68 #clock-cells = <2>; 69 #power-domain-cells = <0>; 70 #reset-cells = <1>; 71 }; 72 73 rst: reset-controller@e6160000 { 74 compatible = "renesas,r8a77470-rst"; 75 reg = <0 0xe6160000 0 0x100>; 76 }; 77 78 sysc: system-controller@e6180000 { 79 compatible = "renesas,r8a77470-sysc"; 80 reg = <0 0xe6180000 0 0x200>; 81 #power-domain-cells = <1>; 82 }; 83 84 irqc: interrupt-controller@e61c0000 { 85 compatible = "renesas,irqc-r8a77470", "renesas,irqc"; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 reg = <0 0xe61c0000 0 0x200>; 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&cpg CPG_MOD 407>; 100 power-domains = <&sysc 32>; 101 resets = <&cpg 407>; 102 }; 103 104 icram0: sram@e63a0000 { 105 compatible = "mmio-sram"; 106 reg = <0 0xe63a0000 0 0x12000>; 107 }; 108 109 icram1: sram@e63c0000 { 110 compatible = "mmio-sram"; 111 reg = <0 0xe63c0000 0 0x1000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0 0 0xe63c0000 0x1000>; 115 116 smp-sram@0 { 117 compatible = "renesas,smp-sram"; 118 reg = <0 0x100>; 119 }; 120 }; 121 122 icram2: sram@e6300000 { 123 compatible = "mmio-sram"; 124 reg = <0 0xe6300000 0 0x20000>; 125 }; 126 127 dmac0: dma-controller@e6700000 { 128 compatible = "renesas,dmac-r8a77470", 129 "renesas,rcar-dmac"; 130 reg = <0 0xe6700000 0 0x20000>; 131 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 132 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 133 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 134 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 135 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 136 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 137 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 138 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 139 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 140 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 141 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 142 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 143 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 144 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 145 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 146 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "error", 148 "ch0", "ch1", "ch2", "ch3", 149 "ch4", "ch5", "ch6", "ch7", 150 "ch8", "ch9", "ch10", "ch11", 151 "ch12", "ch13", "ch14"; 152 clocks = <&cpg CPG_MOD 219>; 153 clock-names = "fck"; 154 power-domains = <&sysc 32>; 155 resets = <&cpg 219>; 156 #dma-cells = <1>; 157 dma-channels = <15>; 158 }; 159 160 dmac1: dma-controller@e6720000 { 161 compatible = "renesas,dmac-r8a77470", 162 "renesas,rcar-dmac"; 163 reg = <0 0xe6720000 0 0x20000>; 164 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 165 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 166 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 167 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 168 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 169 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 170 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 171 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 172 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 173 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 174 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 175 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 176 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 177 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 178 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 179 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 180 interrupt-names = "error", 181 "ch0", "ch1", "ch2", "ch3", 182 "ch4", "ch5", "ch6", "ch7", 183 "ch8", "ch9", "ch10", "ch11", 184 "ch12", "ch13", "ch14"; 185 clocks = <&cpg CPG_MOD 218>; 186 clock-names = "fck"; 187 power-domains = <&sysc 32>; 188 resets = <&cpg 218>; 189 #dma-cells = <1>; 190 dma-channels = <15>; 191 }; 192 193 avb: ethernet@e6800000 { 194 compatible = "renesas,etheravb-r8a77470", 195 "renesas,etheravb-rcar-gen2"; 196 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 197 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&cpg CPG_MOD 812>; 199 power-domains = <&sysc 32>; 200 resets = <&cpg 812>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 status = "disabled"; 204 }; 205 206 scif0: serial@e6e60000 { 207 compatible = "renesas,scif-r8a77470", 208 "renesas,rcar-gen2-scif", "renesas,scif"; 209 reg = <0 0xe6e60000 0 0x40>; 210 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&cpg CPG_MOD 721>, 212 <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 213 clock-names = "fck", "brg_int", "scif_clk"; 214 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 215 <&dmac1 0x29>, <&dmac1 0x2a>; 216 dma-names = "tx", "rx", "tx", "rx"; 217 power-domains = <&sysc 32>; 218 resets = <&cpg 721>; 219 status = "disabled"; 220 }; 221 222 scif1: serial@e6e68000 { 223 compatible = "renesas,scif-r8a77470", 224 "renesas,rcar-gen2-scif", "renesas,scif"; 225 reg = <0 0xe6e68000 0 0x40>; 226 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cpg CPG_MOD 720>, 228 <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 229 clock-names = "fck", "brg_int", "scif_clk"; 230 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 231 <&dmac1 0x2d>, <&dmac1 0x2e>; 232 dma-names = "tx", "rx", "tx", "rx"; 233 power-domains = <&sysc 32>; 234 resets = <&cpg 720>; 235 status = "disabled"; 236 }; 237 238 scif2: serial@e6e58000 { 239 compatible = "renesas,scif-r8a77470", 240 "renesas,rcar-gen2-scif", "renesas,scif"; 241 reg = <0 0xe6e58000 0 0x40>; 242 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cpg CPG_MOD 719>, 244 <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 245 clock-names = "fck", "brg_int", "scif_clk"; 246 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 247 <&dmac1 0x2b>, <&dmac1 0x2c>; 248 dma-names = "tx", "rx", "tx", "rx"; 249 power-domains = <&sysc 32>; 250 resets = <&cpg 719>; 251 status = "disabled"; 252 }; 253 254 scif3: serial@e6ea8000 { 255 compatible = "renesas,scif-r8a77470", 256 "renesas,rcar-gen2-scif", "renesas,scif"; 257 reg = <0 0xe6ea8000 0 0x40>; 258 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cpg CPG_MOD 718>, 260 <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 261 clock-names = "fck", "brg_int", "scif_clk"; 262 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 263 <&dmac1 0x2f>, <&dmac1 0x30>; 264 dma-names = "tx", "rx", "tx", "rx"; 265 power-domains = <&sysc 32>; 266 resets = <&cpg 718>; 267 status = "disabled"; 268 }; 269 270 scif4: serial@e6ee0000 { 271 compatible = "renesas,scif-r8a77470", 272 "renesas,rcar-gen2-scif", "renesas,scif"; 273 reg = <0 0xe6ee0000 0 0x40>; 274 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&cpg CPG_MOD 715>, 276 <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 277 clock-names = "fck", "brg_int", "scif_clk"; 278 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 279 <&dmac1 0xfb>, <&dmac1 0xfc>; 280 dma-names = "tx", "rx", "tx", "rx"; 281 power-domains = <&sysc 32>; 282 resets = <&cpg 715>; 283 status = "disabled"; 284 }; 285 286 scif5: serial@e6ee8000 { 287 compatible = "renesas,scif-r8a77470", 288 "renesas,rcar-gen2-scif", "renesas,scif"; 289 reg = <0 0xe6ee8000 0 0x40>; 290 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&cpg CPG_MOD 714>, 292 <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; 293 clock-names = "fck", "brg_int", "scif_clk"; 294 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 295 <&dmac1 0xfd>, <&dmac1 0xfe>; 296 dma-names = "tx", "rx", "tx", "rx"; 297 power-domains = <&sysc 32>; 298 resets = <&cpg 714>; 299 status = "disabled"; 300 }; 301 302 gic: interrupt-controller@f1001000 { 303 compatible = "arm,gic-400"; 304 #interrupt-cells = <3>; 305 #address-cells = <0>; 306 interrupt-controller; 307 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, 308 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; 309 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 310 clocks = <&cpg CPG_MOD 408>; 311 clock-names = "clk"; 312 power-domains = <&sysc 32>; 313 resets = <&cpg 408>; 314 }; 315 316 prr: chipid@ff000044 { 317 compatible = "renesas,prr"; 318 reg = <0 0xff000044 0 4>; 319 }; 320 }; 321 322 timer { 323 compatible = "arm,armv7-timer"; 324 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 325 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 326 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 327 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 328 }; 329 330 /* External USB clock - can be overridden by the board */ 331 usb_extal_clk: usb_extal { 332 compatible = "fixed-clock"; 333 #clock-cells = <0>; 334 clock-frequency = <48000000>; 335 }; 336}; 337