1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3288-cru.h> 8#include <dt-bindings/power/rk3288-power.h> 9#include <dt-bindings/thermal/thermal.h> 10#include <dt-bindings/power/rk3288-power.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 compatible = "rockchip,rk3288"; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 mshc0 = &emmc; 30 mshc1 = &sdmmc; 31 mshc2 = &sdio0; 32 mshc3 = &sdio1; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 spi2 = &spi2; 41 }; 42 43 arm-pmu { 44 compatible = "arm,cortex-a12-pmu"; 45 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 49 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3066-smp"; 56 rockchip,pmu = <&pmu>; 57 58 cpu0: cpu@500 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a12"; 61 reg = <0x500>; 62 resets = <&cru SRST_CORE0>; 63 operating-points-v2 = <&cpu_opp_table>; 64 #cooling-cells = <2>; /* min followed by max */ 65 clock-latency = <40000>; 66 clocks = <&cru ARMCLK>; 67 }; 68 cpu1: cpu@501 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a12"; 71 reg = <0x501>; 72 resets = <&cru SRST_CORE1>; 73 operating-points-v2 = <&cpu_opp_table>; 74 #cooling-cells = <2>; /* min followed by max */ 75 clock-latency = <40000>; 76 clocks = <&cru ARMCLK>; 77 }; 78 cpu2: cpu@502 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a12"; 81 reg = <0x502>; 82 resets = <&cru SRST_CORE2>; 83 operating-points-v2 = <&cpu_opp_table>; 84 #cooling-cells = <2>; /* min followed by max */ 85 clock-latency = <40000>; 86 clocks = <&cru ARMCLK>; 87 }; 88 cpu3: cpu@503 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a12"; 91 reg = <0x503>; 92 resets = <&cru SRST_CORE3>; 93 operating-points-v2 = <&cpu_opp_table>; 94 #cooling-cells = <2>; /* min followed by max */ 95 clock-latency = <40000>; 96 clocks = <&cru ARMCLK>; 97 }; 98 }; 99 100 cpu_opp_table: cpu-opp-table { 101 compatible = "operating-points-v2"; 102 opp-shared; 103 104 opp-126000000 { 105 opp-hz = /bits/ 64 <126000000>; 106 opp-microvolt = <900000>; 107 }; 108 opp-216000000 { 109 opp-hz = /bits/ 64 <216000000>; 110 opp-microvolt = <900000>; 111 }; 112 opp-312000000 { 113 opp-hz = /bits/ 64 <312000000>; 114 opp-microvolt = <900000>; 115 }; 116 opp-408000000 { 117 opp-hz = /bits/ 64 <408000000>; 118 opp-microvolt = <900000>; 119 }; 120 opp-600000000 { 121 opp-hz = /bits/ 64 <600000000>; 122 opp-microvolt = <900000>; 123 }; 124 opp-696000000 { 125 opp-hz = /bits/ 64 <696000000>; 126 opp-microvolt = <950000>; 127 }; 128 opp-816000000 { 129 opp-hz = /bits/ 64 <816000000>; 130 opp-microvolt = <1000000>; 131 }; 132 opp-1008000000 { 133 opp-hz = /bits/ 64 <1008000000>; 134 opp-microvolt = <1050000>; 135 }; 136 opp-1200000000 { 137 opp-hz = /bits/ 64 <1200000000>; 138 opp-microvolt = <1100000>; 139 }; 140 opp-1416000000 { 141 opp-hz = /bits/ 64 <1416000000>; 142 opp-microvolt = <1200000>; 143 }; 144 opp-1512000000 { 145 opp-hz = /bits/ 64 <1512000000>; 146 opp-microvolt = <1300000>; 147 }; 148 opp-1608000000 { 149 opp-hz = /bits/ 64 <1608000000>; 150 opp-microvolt = <1350000>; 151 }; 152 }; 153 154 amba { 155 compatible = "simple-bus"; 156 #address-cells = <2>; 157 #size-cells = <2>; 158 ranges; 159 160 dmac_peri: dma-controller@ff250000 { 161 compatible = "arm,pl330", "arm,primecell"; 162 reg = <0x0 0xff250000 0x0 0x4000>; 163 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 165 #dma-cells = <1>; 166 arm,pl330-broken-no-flushp; 167 clocks = <&cru ACLK_DMAC2>; 168 clock-names = "apb_pclk"; 169 }; 170 171 dmac_bus_ns: dma-controller@ff600000 { 172 compatible = "arm,pl330", "arm,primecell"; 173 reg = <0x0 0xff600000 0x0 0x4000>; 174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 arm,pl330-broken-no-flushp; 178 clocks = <&cru ACLK_DMAC1>; 179 clock-names = "apb_pclk"; 180 status = "disabled"; 181 }; 182 183 dmac_bus_s: dma-controller@ffb20000 { 184 compatible = "arm,pl330", "arm,primecell"; 185 reg = <0x0 0xffb20000 0x0 0x4000>; 186 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 188 #dma-cells = <1>; 189 arm,pl330-broken-no-flushp; 190 clocks = <&cru ACLK_DMAC1>; 191 clock-names = "apb_pclk"; 192 }; 193 }; 194 195 reserved-memory { 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges; 199 200 /* 201 * The rk3288 cannot use the memory area above 0xfe000000 202 * for dma operations for some reason. While there is 203 * probably a better solution available somewhere, we 204 * haven't found it yet and while devices with 2GB of ram 205 * are not affected, this issue prevents 4GB from booting. 206 * So to make these devices at least bootable, block 207 * this area for the time being until the real solution 208 * is found. 209 */ 210 dma-unusable@fe000000 { 211 reg = <0x0 0xfe000000 0x0 0x1000000>; 212 }; 213 }; 214 215 xin24m: oscillator { 216 compatible = "fixed-clock"; 217 clock-frequency = <24000000>; 218 clock-output-names = "xin24m"; 219 #clock-cells = <0>; 220 }; 221 222 timer { 223 compatible = "arm,armv7-timer"; 224 arm,cpu-registers-not-fw-configured; 225 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 226 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 227 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 228 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 229 clock-frequency = <24000000>; 230 arm,no-tick-in-suspend; 231 }; 232 233 timer: timer@ff810000 { 234 compatible = "rockchip,rk3288-timer"; 235 reg = <0x0 0xff810000 0x0 0x20>; 236 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&xin24m>, <&cru PCLK_TIMER>; 238 clock-names = "timer", "pclk"; 239 }; 240 241 display-subsystem { 242 compatible = "rockchip,display-subsystem"; 243 ports = <&vopl_out>, <&vopb_out>; 244 }; 245 246 sdmmc: dwmmc@ff0c0000 { 247 compatible = "rockchip,rk3288-dw-mshc"; 248 max-frequency = <150000000>; 249 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 250 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 251 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 252 fifo-depth = <0x100>; 253 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 254 reg = <0x0 0xff0c0000 0x0 0x4000>; 255 resets = <&cru SRST_MMC0>; 256 reset-names = "reset"; 257 status = "disabled"; 258 }; 259 260 sdio0: dwmmc@ff0d0000 { 261 compatible = "rockchip,rk3288-dw-mshc"; 262 max-frequency = <150000000>; 263 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 264 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 265 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 266 fifo-depth = <0x100>; 267 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 268 reg = <0x0 0xff0d0000 0x0 0x4000>; 269 resets = <&cru SRST_SDIO0>; 270 reset-names = "reset"; 271 status = "disabled"; 272 }; 273 274 sdio1: dwmmc@ff0e0000 { 275 compatible = "rockchip,rk3288-dw-mshc"; 276 max-frequency = <150000000>; 277 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 278 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 279 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 280 fifo-depth = <0x100>; 281 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 282 reg = <0x0 0xff0e0000 0x0 0x4000>; 283 resets = <&cru SRST_SDIO1>; 284 reset-names = "reset"; 285 status = "disabled"; 286 }; 287 288 emmc: dwmmc@ff0f0000 { 289 compatible = "rockchip,rk3288-dw-mshc"; 290 max-frequency = <150000000>; 291 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 292 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 293 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 294 fifo-depth = <0x100>; 295 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 296 reg = <0x0 0xff0f0000 0x0 0x4000>; 297 resets = <&cru SRST_EMMC>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 saradc: saradc@ff100000 { 303 compatible = "rockchip,saradc"; 304 reg = <0x0 0xff100000 0x0 0x100>; 305 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 306 #io-channel-cells = <1>; 307 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 308 clock-names = "saradc", "apb_pclk"; 309 resets = <&cru SRST_SARADC>; 310 reset-names = "saradc-apb"; 311 status = "disabled"; 312 }; 313 314 spi0: spi@ff110000 { 315 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 316 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 317 clock-names = "spiclk", "apb_pclk"; 318 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 319 dma-names = "tx", "rx"; 320 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 323 reg = <0x0 0xff110000 0x0 0x1000>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 status = "disabled"; 327 }; 328 329 spi1: spi@ff120000 { 330 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 331 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 332 clock-names = "spiclk", "apb_pclk"; 333 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 334 dma-names = "tx", "rx"; 335 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 338 reg = <0x0 0xff120000 0x0 0x1000>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 spi2: spi@ff130000 { 345 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 346 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 347 clock-names = "spiclk", "apb_pclk"; 348 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 349 dma-names = "tx", "rx"; 350 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 353 reg = <0x0 0xff130000 0x0 0x1000>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 359 i2c1: i2c@ff140000 { 360 compatible = "rockchip,rk3288-i2c"; 361 reg = <0x0 0xff140000 0x0 0x1000>; 362 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 clock-names = "i2c"; 366 clocks = <&cru PCLK_I2C1>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&i2c1_xfer>; 369 status = "disabled"; 370 }; 371 372 i2c3: i2c@ff150000 { 373 compatible = "rockchip,rk3288-i2c"; 374 reg = <0x0 0xff150000 0x0 0x1000>; 375 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clock-names = "i2c"; 379 clocks = <&cru PCLK_I2C3>; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&i2c3_xfer>; 382 status = "disabled"; 383 }; 384 385 i2c4: i2c@ff160000 { 386 compatible = "rockchip,rk3288-i2c"; 387 reg = <0x0 0xff160000 0x0 0x1000>; 388 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clock-names = "i2c"; 392 clocks = <&cru PCLK_I2C4>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&i2c4_xfer>; 395 status = "disabled"; 396 }; 397 398 i2c5: i2c@ff170000 { 399 compatible = "rockchip,rk3288-i2c"; 400 reg = <0x0 0xff170000 0x0 0x1000>; 401 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 clock-names = "i2c"; 405 clocks = <&cru PCLK_I2C5>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&i2c5_xfer>; 408 status = "disabled"; 409 }; 410 411 uart0: serial@ff180000 { 412 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 413 reg = <0x0 0xff180000 0x0 0x100>; 414 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 415 reg-shift = <2>; 416 reg-io-width = <4>; 417 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 418 clock-names = "baudclk", "apb_pclk"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&uart0_xfer>; 421 status = "disabled"; 422 }; 423 424 uart1: serial@ff190000 { 425 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 426 reg = <0x0 0xff190000 0x0 0x100>; 427 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 428 reg-shift = <2>; 429 reg-io-width = <4>; 430 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 431 clock-names = "baudclk", "apb_pclk"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&uart1_xfer>; 434 status = "disabled"; 435 }; 436 437 uart2: serial@ff690000 { 438 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 439 reg = <0x0 0xff690000 0x0 0x100>; 440 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 441 reg-shift = <2>; 442 reg-io-width = <4>; 443 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 444 clock-names = "baudclk", "apb_pclk"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&uart2_xfer>; 447 status = "disabled"; 448 }; 449 450 uart3: serial@ff1b0000 { 451 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 452 reg = <0x0 0xff1b0000 0x0 0x100>; 453 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 454 reg-shift = <2>; 455 reg-io-width = <4>; 456 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 457 clock-names = "baudclk", "apb_pclk"; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&uart3_xfer>; 460 status = "disabled"; 461 }; 462 463 uart4: serial@ff1c0000 { 464 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 465 reg = <0x0 0xff1c0000 0x0 0x100>; 466 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 467 reg-shift = <2>; 468 reg-io-width = <4>; 469 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 470 clock-names = "baudclk", "apb_pclk"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&uart4_xfer>; 473 status = "disabled"; 474 }; 475 476 thermal-zones { 477 reserve_thermal: reserve_thermal { 478 polling-delay-passive = <1000>; /* milliseconds */ 479 polling-delay = <5000>; /* milliseconds */ 480 481 thermal-sensors = <&tsadc 0>; 482 }; 483 484 cpu_thermal: cpu_thermal { 485 polling-delay-passive = <100>; /* milliseconds */ 486 polling-delay = <5000>; /* milliseconds */ 487 488 thermal-sensors = <&tsadc 1>; 489 490 trips { 491 cpu_alert0: cpu_alert0 { 492 temperature = <70000>; /* millicelsius */ 493 hysteresis = <2000>; /* millicelsius */ 494 type = "passive"; 495 }; 496 cpu_alert1: cpu_alert1 { 497 temperature = <75000>; /* millicelsius */ 498 hysteresis = <2000>; /* millicelsius */ 499 type = "passive"; 500 }; 501 cpu_crit: cpu_crit { 502 temperature = <90000>; /* millicelsius */ 503 hysteresis = <2000>; /* millicelsius */ 504 type = "critical"; 505 }; 506 }; 507 508 cooling-maps { 509 map0 { 510 trip = <&cpu_alert0>; 511 cooling-device = 512 <&cpu0 THERMAL_NO_LIMIT 6>; 513 }; 514 map1 { 515 trip = <&cpu_alert1>; 516 cooling-device = 517 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 518 }; 519 }; 520 }; 521 522 gpu_thermal: gpu_thermal { 523 polling-delay-passive = <100>; /* milliseconds */ 524 polling-delay = <5000>; /* milliseconds */ 525 526 thermal-sensors = <&tsadc 2>; 527 528 trips { 529 gpu_alert0: gpu_alert0 { 530 temperature = <70000>; /* millicelsius */ 531 hysteresis = <2000>; /* millicelsius */ 532 type = "passive"; 533 }; 534 gpu_crit: gpu_crit { 535 temperature = <90000>; /* millicelsius */ 536 hysteresis = <2000>; /* millicelsius */ 537 type = "critical"; 538 }; 539 }; 540 541 cooling-maps { 542 map0 { 543 trip = <&gpu_alert0>; 544 cooling-device = 545 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 546 }; 547 }; 548 }; 549 }; 550 551 tsadc: tsadc@ff280000 { 552 compatible = "rockchip,rk3288-tsadc"; 553 reg = <0x0 0xff280000 0x0 0x100>; 554 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 556 clock-names = "tsadc", "apb_pclk"; 557 resets = <&cru SRST_TSADC>; 558 reset-names = "tsadc-apb"; 559 pinctrl-names = "init", "default", "sleep"; 560 pinctrl-0 = <&otp_gpio>; 561 pinctrl-1 = <&otp_out>; 562 pinctrl-2 = <&otp_gpio>; 563 #thermal-sensor-cells = <1>; 564 rockchip,hw-tshut-temp = <95000>; 565 status = "disabled"; 566 }; 567 568 gmac: ethernet@ff290000 { 569 compatible = "rockchip,rk3288-gmac"; 570 reg = <0x0 0xff290000 0x0 0x10000>; 571 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "macirq", "eth_wake_irq"; 574 rockchip,grf = <&grf>; 575 clocks = <&cru SCLK_MAC>, 576 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 577 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 578 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 579 clock-names = "stmmaceth", 580 "mac_clk_rx", "mac_clk_tx", 581 "clk_mac_ref", "clk_mac_refout", 582 "aclk_mac", "pclk_mac"; 583 resets = <&cru SRST_MAC>; 584 reset-names = "stmmaceth"; 585 status = "disabled"; 586 }; 587 588 usb_host0_ehci: usb@ff500000 { 589 compatible = "generic-ehci"; 590 reg = <0x0 0xff500000 0x0 0x100>; 591 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru HCLK_USBHOST0>; 593 clock-names = "usbhost"; 594 phys = <&usbphy1>; 595 phy-names = "usb"; 596 status = "disabled"; 597 }; 598 599 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 600 601 usb_host1: usb@ff540000 { 602 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 603 "snps,dwc2"; 604 reg = <0x0 0xff540000 0x0 0x40000>; 605 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&cru HCLK_USBHOST1>; 607 clock-names = "otg"; 608 dr_mode = "host"; 609 phys = <&usbphy2>; 610 phy-names = "usb2-phy"; 611 status = "disabled"; 612 }; 613 614 usb_otg: usb@ff580000 { 615 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 616 "snps,dwc2"; 617 reg = <0x0 0xff580000 0x0 0x40000>; 618 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru HCLK_OTG0>; 620 clock-names = "otg"; 621 dr_mode = "otg"; 622 g-np-tx-fifo-size = <16>; 623 g-rx-fifo-size = <275>; 624 g-tx-fifo-size = <256 128 128 64 64 32>; 625 phys = <&usbphy0>; 626 phy-names = "usb2-phy"; 627 status = "disabled"; 628 }; 629 630 usb_hsic: usb@ff5c0000 { 631 compatible = "generic-ehci"; 632 reg = <0x0 0xff5c0000 0x0 0x100>; 633 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cru HCLK_HSIC>; 635 clock-names = "usbhost"; 636 status = "disabled"; 637 }; 638 639 i2c0: i2c@ff650000 { 640 compatible = "rockchip,rk3288-i2c"; 641 reg = <0x0 0xff650000 0x0 0x1000>; 642 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clock-names = "i2c"; 646 clocks = <&cru PCLK_I2C0>; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&i2c0_xfer>; 649 status = "disabled"; 650 }; 651 652 i2c2: i2c@ff660000 { 653 compatible = "rockchip,rk3288-i2c"; 654 reg = <0x0 0xff660000 0x0 0x1000>; 655 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 clock-names = "i2c"; 659 clocks = <&cru PCLK_I2C2>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&i2c2_xfer>; 662 status = "disabled"; 663 }; 664 665 pwm0: pwm@ff680000 { 666 compatible = "rockchip,rk3288-pwm"; 667 reg = <0x0 0xff680000 0x0 0x10>; 668 #pwm-cells = <3>; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&pwm0_pin>; 671 clocks = <&cru PCLK_PWM>; 672 clock-names = "pwm"; 673 status = "disabled"; 674 }; 675 676 pwm1: pwm@ff680010 { 677 compatible = "rockchip,rk3288-pwm"; 678 reg = <0x0 0xff680010 0x0 0x10>; 679 #pwm-cells = <3>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pwm1_pin>; 682 clocks = <&cru PCLK_PWM>; 683 clock-names = "pwm"; 684 status = "disabled"; 685 }; 686 687 pwm2: pwm@ff680020 { 688 compatible = "rockchip,rk3288-pwm"; 689 reg = <0x0 0xff680020 0x0 0x10>; 690 #pwm-cells = <3>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pwm2_pin>; 693 clocks = <&cru PCLK_PWM>; 694 clock-names = "pwm"; 695 status = "disabled"; 696 }; 697 698 pwm3: pwm@ff680030 { 699 compatible = "rockchip,rk3288-pwm"; 700 reg = <0x0 0xff680030 0x0 0x10>; 701 #pwm-cells = <2>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pwm3_pin>; 704 clocks = <&cru PCLK_PWM>; 705 clock-names = "pwm"; 706 status = "disabled"; 707 }; 708 709 bus_intmem@ff700000 { 710 compatible = "mmio-sram"; 711 reg = <0x0 0xff700000 0x0 0x18000>; 712 #address-cells = <1>; 713 #size-cells = <1>; 714 ranges = <0 0x0 0xff700000 0x18000>; 715 smp-sram@0 { 716 compatible = "rockchip,rk3066-smp-sram"; 717 reg = <0x00 0x10>; 718 }; 719 }; 720 721 sram@ff720000 { 722 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 723 reg = <0x0 0xff720000 0x0 0x1000>; 724 }; 725 726 pmu: power-management@ff730000 { 727 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 728 reg = <0x0 0xff730000 0x0 0x100>; 729 730 power: power-controller { 731 compatible = "rockchip,rk3288-power-controller"; 732 #power-domain-cells = <1>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 736 assigned-clocks = <&cru SCLK_EDP_24M>; 737 assigned-clock-parents = <&xin24m>; 738 739 /* 740 * Note: Although SCLK_* are the working clocks 741 * of device without including on the NOC, needed for 742 * synchronous reset. 743 * 744 * The clocks on the which NOC: 745 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 746 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 747 * ACLK_RGA is on ACLK_RGA_NIU. 748 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 749 * 750 * Which clock are device clocks: 751 * clocks devices 752 * *_IEP IEP:Image Enhancement Processor 753 * *_ISP ISP:Image Signal Processing 754 * *_VIP VIP:Video Input Processor 755 * *_VOP* VOP:Visual Output Processor 756 * *_RGA RGA 757 * *_EDP* EDP 758 * *_LVDS_* LVDS 759 * *_HDMI HDMI 760 * *_MIPI_* MIPI 761 */ 762 pd_vio@RK3288_PD_VIO { 763 reg = <RK3288_PD_VIO>; 764 clocks = <&cru ACLK_IEP>, 765 <&cru ACLK_ISP>, 766 <&cru ACLK_RGA>, 767 <&cru ACLK_VIP>, 768 <&cru ACLK_VOP0>, 769 <&cru ACLK_VOP1>, 770 <&cru DCLK_VOP0>, 771 <&cru DCLK_VOP1>, 772 <&cru HCLK_IEP>, 773 <&cru HCLK_ISP>, 774 <&cru HCLK_RGA>, 775 <&cru HCLK_VIP>, 776 <&cru HCLK_VOP0>, 777 <&cru HCLK_VOP1>, 778 <&cru PCLK_EDP_CTRL>, 779 <&cru PCLK_HDMI_CTRL>, 780 <&cru PCLK_LVDS_PHY>, 781 <&cru PCLK_MIPI_CSI>, 782 <&cru PCLK_MIPI_DSI0>, 783 <&cru PCLK_MIPI_DSI1>, 784 <&cru SCLK_EDP_24M>, 785 <&cru SCLK_EDP>, 786 <&cru SCLK_ISP_JPE>, 787 <&cru SCLK_ISP>, 788 <&cru SCLK_RGA>; 789 pm_qos = <&qos_vio0_iep>, 790 <&qos_vio1_vop>, 791 <&qos_vio1_isp_w0>, 792 <&qos_vio1_isp_w1>, 793 <&qos_vio0_vop>, 794 <&qos_vio0_vip>, 795 <&qos_vio2_rga_r>, 796 <&qos_vio2_rga_w>, 797 <&qos_vio1_isp_r>; 798 }; 799 800 /* 801 * Note: The following 3 are HEVC(H.265) clocks, 802 * and on the ACLK_HEVC_NIU (NOC). 803 */ 804 pd_hevc@RK3288_PD_HEVC { 805 reg = <RK3288_PD_HEVC>; 806 clocks = <&cru ACLK_HEVC>, 807 <&cru SCLK_HEVC_CABAC>, 808 <&cru SCLK_HEVC_CORE>; 809 pm_qos = <&qos_hevc_r>, 810 <&qos_hevc_w>; 811 }; 812 813 /* 814 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 815 * (video endecoder & decoder) clocks that on the 816 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 817 */ 818 pd_video@RK3288_PD_VIDEO { 819 reg = <RK3288_PD_VIDEO>; 820 clocks = <&cru ACLK_VCODEC>, 821 <&cru HCLK_VCODEC>; 822 pm_qos = <&qos_video>; 823 }; 824 825 /* 826 * Note: ACLK_GPU is the GPU clock, 827 * and on the ACLK_GPU_NIU (NOC). 828 */ 829 pd_gpu@RK3288_PD_GPU { 830 reg = <RK3288_PD_GPU>; 831 clocks = <&cru ACLK_GPU>; 832 pm_qos = <&qos_gpu_r>, 833 <&qos_gpu_w>; 834 }; 835 }; 836 837 reboot-mode { 838 compatible = "syscon-reboot-mode"; 839 offset = <0x94>; 840 mode-normal = <BOOT_NORMAL>; 841 mode-recovery = <BOOT_RECOVERY>; 842 mode-bootloader = <BOOT_FASTBOOT>; 843 mode-loader = <BOOT_BL_DOWNLOAD>; 844 }; 845 }; 846 847 sgrf: syscon@ff740000 { 848 compatible = "rockchip,rk3288-sgrf", "syscon"; 849 reg = <0x0 0xff740000 0x0 0x1000>; 850 }; 851 852 cru: clock-controller@ff760000 { 853 compatible = "rockchip,rk3288-cru"; 854 reg = <0x0 0xff760000 0x0 0x1000>; 855 rockchip,grf = <&grf>; 856 #clock-cells = <1>; 857 #reset-cells = <1>; 858 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 859 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 860 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 861 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 862 <&cru PCLK_PERI>; 863 assigned-clock-rates = <594000000>, <400000000>, 864 <500000000>, <300000000>, 865 <150000000>, <75000000>, 866 <300000000>, <150000000>, 867 <75000000>; 868 }; 869 870 grf: syscon@ff770000 { 871 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 872 reg = <0x0 0xff770000 0x0 0x1000>; 873 874 edp_phy: edp-phy { 875 compatible = "rockchip,rk3288-dp-phy"; 876 clocks = <&cru SCLK_EDP_24M>; 877 clock-names = "24m"; 878 #phy-cells = <0>; 879 status = "disabled"; 880 }; 881 882 io_domains: io-domains { 883 compatible = "rockchip,rk3288-io-voltage-domain"; 884 status = "disabled"; 885 }; 886 887 usbphy: usbphy { 888 compatible = "rockchip,rk3288-usb-phy"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 893 usbphy0: usb-phy@320 { 894 #phy-cells = <0>; 895 reg = <0x320>; 896 clocks = <&cru SCLK_OTGPHY0>; 897 clock-names = "phyclk"; 898 #clock-cells = <0>; 899 }; 900 901 usbphy1: usb-phy@334 { 902 #phy-cells = <0>; 903 reg = <0x334>; 904 clocks = <&cru SCLK_OTGPHY1>; 905 clock-names = "phyclk"; 906 #clock-cells = <0>; 907 }; 908 909 usbphy2: usb-phy@348 { 910 #phy-cells = <0>; 911 reg = <0x348>; 912 clocks = <&cru SCLK_OTGPHY2>; 913 clock-names = "phyclk"; 914 #clock-cells = <0>; 915 }; 916 }; 917 }; 918 919 wdt: watchdog@ff800000 { 920 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 921 reg = <0x0 0xff800000 0x0 0x100>; 922 clocks = <&cru PCLK_WDT>; 923 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 924 status = "disabled"; 925 }; 926 927 spdif: sound@ff88b0000 { 928 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 929 reg = <0x0 0xff8b0000 0x0 0x10000>; 930 #sound-dai-cells = <0>; 931 clock-names = "hclk", "mclk"; 932 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 933 dmas = <&dmac_bus_s 3>; 934 dma-names = "tx"; 935 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&spdif_tx>; 938 rockchip,grf = <&grf>; 939 status = "disabled"; 940 }; 941 942 i2s: i2s@ff890000 { 943 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 944 reg = <0x0 0xff890000 0x0 0x10000>; 945 #sound-dai-cells = <0>; 946 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 950 dma-names = "tx", "rx"; 951 clock-names = "i2s_hclk", "i2s_clk"; 952 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 953 pinctrl-names = "default"; 954 pinctrl-0 = <&i2s0_bus>; 955 rockchip,playback-channels = <8>; 956 rockchip,capture-channels = <2>; 957 status = "disabled"; 958 }; 959 960 crypto: cypto-controller@ff8a0000 { 961 compatible = "rockchip,rk3288-crypto"; 962 reg = <0x0 0xff8a0000 0x0 0x4000>; 963 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 965 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 966 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 967 resets = <&cru SRST_CRYPTO>; 968 reset-names = "crypto-rst"; 969 status = "okay"; 970 }; 971 972 iep_mmu: iommu@ff900800 { 973 compatible = "rockchip,iommu"; 974 reg = <0x0 0xff900800 0x0 0x40>; 975 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 976 interrupt-names = "iep_mmu"; 977 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 978 clock-names = "aclk", "iface"; 979 #iommu-cells = <0>; 980 status = "disabled"; 981 }; 982 983 isp_mmu: iommu@ff914000 { 984 compatible = "rockchip,iommu"; 985 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 986 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 987 interrupt-names = "isp_mmu"; 988 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 989 clock-names = "aclk", "iface"; 990 #iommu-cells = <0>; 991 rockchip,disable-mmu-reset; 992 status = "disabled"; 993 }; 994 995 rga: rga@ff920000 { 996 compatible = "rockchip,rk3288-rga"; 997 reg = <0x0 0xff920000 0x0 0x180>; 998 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1000 clock-names = "aclk", "hclk", "sclk"; 1001 power-domains = <&power RK3288_PD_VIO>; 1002 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1003 reset-names = "core", "axi", "ahb"; 1004 }; 1005 1006 vopb: vop@ff930000 { 1007 compatible = "rockchip,rk3288-vop"; 1008 reg = <0x0 0xff930000 0x0 0x19c>; 1009 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1011 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1012 power-domains = <&power RK3288_PD_VIO>; 1013 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1014 reset-names = "axi", "ahb", "dclk"; 1015 iommus = <&vopb_mmu>; 1016 status = "disabled"; 1017 1018 vopb_out: port { 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 1022 vopb_out_hdmi: endpoint@0 { 1023 reg = <0>; 1024 remote-endpoint = <&hdmi_in_vopb>; 1025 }; 1026 1027 vopb_out_edp: endpoint@1 { 1028 reg = <1>; 1029 remote-endpoint = <&edp_in_vopb>; 1030 }; 1031 1032 vopb_out_mipi: endpoint@2 { 1033 reg = <2>; 1034 remote-endpoint = <&mipi_in_vopb>; 1035 }; 1036 1037 vopb_out_lvds: endpoint@3 { 1038 reg = <3>; 1039 remote-endpoint = <&lvds_in_vopb>; 1040 }; 1041 }; 1042 }; 1043 1044 vopb_mmu: iommu@ff930300 { 1045 compatible = "rockchip,iommu"; 1046 reg = <0x0 0xff930300 0x0 0x100>; 1047 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1048 interrupt-names = "vopb_mmu"; 1049 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1050 clock-names = "aclk", "iface"; 1051 power-domains = <&power RK3288_PD_VIO>; 1052 #iommu-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 vopl: vop@ff940000 { 1057 compatible = "rockchip,rk3288-vop"; 1058 reg = <0x0 0xff940000 0x0 0x19c>; 1059 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1061 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1062 power-domains = <&power RK3288_PD_VIO>; 1063 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1064 reset-names = "axi", "ahb", "dclk"; 1065 iommus = <&vopl_mmu>; 1066 status = "disabled"; 1067 1068 vopl_out: port { 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 1072 vopl_out_hdmi: endpoint@0 { 1073 reg = <0>; 1074 remote-endpoint = <&hdmi_in_vopl>; 1075 }; 1076 1077 vopl_out_edp: endpoint@1 { 1078 reg = <1>; 1079 remote-endpoint = <&edp_in_vopl>; 1080 }; 1081 1082 vopl_out_mipi: endpoint@2 { 1083 reg = <2>; 1084 remote-endpoint = <&mipi_in_vopl>; 1085 }; 1086 1087 vopl_out_lvds: endpoint@3 { 1088 reg = <3>; 1089 remote-endpoint = <&lvds_in_vopl>; 1090 }; 1091 }; 1092 }; 1093 1094 vopl_mmu: iommu@ff940300 { 1095 compatible = "rockchip,iommu"; 1096 reg = <0x0 0xff940300 0x0 0x100>; 1097 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1098 interrupt-names = "vopl_mmu"; 1099 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1100 clock-names = "aclk", "iface"; 1101 power-domains = <&power RK3288_PD_VIO>; 1102 #iommu-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 mipi_dsi: mipi@ff960000 { 1107 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1108 reg = <0x0 0xff960000 0x0 0x4000>; 1109 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1111 clock-names = "ref", "pclk"; 1112 power-domains = <&power RK3288_PD_VIO>; 1113 rockchip,grf = <&grf>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 status = "disabled"; 1117 1118 ports { 1119 mipi_in: port { 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 mipi_in_vopb: endpoint@0 { 1123 reg = <0>; 1124 remote-endpoint = <&vopb_out_mipi>; 1125 }; 1126 mipi_in_vopl: endpoint@1 { 1127 reg = <1>; 1128 remote-endpoint = <&vopl_out_mipi>; 1129 }; 1130 }; 1131 }; 1132 }; 1133 1134 lvds: lvds@ff96c000 { 1135 compatible = "rockchip,rk3288-lvds"; 1136 reg = <0x0 0xff96c000 0x0 0x4000>; 1137 clocks = <&cru PCLK_LVDS_PHY>; 1138 clock-names = "pclk_lvds"; 1139 pinctrl-names = "lcdc"; 1140 pinctrl-0 = <&lcdc_ctl>; 1141 power-domains = <&power RK3288_PD_VIO>; 1142 rockchip,grf = <&grf>; 1143 status = "disabled"; 1144 1145 ports { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 lvds_in: port@0 { 1150 reg = <0>; 1151 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 1155 lvds_in_vopb: endpoint@0 { 1156 reg = <0>; 1157 remote-endpoint = <&vopb_out_lvds>; 1158 }; 1159 lvds_in_vopl: endpoint@1 { 1160 reg = <1>; 1161 remote-endpoint = <&vopl_out_lvds>; 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 edp: dp@ff970000 { 1168 compatible = "rockchip,rk3288-dp"; 1169 reg = <0x0 0xff970000 0x0 0x4000>; 1170 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1172 clock-names = "dp", "pclk"; 1173 phys = <&edp_phy>; 1174 phy-names = "dp"; 1175 resets = <&cru SRST_EDP>; 1176 reset-names = "dp"; 1177 rockchip,grf = <&grf>; 1178 status = "disabled"; 1179 1180 ports { 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 edp_in: port@0 { 1184 reg = <0>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 edp_in_vopb: endpoint@0 { 1188 reg = <0>; 1189 remote-endpoint = <&vopb_out_edp>; 1190 }; 1191 edp_in_vopl: endpoint@1 { 1192 reg = <1>; 1193 remote-endpoint = <&vopl_out_edp>; 1194 }; 1195 }; 1196 }; 1197 }; 1198 1199 hdmi: hdmi@ff980000 { 1200 compatible = "rockchip,rk3288-dw-hdmi"; 1201 reg = <0x0 0xff980000 0x0 0x20000>; 1202 reg-io-width = <4>; 1203 #sound-dai-cells = <0>; 1204 rockchip,grf = <&grf>; 1205 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1207 clock-names = "iahb", "isfr", "cec"; 1208 power-domains = <&power RK3288_PD_VIO>; 1209 status = "disabled"; 1210 1211 ports { 1212 hdmi_in: port { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 hdmi_in_vopb: endpoint@0 { 1216 reg = <0>; 1217 remote-endpoint = <&vopb_out_hdmi>; 1218 }; 1219 hdmi_in_vopl: endpoint@1 { 1220 reg = <1>; 1221 remote-endpoint = <&vopl_out_hdmi>; 1222 }; 1223 }; 1224 }; 1225 }; 1226 1227 vpu_mmu: iommu@ff9a0800 { 1228 compatible = "rockchip,iommu"; 1229 reg = <0x0 0xff9a0800 0x0 0x100>; 1230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupt-names = "vpu_mmu"; 1232 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1233 clock-names = "aclk", "iface"; 1234 #iommu-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 hevc_mmu: iommu@ff9c0440 { 1239 compatible = "rockchip,iommu"; 1240 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1241 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1242 interrupt-names = "hevc_mmu"; 1243 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1244 clock-names = "aclk", "iface"; 1245 #iommu-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 1249 gpu: gpu@ffa30000 { 1250 compatible = "rockchip,rk3288-mali", "arm,mali-t760"; 1251 reg = <0x0 0xffa30000 0x0 0x10000>; 1252 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1255 interrupt-names = "job", "mmu", "gpu"; 1256 clocks = <&cru ACLK_GPU>; 1257 operating-points-v2 = <&gpu_opp_table>; 1258 power-domains = <&power RK3288_PD_GPU>; 1259 status = "disabled"; 1260 }; 1261 1262 gpu_opp_table: gpu-opp-table { 1263 compatible = "operating-points-v2"; 1264 1265 opp-100000000 { 1266 opp-hz = /bits/ 64 <100000000>; 1267 opp-microvolt = <950000>; 1268 }; 1269 opp-200000000 { 1270 opp-hz = /bits/ 64 <200000000>; 1271 opp-microvolt = <950000>; 1272 }; 1273 opp-300000000 { 1274 opp-hz = /bits/ 64 <300000000>; 1275 opp-microvolt = <1000000>; 1276 }; 1277 opp-400000000 { 1278 opp-hz = /bits/ 64 <400000000>; 1279 opp-microvolt = <1100000>; 1280 }; 1281 opp-500000000 { 1282 opp-hz = /bits/ 64 <500000000>; 1283 opp-microvolt = <1200000>; 1284 }; 1285 opp-600000000 { 1286 opp-hz = /bits/ 64 <600000000>; 1287 opp-microvolt = <1250000>; 1288 }; 1289 }; 1290 1291 qos_gpu_r: qos@ffaa0000 { 1292 compatible = "syscon"; 1293 reg = <0x0 0xffaa0000 0x0 0x20>; 1294 }; 1295 1296 qos_gpu_w: qos@ffaa0080 { 1297 compatible = "syscon"; 1298 reg = <0x0 0xffaa0080 0x0 0x20>; 1299 }; 1300 1301 qos_vio1_vop: qos@ffad0000 { 1302 compatible = "syscon"; 1303 reg = <0x0 0xffad0000 0x0 0x20>; 1304 }; 1305 1306 qos_vio1_isp_w0: qos@ffad0100 { 1307 compatible = "syscon"; 1308 reg = <0x0 0xffad0100 0x0 0x20>; 1309 }; 1310 1311 qos_vio1_isp_w1: qos@ffad0180 { 1312 compatible = "syscon"; 1313 reg = <0x0 0xffad0180 0x0 0x20>; 1314 }; 1315 1316 qos_vio0_vop: qos@ffad0400 { 1317 compatible = "syscon"; 1318 reg = <0x0 0xffad0400 0x0 0x20>; 1319 }; 1320 1321 qos_vio0_vip: qos@ffad0480 { 1322 compatible = "syscon"; 1323 reg = <0x0 0xffad0480 0x0 0x20>; 1324 }; 1325 1326 qos_vio0_iep: qos@ffad0500 { 1327 compatible = "syscon"; 1328 reg = <0x0 0xffad0500 0x0 0x20>; 1329 }; 1330 1331 qos_vio2_rga_r: qos@ffad0800 { 1332 compatible = "syscon"; 1333 reg = <0x0 0xffad0800 0x0 0x20>; 1334 }; 1335 1336 qos_vio2_rga_w: qos@ffad0880 { 1337 compatible = "syscon"; 1338 reg = <0x0 0xffad0880 0x0 0x20>; 1339 }; 1340 1341 qos_vio1_isp_r: qos@ffad0900 { 1342 compatible = "syscon"; 1343 reg = <0x0 0xffad0900 0x0 0x20>; 1344 }; 1345 1346 qos_video: qos@ffae0000 { 1347 compatible = "syscon"; 1348 reg = <0x0 0xffae0000 0x0 0x20>; 1349 }; 1350 1351 qos_hevc_r: qos@ffaf0000 { 1352 compatible = "syscon"; 1353 reg = <0x0 0xffaf0000 0x0 0x20>; 1354 }; 1355 1356 qos_hevc_w: qos@ffaf0080 { 1357 compatible = "syscon"; 1358 reg = <0x0 0xffaf0080 0x0 0x20>; 1359 }; 1360 1361 gic: interrupt-controller@ffc01000 { 1362 compatible = "arm,gic-400"; 1363 interrupt-controller; 1364 #interrupt-cells = <3>; 1365 #address-cells = <0>; 1366 1367 reg = <0x0 0xffc01000 0x0 0x1000>, 1368 <0x0 0xffc02000 0x0 0x2000>, 1369 <0x0 0xffc04000 0x0 0x2000>, 1370 <0x0 0xffc06000 0x0 0x2000>; 1371 interrupts = <GIC_PPI 9 0xf04>; 1372 }; 1373 1374 efuse: efuse@ffb40000 { 1375 compatible = "rockchip,rk3288-efuse"; 1376 reg = <0x0 0xffb40000 0x0 0x20>; 1377 #address-cells = <1>; 1378 #size-cells = <1>; 1379 clocks = <&cru PCLK_EFUSE256>; 1380 clock-names = "pclk_efuse"; 1381 1382 cpu_leakage: cpu_leakage@17 { 1383 reg = <0x17 0x1>; 1384 }; 1385 }; 1386 1387 pinctrl: pinctrl { 1388 compatible = "rockchip,rk3288-pinctrl"; 1389 rockchip,grf = <&grf>; 1390 rockchip,pmu = <&pmu>; 1391 #address-cells = <2>; 1392 #size-cells = <2>; 1393 ranges; 1394 1395 gpio0: gpio0@ff750000 { 1396 compatible = "rockchip,gpio-bank"; 1397 reg = <0x0 0xff750000 0x0 0x100>; 1398 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&cru PCLK_GPIO0>; 1400 1401 gpio-controller; 1402 #gpio-cells = <2>; 1403 1404 interrupt-controller; 1405 #interrupt-cells = <2>; 1406 }; 1407 1408 gpio1: gpio1@ff780000 { 1409 compatible = "rockchip,gpio-bank"; 1410 reg = <0x0 0xff780000 0x0 0x100>; 1411 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1412 clocks = <&cru PCLK_GPIO1>; 1413 1414 gpio-controller; 1415 #gpio-cells = <2>; 1416 1417 interrupt-controller; 1418 #interrupt-cells = <2>; 1419 }; 1420 1421 gpio2: gpio2@ff790000 { 1422 compatible = "rockchip,gpio-bank"; 1423 reg = <0x0 0xff790000 0x0 0x100>; 1424 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&cru PCLK_GPIO2>; 1426 1427 gpio-controller; 1428 #gpio-cells = <2>; 1429 1430 interrupt-controller; 1431 #interrupt-cells = <2>; 1432 }; 1433 1434 gpio3: gpio3@ff7a0000 { 1435 compatible = "rockchip,gpio-bank"; 1436 reg = <0x0 0xff7a0000 0x0 0x100>; 1437 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1438 clocks = <&cru PCLK_GPIO3>; 1439 1440 gpio-controller; 1441 #gpio-cells = <2>; 1442 1443 interrupt-controller; 1444 #interrupt-cells = <2>; 1445 }; 1446 1447 gpio4: gpio4@ff7b0000 { 1448 compatible = "rockchip,gpio-bank"; 1449 reg = <0x0 0xff7b0000 0x0 0x100>; 1450 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1451 clocks = <&cru PCLK_GPIO4>; 1452 1453 gpio-controller; 1454 #gpio-cells = <2>; 1455 1456 interrupt-controller; 1457 #interrupt-cells = <2>; 1458 }; 1459 1460 gpio5: gpio5@ff7c0000 { 1461 compatible = "rockchip,gpio-bank"; 1462 reg = <0x0 0xff7c0000 0x0 0x100>; 1463 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1464 clocks = <&cru PCLK_GPIO5>; 1465 1466 gpio-controller; 1467 #gpio-cells = <2>; 1468 1469 interrupt-controller; 1470 #interrupt-cells = <2>; 1471 }; 1472 1473 gpio6: gpio6@ff7d0000 { 1474 compatible = "rockchip,gpio-bank"; 1475 reg = <0x0 0xff7d0000 0x0 0x100>; 1476 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&cru PCLK_GPIO6>; 1478 1479 gpio-controller; 1480 #gpio-cells = <2>; 1481 1482 interrupt-controller; 1483 #interrupt-cells = <2>; 1484 }; 1485 1486 gpio7: gpio7@ff7e0000 { 1487 compatible = "rockchip,gpio-bank"; 1488 reg = <0x0 0xff7e0000 0x0 0x100>; 1489 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1490 clocks = <&cru PCLK_GPIO7>; 1491 1492 gpio-controller; 1493 #gpio-cells = <2>; 1494 1495 interrupt-controller; 1496 #interrupt-cells = <2>; 1497 }; 1498 1499 gpio8: gpio8@ff7f0000 { 1500 compatible = "rockchip,gpio-bank"; 1501 reg = <0x0 0xff7f0000 0x0 0x100>; 1502 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1503 clocks = <&cru PCLK_GPIO8>; 1504 1505 gpio-controller; 1506 #gpio-cells = <2>; 1507 1508 interrupt-controller; 1509 #interrupt-cells = <2>; 1510 }; 1511 1512 hdmi { 1513 hdmi_cec_c0: hdmi-cec-c0 { 1514 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1515 }; 1516 1517 hdmi_cec_c7: hdmi-cec-c7 { 1518 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>; 1519 }; 1520 1521 hdmi_ddc: hdmi-ddc { 1522 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, 1523 <7 20 RK_FUNC_2 &pcfg_pull_none>; 1524 }; 1525 }; 1526 1527 pcfg_pull_up: pcfg-pull-up { 1528 bias-pull-up; 1529 }; 1530 1531 pcfg_pull_down: pcfg-pull-down { 1532 bias-pull-down; 1533 }; 1534 1535 pcfg_pull_none: pcfg-pull-none { 1536 bias-disable; 1537 }; 1538 1539 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1540 bias-disable; 1541 drive-strength = <12>; 1542 }; 1543 1544 sleep { 1545 global_pwroff: global-pwroff { 1546 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1547 }; 1548 1549 ddrio_pwroff: ddrio-pwroff { 1550 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1551 }; 1552 1553 ddr0_retention: ddr0-retention { 1554 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1555 }; 1556 1557 ddr1_retention: ddr1-retention { 1558 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1559 }; 1560 }; 1561 1562 edp { 1563 edp_hpd: edp-hpd { 1564 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; 1565 }; 1566 }; 1567 1568 i2c0 { 1569 i2c0_xfer: i2c0-xfer { 1570 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1571 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1572 }; 1573 }; 1574 1575 i2c1 { 1576 i2c1_xfer: i2c1-xfer { 1577 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1578 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1579 }; 1580 }; 1581 1582 i2c2 { 1583 i2c2_xfer: i2c2-xfer { 1584 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1585 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1586 }; 1587 }; 1588 1589 i2c3 { 1590 i2c3_xfer: i2c3-xfer { 1591 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1592 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1593 }; 1594 }; 1595 1596 i2c4 { 1597 i2c4_xfer: i2c4-xfer { 1598 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1599 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1600 }; 1601 }; 1602 1603 i2c5 { 1604 i2c5_xfer: i2c5-xfer { 1605 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1606 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1607 }; 1608 }; 1609 1610 i2s0 { 1611 i2s0_bus: i2s0-bus { 1612 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1613 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1614 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1615 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1616 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1617 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1618 }; 1619 }; 1620 1621 lcdc { 1622 lcdc_ctl: lcdc-ctl { 1623 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1624 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1625 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1626 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1627 }; 1628 }; 1629 1630 sdmmc { 1631 sdmmc_clk: sdmmc-clk { 1632 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1633 }; 1634 1635 sdmmc_cmd: sdmmc-cmd { 1636 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1637 }; 1638 1639 sdmmc_cd: sdmmc-cd { 1640 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1641 }; 1642 1643 sdmmc_bus1: sdmmc-bus1 { 1644 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1645 }; 1646 1647 sdmmc_bus4: sdmmc-bus4 { 1648 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1649 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1650 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1651 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1652 }; 1653 }; 1654 1655 sdio0 { 1656 sdio0_bus1: sdio0-bus1 { 1657 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1658 }; 1659 1660 sdio0_bus4: sdio0-bus4 { 1661 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1662 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1663 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1664 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1665 }; 1666 1667 sdio0_cmd: sdio0-cmd { 1668 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1669 }; 1670 1671 sdio0_clk: sdio0-clk { 1672 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1673 }; 1674 1675 sdio0_cd: sdio0-cd { 1676 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1677 }; 1678 1679 sdio0_wp: sdio0-wp { 1680 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1681 }; 1682 1683 sdio0_pwr: sdio0-pwr { 1684 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1685 }; 1686 1687 sdio0_bkpwr: sdio0-bkpwr { 1688 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1689 }; 1690 1691 sdio0_int: sdio0-int { 1692 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1693 }; 1694 }; 1695 1696 sdio1 { 1697 sdio1_bus1: sdio1-bus1 { 1698 rockchip,pins = <3 24 4 &pcfg_pull_up>; 1699 }; 1700 1701 sdio1_bus4: sdio1-bus4 { 1702 rockchip,pins = <3 24 4 &pcfg_pull_up>, 1703 <3 25 4 &pcfg_pull_up>, 1704 <3 26 4 &pcfg_pull_up>, 1705 <3 27 4 &pcfg_pull_up>; 1706 }; 1707 1708 sdio1_cd: sdio1-cd { 1709 rockchip,pins = <3 28 4 &pcfg_pull_up>; 1710 }; 1711 1712 sdio1_wp: sdio1-wp { 1713 rockchip,pins = <3 29 4 &pcfg_pull_up>; 1714 }; 1715 1716 sdio1_bkpwr: sdio1-bkpwr { 1717 rockchip,pins = <3 30 4 &pcfg_pull_up>; 1718 }; 1719 1720 sdio1_int: sdio1-int { 1721 rockchip,pins = <3 31 4 &pcfg_pull_up>; 1722 }; 1723 1724 sdio1_cmd: sdio1-cmd { 1725 rockchip,pins = <4 6 4 &pcfg_pull_up>; 1726 }; 1727 1728 sdio1_clk: sdio1-clk { 1729 rockchip,pins = <4 7 4 &pcfg_pull_none>; 1730 }; 1731 1732 sdio1_pwr: sdio1-pwr { 1733 rockchip,pins = <4 9 4 &pcfg_pull_up>; 1734 }; 1735 }; 1736 1737 emmc { 1738 emmc_clk: emmc-clk { 1739 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1740 }; 1741 1742 emmc_cmd: emmc-cmd { 1743 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1744 }; 1745 1746 emmc_pwr: emmc-pwr { 1747 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1748 }; 1749 1750 emmc_bus1: emmc-bus1 { 1751 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1752 }; 1753 1754 emmc_bus4: emmc-bus4 { 1755 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1756 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1757 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1758 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1759 }; 1760 1761 emmc_bus8: emmc-bus8 { 1762 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1763 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1764 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1765 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1766 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1767 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1768 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1769 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1770 }; 1771 }; 1772 1773 spi0 { 1774 spi0_clk: spi0-clk { 1775 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1776 }; 1777 spi0_cs0: spi0-cs0 { 1778 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1779 }; 1780 spi0_tx: spi0-tx { 1781 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1782 }; 1783 spi0_rx: spi0-rx { 1784 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1785 }; 1786 spi0_cs1: spi0-cs1 { 1787 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1788 }; 1789 }; 1790 spi1 { 1791 spi1_clk: spi1-clk { 1792 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1793 }; 1794 spi1_cs0: spi1-cs0 { 1795 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1796 }; 1797 spi1_rx: spi1-rx { 1798 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1799 }; 1800 spi1_tx: spi1-tx { 1801 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1802 }; 1803 }; 1804 1805 spi2 { 1806 spi2_cs1: spi2-cs1 { 1807 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1808 }; 1809 spi2_clk: spi2-clk { 1810 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1811 }; 1812 spi2_cs0: spi2-cs0 { 1813 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1814 }; 1815 spi2_rx: spi2-rx { 1816 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1817 }; 1818 spi2_tx: spi2-tx { 1819 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1820 }; 1821 }; 1822 1823 uart0 { 1824 uart0_xfer: uart0-xfer { 1825 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1826 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1827 }; 1828 1829 uart0_cts: uart0-cts { 1830 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; 1831 }; 1832 1833 uart0_rts: uart0-rts { 1834 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1835 }; 1836 }; 1837 1838 uart1 { 1839 uart1_xfer: uart1-xfer { 1840 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1841 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1842 }; 1843 1844 uart1_cts: uart1-cts { 1845 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; 1846 }; 1847 1848 uart1_rts: uart1-rts { 1849 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1850 }; 1851 }; 1852 1853 uart2 { 1854 uart2_xfer: uart2-xfer { 1855 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1856 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1857 }; 1858 /* no rts / cts for uart2 */ 1859 }; 1860 1861 uart3 { 1862 uart3_xfer: uart3-xfer { 1863 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1864 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1865 }; 1866 1867 uart3_cts: uart3-cts { 1868 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; 1869 }; 1870 1871 uart3_rts: uart3-rts { 1872 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1873 }; 1874 }; 1875 1876 uart4 { 1877 uart4_xfer: uart4-xfer { 1878 rockchip,pins = <5 15 3 &pcfg_pull_up>, 1879 <5 14 3 &pcfg_pull_none>; 1880 }; 1881 1882 uart4_cts: uart4-cts { 1883 rockchip,pins = <5 12 3 &pcfg_pull_up>; 1884 }; 1885 1886 uart4_rts: uart4-rts { 1887 rockchip,pins = <5 13 3 &pcfg_pull_none>; 1888 }; 1889 }; 1890 1891 tsadc { 1892 otp_gpio: otp-gpio { 1893 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; 1894 }; 1895 1896 otp_out: otp-out { 1897 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1898 }; 1899 }; 1900 1901 pwm0 { 1902 pwm0_pin: pwm0-pin { 1903 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1904 }; 1905 }; 1906 1907 pwm1 { 1908 pwm1_pin: pwm1-pin { 1909 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1910 }; 1911 }; 1912 1913 pwm2 { 1914 pwm2_pin: pwm2-pin { 1915 rockchip,pins = <7 22 3 &pcfg_pull_none>; 1916 }; 1917 }; 1918 1919 pwm3 { 1920 pwm3_pin: pwm3-pin { 1921 rockchip,pins = <7 23 3 &pcfg_pull_none>; 1922 }; 1923 }; 1924 1925 gmac { 1926 rgmii_pins: rgmii-pins { 1927 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1928 <3 31 3 &pcfg_pull_none>, 1929 <3 26 3 &pcfg_pull_none>, 1930 <3 27 3 &pcfg_pull_none>, 1931 <3 28 3 &pcfg_pull_none_12ma>, 1932 <3 29 3 &pcfg_pull_none_12ma>, 1933 <3 24 3 &pcfg_pull_none_12ma>, 1934 <3 25 3 &pcfg_pull_none_12ma>, 1935 <4 0 3 &pcfg_pull_none>, 1936 <4 5 3 &pcfg_pull_none>, 1937 <4 6 3 &pcfg_pull_none>, 1938 <4 9 3 &pcfg_pull_none_12ma>, 1939 <4 4 3 &pcfg_pull_none_12ma>, 1940 <4 1 3 &pcfg_pull_none>, 1941 <4 3 3 &pcfg_pull_none>; 1942 }; 1943 1944 rmii_pins: rmii-pins { 1945 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1946 <3 31 3 &pcfg_pull_none>, 1947 <3 28 3 &pcfg_pull_none>, 1948 <3 29 3 &pcfg_pull_none>, 1949 <4 0 3 &pcfg_pull_none>, 1950 <4 5 3 &pcfg_pull_none>, 1951 <4 4 3 &pcfg_pull_none>, 1952 <4 1 3 &pcfg_pull_none>, 1953 <4 2 3 &pcfg_pull_none>, 1954 <4 3 3 &pcfg_pull_none>; 1955 }; 1956 }; 1957 1958 spdif { 1959 spdif_tx: spdif-tx { 1960 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1961 }; 1962 }; 1963 }; 1964}; 1965