1/* 2 * Copyright 2012 Stefan Roese 3 * Stefan Roese <sr@denx.de> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This library is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/thermal/thermal.h> 45#include <dt-bindings/dma/sun4i-a10.h> 46#include <dt-bindings/clock/sun4i-a10-ccu.h> 47#include <dt-bindings/reset/sun4i-a10-ccu.h> 48 49/ { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 interrupt-parent = <&intc>; 53 54 aliases { 55 ethernet0 = &emac; 56 }; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 framebuffer-lcd0-hdmi { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "de_be0-lcd0-hdmi"; 67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, 68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; 70 status = "disabled"; 71 }; 72 73 framebuffer-fe0-lcd0-hdmi { 74 compatible = "allwinner,simple-framebuffer", 75 "simple-framebuffer"; 76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; 77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, 78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, 79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, 80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, 81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; 82 status = "disabled"; 83 }; 84 85 framebuffer-fe0-lcd0 { 86 compatible = "allwinner,simple-framebuffer", 87 "simple-framebuffer"; 88 allwinner,pipeline = "de_fe0-de_be0-lcd0"; 89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, 90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, 91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, 92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; 93 status = "disabled"; 94 }; 95 96 framebuffer-fe0-lcd0-tve0 { 97 compatible = "allwinner,simple-framebuffer", 98 "simple-framebuffer"; 99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; 100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, 101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, 102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, 103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, 104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; 105 status = "disabled"; 106 }; 107 }; 108 109 cpus { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 cpu0: cpu@0 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a8"; 115 reg = <0x0>; 116 clocks = <&ccu CLK_CPU>; 117 clock-latency = <244144>; /* 8 32k periods */ 118 operating-points = < 119 /* kHz uV */ 120 1008000 1400000 121 912000 1350000 122 864000 1300000 123 624000 1250000 124 >; 125 #cooling-cells = <2>; 126 }; 127 }; 128 129 thermal-zones { 130 cpu-thermal { 131 /* milliseconds */ 132 polling-delay-passive = <250>; 133 polling-delay = <1000>; 134 thermal-sensors = <&rtp>; 135 136 cooling-maps { 137 map0 { 138 trip = <&cpu_alert0>; 139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 140 }; 141 }; 142 143 trips { 144 cpu_alert0: cpu-alert0 { 145 /* milliCelsius */ 146 temperature = <850000>; 147 hysteresis = <2000>; 148 type = "passive"; 149 }; 150 151 cpu_crit: cpu-crit { 152 /* milliCelsius */ 153 temperature = <100000>; 154 hysteresis = <2000>; 155 type = "critical"; 156 }; 157 }; 158 }; 159 }; 160 161 clocks { 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges; 165 166 osc24M: clk-24M { 167 #clock-cells = <0>; 168 compatible = "fixed-clock"; 169 clock-frequency = <24000000>; 170 clock-output-names = "osc24M"; 171 }; 172 173 osc32k: clk-32k { 174 #clock-cells = <0>; 175 compatible = "fixed-clock"; 176 clock-frequency = <32768>; 177 clock-output-names = "osc32k"; 178 }; 179 }; 180 181 de: display-engine { 182 compatible = "allwinner,sun4i-a10-display-engine"; 183 allwinner,pipelines = <&fe0>, <&fe1>; 184 status = "disabled"; 185 }; 186 187 soc { 188 compatible = "simple-bus"; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges; 192 193 system-control@1c00000 { 194 compatible = "allwinner,sun4i-a10-system-control"; 195 reg = <0x01c00000 0x30>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges; 199 200 sram_a: sram@0 { 201 compatible = "mmio-sram"; 202 reg = <0x00000000 0xc000>; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges = <0 0x00000000 0xc000>; 206 207 emac_sram: sram-section@8000 { 208 compatible = "allwinner,sun4i-a10-sram-a3-a4"; 209 reg = <0x8000 0x4000>; 210 status = "disabled"; 211 }; 212 }; 213 214 sram_d: sram@10000 { 215 compatible = "mmio-sram"; 216 reg = <0x00010000 0x1000>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 ranges = <0 0x00010000 0x1000>; 220 221 otg_sram: sram-section@0 { 222 compatible = "allwinner,sun4i-a10-sram-d"; 223 reg = <0x0000 0x1000>; 224 status = "disabled"; 225 }; 226 }; 227 }; 228 229 dma: dma-controller@1c02000 { 230 compatible = "allwinner,sun4i-a10-dma"; 231 reg = <0x01c02000 0x1000>; 232 interrupts = <27>; 233 clocks = <&ccu CLK_AHB_DMA>; 234 #dma-cells = <2>; 235 }; 236 237 nfc: nand@1c03000 { 238 compatible = "allwinner,sun4i-a10-nand"; 239 reg = <0x01c03000 0x1000>; 240 interrupts = <37>; 241 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; 242 clock-names = "ahb", "mod"; 243 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 244 dma-names = "rxtx"; 245 status = "disabled"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 }; 249 250 spi0: spi@1c05000 { 251 compatible = "allwinner,sun4i-a10-spi"; 252 reg = <0x01c05000 0x1000>; 253 interrupts = <10>; 254 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; 255 clock-names = "ahb", "mod"; 256 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 257 <&dma SUN4I_DMA_DEDICATED 26>; 258 dma-names = "rx", "tx"; 259 status = "disabled"; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 }; 263 264 spi1: spi@1c06000 { 265 compatible = "allwinner,sun4i-a10-spi"; 266 reg = <0x01c06000 0x1000>; 267 interrupts = <11>; 268 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; 269 clock-names = "ahb", "mod"; 270 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 271 <&dma SUN4I_DMA_DEDICATED 8>; 272 dma-names = "rx", "tx"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; 275 status = "disabled"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 }; 279 280 emac: ethernet@1c0b000 { 281 compatible = "allwinner,sun4i-a10-emac"; 282 reg = <0x01c0b000 0x1000>; 283 interrupts = <55>; 284 clocks = <&ccu CLK_AHB_EMAC>; 285 allwinner,sram = <&emac_sram 1>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&emac_pins>; 288 status = "disabled"; 289 }; 290 291 mdio: mdio@1c0b080 { 292 compatible = "allwinner,sun4i-a10-mdio"; 293 reg = <0x01c0b080 0x14>; 294 status = "disabled"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 }; 298 299 tcon0: lcd-controller@1c0c000 { 300 compatible = "allwinner,sun4i-a10-tcon"; 301 reg = <0x01c0c000 0x1000>; 302 interrupts = <44>; 303 resets = <&ccu RST_TCON0>; 304 reset-names = "lcd"; 305 clocks = <&ccu CLK_AHB_LCD0>, 306 <&ccu CLK_TCON0_CH0>, 307 <&ccu CLK_TCON0_CH1>; 308 clock-names = "ahb", 309 "tcon-ch0", 310 "tcon-ch1"; 311 clock-output-names = "tcon0-pixel-clock"; 312 dmas = <&dma SUN4I_DMA_DEDICATED 14>; 313 314 ports { 315 #address-cells = <1>; 316 #size-cells = <0>; 317 318 tcon0_in: port@0 { 319 #address-cells = <1>; 320 #size-cells = <0>; 321 reg = <0>; 322 323 tcon0_in_be0: endpoint@0 { 324 reg = <0>; 325 remote-endpoint = <&be0_out_tcon0>; 326 }; 327 328 tcon0_in_be1: endpoint@1 { 329 reg = <1>; 330 remote-endpoint = <&be1_out_tcon0>; 331 }; 332 }; 333 334 tcon0_out: port@1 { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <1>; 338 339 tcon0_out_hdmi: endpoint@1 { 340 reg = <1>; 341 remote-endpoint = <&hdmi_in_tcon0>; 342 allwinner,tcon-channel = <1>; 343 }; 344 }; 345 }; 346 }; 347 348 tcon1: lcd-controller@1c0d000 { 349 compatible = "allwinner,sun4i-a10-tcon"; 350 reg = <0x01c0d000 0x1000>; 351 interrupts = <45>; 352 resets = <&ccu RST_TCON1>; 353 reset-names = "lcd"; 354 clocks = <&ccu CLK_AHB_LCD1>, 355 <&ccu CLK_TCON1_CH0>, 356 <&ccu CLK_TCON1_CH1>; 357 clock-names = "ahb", 358 "tcon-ch0", 359 "tcon-ch1"; 360 clock-output-names = "tcon1-pixel-clock"; 361 dmas = <&dma SUN4I_DMA_DEDICATED 15>; 362 363 ports { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 367 tcon1_in: port@0 { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <0>; 371 372 tcon1_in_be0: endpoint@0 { 373 reg = <0>; 374 remote-endpoint = <&be0_out_tcon1>; 375 }; 376 377 tcon1_in_be1: endpoint@1 { 378 reg = <1>; 379 remote-endpoint = <&be1_out_tcon1>; 380 }; 381 }; 382 383 tcon1_out: port@1 { 384 #address-cells = <1>; 385 #size-cells = <0>; 386 reg = <1>; 387 388 tcon1_out_hdmi: endpoint@1 { 389 reg = <1>; 390 remote-endpoint = <&hdmi_in_tcon1>; 391 allwinner,tcon-channel = <1>; 392 }; 393 }; 394 }; 395 }; 396 397 mmc0: mmc@1c0f000 { 398 compatible = "allwinner,sun4i-a10-mmc"; 399 reg = <0x01c0f000 0x1000>; 400 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; 401 clock-names = "ahb", "mmc"; 402 interrupts = <32>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&mmc0_pins>; 405 status = "disabled"; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 }; 409 410 mmc1: mmc@1c10000 { 411 compatible = "allwinner,sun4i-a10-mmc"; 412 reg = <0x01c10000 0x1000>; 413 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; 414 clock-names = "ahb", "mmc"; 415 interrupts = <33>; 416 status = "disabled"; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 }; 420 421 mmc2: mmc@1c11000 { 422 compatible = "allwinner,sun4i-a10-mmc"; 423 reg = <0x01c11000 0x1000>; 424 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; 425 clock-names = "ahb", "mmc"; 426 interrupts = <34>; 427 status = "disabled"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 }; 431 432 mmc3: mmc@1c12000 { 433 compatible = "allwinner,sun4i-a10-mmc"; 434 reg = <0x01c12000 0x1000>; 435 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; 436 clock-names = "ahb", "mmc"; 437 interrupts = <35>; 438 status = "disabled"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 }; 442 443 usb_otg: usb@1c13000 { 444 compatible = "allwinner,sun4i-a10-musb"; 445 reg = <0x01c13000 0x0400>; 446 clocks = <&ccu CLK_AHB_OTG>; 447 interrupts = <38>; 448 interrupt-names = "mc"; 449 phys = <&usbphy 0>; 450 phy-names = "usb"; 451 extcon = <&usbphy 0>; 452 allwinner,sram = <&otg_sram 1>; 453 status = "disabled"; 454 }; 455 456 usbphy: phy@1c13400 { 457 #phy-cells = <1>; 458 compatible = "allwinner,sun4i-a10-usb-phy"; 459 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 460 reg-names = "phy_ctrl", "pmu1", "pmu2"; 461 clocks = <&ccu CLK_USB_PHY>; 462 clock-names = "usb_phy"; 463 resets = <&ccu RST_USB_PHY0>, 464 <&ccu RST_USB_PHY1>, 465 <&ccu RST_USB_PHY2>; 466 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 467 status = "disabled"; 468 }; 469 470 ehci0: usb@1c14000 { 471 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 472 reg = <0x01c14000 0x100>; 473 interrupts = <39>; 474 clocks = <&ccu CLK_AHB_EHCI0>; 475 phys = <&usbphy 1>; 476 phy-names = "usb"; 477 status = "disabled"; 478 }; 479 480 ohci0: usb@1c14400 { 481 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 482 reg = <0x01c14400 0x100>; 483 interrupts = <64>; 484 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; 485 phys = <&usbphy 1>; 486 phy-names = "usb"; 487 status = "disabled"; 488 }; 489 490 crypto: crypto-engine@1c15000 { 491 compatible = "allwinner,sun4i-a10-crypto"; 492 reg = <0x01c15000 0x1000>; 493 interrupts = <86>; 494 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; 495 clock-names = "ahb", "mod"; 496 }; 497 498 hdmi: hdmi@1c16000 { 499 compatible = "allwinner,sun4i-a10-hdmi"; 500 reg = <0x01c16000 0x1000>; 501 interrupts = <58>; 502 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, 503 <&ccu CLK_PLL_VIDEO0_2X>, 504 <&ccu CLK_PLL_VIDEO1_2X>; 505 clock-names = "ahb", "mod", "pll-0", "pll-1"; 506 dmas = <&dma SUN4I_DMA_NORMAL 16>, 507 <&dma SUN4I_DMA_NORMAL 16>, 508 <&dma SUN4I_DMA_DEDICATED 24>; 509 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 510 status = "disabled"; 511 512 ports { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 516 hdmi_in: port@0 { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 reg = <0>; 520 521 hdmi_in_tcon0: endpoint@0 { 522 reg = <0>; 523 remote-endpoint = <&tcon0_out_hdmi>; 524 }; 525 526 hdmi_in_tcon1: endpoint@1 { 527 reg = <1>; 528 remote-endpoint = <&tcon1_out_hdmi>; 529 }; 530 }; 531 532 hdmi_out: port@1 { 533 reg = <1>; 534 }; 535 }; 536 }; 537 538 spi2: spi@1c17000 { 539 compatible = "allwinner,sun4i-a10-spi"; 540 reg = <0x01c17000 0x1000>; 541 interrupts = <12>; 542 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; 543 clock-names = "ahb", "mod"; 544 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 545 <&dma SUN4I_DMA_DEDICATED 28>; 546 dma-names = "rx", "tx"; 547 status = "disabled"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 }; 551 552 ahci: sata@1c18000 { 553 compatible = "allwinner,sun4i-a10-ahci"; 554 reg = <0x01c18000 0x1000>; 555 interrupts = <56>; 556 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; 557 status = "disabled"; 558 }; 559 560 ehci1: usb@1c1c000 { 561 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 562 reg = <0x01c1c000 0x100>; 563 interrupts = <40>; 564 clocks = <&ccu CLK_AHB_EHCI1>; 565 phys = <&usbphy 2>; 566 phy-names = "usb"; 567 status = "disabled"; 568 }; 569 570 ohci1: usb@1c1c400 { 571 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 572 reg = <0x01c1c400 0x100>; 573 interrupts = <65>; 574 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; 575 phys = <&usbphy 2>; 576 phy-names = "usb"; 577 status = "disabled"; 578 }; 579 580 spi3: spi@1c1f000 { 581 compatible = "allwinner,sun4i-a10-spi"; 582 reg = <0x01c1f000 0x1000>; 583 interrupts = <50>; 584 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; 585 clock-names = "ahb", "mod"; 586 dmas = <&dma SUN4I_DMA_DEDICATED 31>, 587 <&dma SUN4I_DMA_DEDICATED 30>; 588 dma-names = "rx", "tx"; 589 status = "disabled"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 }; 593 594 ccu: clock@1c20000 { 595 compatible = "allwinner,sun4i-a10-ccu"; 596 reg = <0x01c20000 0x400>; 597 clocks = <&osc24M>, <&osc32k>; 598 clock-names = "hosc", "losc"; 599 #clock-cells = <1>; 600 #reset-cells = <1>; 601 }; 602 603 intc: interrupt-controller@1c20400 { 604 compatible = "allwinner,sun4i-a10-ic"; 605 reg = <0x01c20400 0x400>; 606 interrupt-controller; 607 #interrupt-cells = <1>; 608 }; 609 610 pio: pinctrl@1c20800 { 611 compatible = "allwinner,sun4i-a10-pinctrl"; 612 reg = <0x01c20800 0x400>; 613 interrupts = <28>; 614 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 615 clock-names = "apb", "hosc", "losc"; 616 gpio-controller; 617 interrupt-controller; 618 #interrupt-cells = <3>; 619 #gpio-cells = <3>; 620 621 can0_ph_pins: can0-ph-pins { 622 pins = "PH20", "PH21"; 623 function = "can"; 624 }; 625 626 emac_pins: emac0-pins { 627 pins = "PA0", "PA1", "PA2", 628 "PA3", "PA4", "PA5", "PA6", 629 "PA7", "PA8", "PA9", "PA10", 630 "PA11", "PA12", "PA13", "PA14", 631 "PA15", "PA16"; 632 function = "emac"; 633 }; 634 635 i2c0_pins: i2c0-pins { 636 pins = "PB0", "PB1"; 637 function = "i2c0"; 638 }; 639 640 i2c1_pins: i2c1-pins { 641 pins = "PB18", "PB19"; 642 function = "i2c1"; 643 }; 644 645 i2c2_pins: i2c2-pins { 646 pins = "PB20", "PB21"; 647 function = "i2c2"; 648 }; 649 650 ir0_rx_pins: ir0-rx-pin { 651 pins = "PB4"; 652 function = "ir0"; 653 }; 654 655 ir0_tx_pins: ir0-tx-pin { 656 pins = "PB3"; 657 function = "ir0"; 658 }; 659 660 ir1_rx_pins: ir1-rx-pin { 661 pins = "PB23"; 662 function = "ir1"; 663 }; 664 665 ir1_tx_pins: ir1-tx-pin { 666 pins = "PB22"; 667 function = "ir1"; 668 }; 669 670 mmc0_pins: mmc0-pins { 671 pins = "PF0", "PF1", "PF2", 672 "PF3", "PF4", "PF5"; 673 function = "mmc0"; 674 drive-strength = <30>; 675 bias-pull-up; 676 }; 677 678 ps2_ch0_pins: ps2-ch0-pins { 679 pins = "PI20", "PI21"; 680 function = "ps2"; 681 }; 682 683 ps2_ch1_ph_pins: ps2-ch1-ph-pins { 684 pins = "PH12", "PH13"; 685 function = "ps2"; 686 }; 687 688 pwm0_pin: pwm0-pin { 689 pins = "PB2"; 690 function = "pwm"; 691 }; 692 693 pwm1_pin: pwm1-pin { 694 pins = "PI3"; 695 function = "pwm"; 696 }; 697 698 spdif_tx_pin: spdif-tx-pin { 699 pins = "PB13"; 700 function = "spdif"; 701 bias-pull-up; 702 }; 703 704 spi0_pi_pins: spi0-pi-pins { 705 pins = "PI11", "PI12", "PI13"; 706 function = "spi0"; 707 }; 708 709 spi0_cs0_pi_pin: spi0-cs0-pi-pin { 710 pins = "PI10"; 711 function = "spi0"; 712 }; 713 714 spi1_pins: spi1-pins { 715 pins = "PI17", "PI18", "PI19"; 716 function = "spi1"; 717 }; 718 719 spi1_cs0_pin: spi1-cs0-pin { 720 pins = "PI16"; 721 function = "spi1"; 722 }; 723 724 spi2_pb_pins: spi2-pb-pins { 725 pins = "PB15", "PB16", "PB17"; 726 function = "spi2"; 727 }; 728 729 spi2_pc_pins: spi2-pc-pins { 730 pins = "PC20", "PC21", "PC22"; 731 function = "spi2"; 732 }; 733 734 spi2_cs0_pb_pin: spi2-cs0-pb-pin { 735 pins = "PB14"; 736 function = "spi2"; 737 }; 738 739 spi2_cs0_pc_pins: spi2-cs0-pc-pin { 740 pins = "PC19"; 741 function = "spi2"; 742 }; 743 744 uart0_pb_pins: uart0-pb-pins { 745 pins = "PB22", "PB23"; 746 function = "uart0"; 747 }; 748 749 uart0_pf_pins: uart0-pf-pins { 750 pins = "PF2", "PF4"; 751 function = "uart0"; 752 }; 753 754 uart1_pins: uart1-pins { 755 pins = "PA10", "PA11"; 756 function = "uart1"; 757 }; 758 }; 759 760 timer@1c20c00 { 761 compatible = "allwinner,sun4i-a10-timer"; 762 reg = <0x01c20c00 0x90>; 763 interrupts = <22>; 764 clocks = <&osc24M>; 765 }; 766 767 wdt: watchdog@1c20c90 { 768 compatible = "allwinner,sun4i-a10-wdt"; 769 reg = <0x01c20c90 0x10>; 770 }; 771 772 rtc: rtc@1c20d00 { 773 compatible = "allwinner,sun4i-a10-rtc"; 774 reg = <0x01c20d00 0x20>; 775 interrupts = <24>; 776 }; 777 778 pwm: pwm@1c20e00 { 779 compatible = "allwinner,sun4i-a10-pwm"; 780 reg = <0x01c20e00 0xc>; 781 clocks = <&osc24M>; 782 #pwm-cells = <3>; 783 status = "disabled"; 784 }; 785 786 spdif: spdif@1c21000 { 787 #sound-dai-cells = <0>; 788 compatible = "allwinner,sun4i-a10-spdif"; 789 reg = <0x01c21000 0x400>; 790 interrupts = <13>; 791 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; 792 clock-names = "apb", "spdif"; 793 dmas = <&dma SUN4I_DMA_NORMAL 2>, 794 <&dma SUN4I_DMA_NORMAL 2>; 795 dma-names = "rx", "tx"; 796 status = "disabled"; 797 }; 798 799 ir0: ir@1c21800 { 800 compatible = "allwinner,sun4i-a10-ir"; 801 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; 802 clock-names = "apb", "ir"; 803 interrupts = <5>; 804 reg = <0x01c21800 0x40>; 805 status = "disabled"; 806 }; 807 808 ir1: ir@1c21c00 { 809 compatible = "allwinner,sun4i-a10-ir"; 810 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; 811 clock-names = "apb", "ir"; 812 interrupts = <6>; 813 reg = <0x01c21c00 0x40>; 814 status = "disabled"; 815 }; 816 817 i2s0: i2s@1c22400 { 818 #sound-dai-cells = <0>; 819 compatible = "allwinner,sun4i-a10-i2s"; 820 reg = <0x01c22400 0x400>; 821 interrupts = <16>; 822 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; 823 clock-names = "apb", "mod"; 824 dmas = <&dma SUN4I_DMA_NORMAL 3>, 825 <&dma SUN4I_DMA_NORMAL 3>; 826 dma-names = "rx", "tx"; 827 status = "disabled"; 828 }; 829 830 lradc: lradc@1c22800 { 831 compatible = "allwinner,sun4i-a10-lradc-keys"; 832 reg = <0x01c22800 0x100>; 833 interrupts = <31>; 834 status = "disabled"; 835 }; 836 837 codec: codec@1c22c00 { 838 #sound-dai-cells = <0>; 839 compatible = "allwinner,sun4i-a10-codec"; 840 reg = <0x01c22c00 0x40>; 841 interrupts = <30>; 842 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; 843 clock-names = "apb", "codec"; 844 dmas = <&dma SUN4I_DMA_NORMAL 19>, 845 <&dma SUN4I_DMA_NORMAL 19>; 846 dma-names = "rx", "tx"; 847 status = "disabled"; 848 }; 849 850 sid: eeprom@1c23800 { 851 compatible = "allwinner,sun4i-a10-sid"; 852 reg = <0x01c23800 0x10>; 853 }; 854 855 rtp: rtp@1c25000 { 856 compatible = "allwinner,sun4i-a10-ts"; 857 reg = <0x01c25000 0x100>; 858 interrupts = <29>; 859 #thermal-sensor-cells = <0>; 860 }; 861 862 uart0: serial@1c28000 { 863 compatible = "snps,dw-apb-uart"; 864 reg = <0x01c28000 0x400>; 865 interrupts = <1>; 866 reg-shift = <2>; 867 reg-io-width = <4>; 868 clocks = <&ccu CLK_APB1_UART0>; 869 status = "disabled"; 870 }; 871 872 uart1: serial@1c28400 { 873 compatible = "snps,dw-apb-uart"; 874 reg = <0x01c28400 0x400>; 875 interrupts = <2>; 876 reg-shift = <2>; 877 reg-io-width = <4>; 878 clocks = <&ccu CLK_APB1_UART1>; 879 status = "disabled"; 880 }; 881 882 uart2: serial@1c28800 { 883 compatible = "snps,dw-apb-uart"; 884 reg = <0x01c28800 0x400>; 885 interrupts = <3>; 886 reg-shift = <2>; 887 reg-io-width = <4>; 888 clocks = <&ccu CLK_APB1_UART2>; 889 status = "disabled"; 890 }; 891 892 uart3: serial@1c28c00 { 893 compatible = "snps,dw-apb-uart"; 894 reg = <0x01c28c00 0x400>; 895 interrupts = <4>; 896 reg-shift = <2>; 897 reg-io-width = <4>; 898 clocks = <&ccu CLK_APB1_UART3>; 899 status = "disabled"; 900 }; 901 902 uart4: serial@1c29000 { 903 compatible = "snps,dw-apb-uart"; 904 reg = <0x01c29000 0x400>; 905 interrupts = <17>; 906 reg-shift = <2>; 907 reg-io-width = <4>; 908 clocks = <&ccu CLK_APB1_UART4>; 909 status = "disabled"; 910 }; 911 912 uart5: serial@1c29400 { 913 compatible = "snps,dw-apb-uart"; 914 reg = <0x01c29400 0x400>; 915 interrupts = <18>; 916 reg-shift = <2>; 917 reg-io-width = <4>; 918 clocks = <&ccu CLK_APB1_UART5>; 919 status = "disabled"; 920 }; 921 922 uart6: serial@1c29800 { 923 compatible = "snps,dw-apb-uart"; 924 reg = <0x01c29800 0x400>; 925 interrupts = <19>; 926 reg-shift = <2>; 927 reg-io-width = <4>; 928 clocks = <&ccu CLK_APB1_UART6>; 929 status = "disabled"; 930 }; 931 932 uart7: serial@1c29c00 { 933 compatible = "snps,dw-apb-uart"; 934 reg = <0x01c29c00 0x400>; 935 interrupts = <20>; 936 reg-shift = <2>; 937 reg-io-width = <4>; 938 clocks = <&ccu CLK_APB1_UART7>; 939 status = "disabled"; 940 }; 941 942 ps20: ps2@1c2a000 { 943 compatible = "allwinner,sun4i-a10-ps2"; 944 reg = <0x01c2a000 0x400>; 945 interrupts = <62>; 946 clocks = <&ccu CLK_APB1_PS20>; 947 status = "disabled"; 948 }; 949 950 ps21: ps2@1c2a400 { 951 compatible = "allwinner,sun4i-a10-ps2"; 952 reg = <0x01c2a400 0x400>; 953 interrupts = <63>; 954 clocks = <&ccu CLK_APB1_PS21>; 955 status = "disabled"; 956 }; 957 958 i2c0: i2c@1c2ac00 { 959 compatible = "allwinner,sun4i-a10-i2c"; 960 reg = <0x01c2ac00 0x400>; 961 interrupts = <7>; 962 clocks = <&ccu CLK_APB1_I2C0>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&i2c0_pins>; 965 status = "disabled"; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 }; 969 970 i2c1: i2c@1c2b000 { 971 compatible = "allwinner,sun4i-a10-i2c"; 972 reg = <0x01c2b000 0x400>; 973 interrupts = <8>; 974 clocks = <&ccu CLK_APB1_I2C1>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&i2c1_pins>; 977 status = "disabled"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 }; 981 982 i2c2: i2c@1c2b400 { 983 compatible = "allwinner,sun4i-a10-i2c"; 984 reg = <0x01c2b400 0x400>; 985 interrupts = <9>; 986 clocks = <&ccu CLK_APB1_I2C2>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&i2c2_pins>; 989 status = "disabled"; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 }; 993 994 can0: can@1c2bc00 { 995 compatible = "allwinner,sun4i-a10-can"; 996 reg = <0x01c2bc00 0x400>; 997 interrupts = <26>; 998 clocks = <&ccu CLK_APB1_CAN>; 999 status = "disabled"; 1000 }; 1001 1002 mali: gpu@1c40000 { 1003 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; 1004 reg = <0x01c40000 0x10000>; 1005 interrupts = <69>, 1006 <70>, 1007 <71>, 1008 <72>, 1009 <73>; 1010 interrupt-names = "gp", 1011 "gpmmu", 1012 "pp0", 1013 "ppmmu0", 1014 "pmu"; 1015 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; 1016 clock-names = "bus", "core"; 1017 resets = <&ccu RST_GPU>; 1018 1019 assigned-clocks = <&ccu CLK_GPU>; 1020 assigned-clock-rates = <384000000>; 1021 }; 1022 1023 fe0: display-frontend@1e00000 { 1024 compatible = "allwinner,sun4i-a10-display-frontend"; 1025 reg = <0x01e00000 0x20000>; 1026 interrupts = <47>; 1027 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, 1028 <&ccu CLK_DRAM_DE_FE0>; 1029 clock-names = "ahb", "mod", 1030 "ram"; 1031 resets = <&ccu RST_DE_FE0>; 1032 1033 ports { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 fe0_out: port@1 { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 reg = <1>; 1041 1042 fe0_out_be0: endpoint@0 { 1043 reg = <0>; 1044 remote-endpoint = <&be0_in_fe0>; 1045 }; 1046 1047 fe0_out_be1: endpoint@1 { 1048 reg = <1>; 1049 remote-endpoint = <&be1_in_fe0>; 1050 }; 1051 }; 1052 }; 1053 }; 1054 1055 fe1: display-frontend@1e20000 { 1056 compatible = "allwinner,sun4i-a10-display-frontend"; 1057 reg = <0x01e20000 0x20000>; 1058 interrupts = <48>; 1059 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, 1060 <&ccu CLK_DRAM_DE_FE1>; 1061 clock-names = "ahb", "mod", 1062 "ram"; 1063 resets = <&ccu RST_DE_FE1>; 1064 1065 ports { 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 1069 fe1_out: port@1 { 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 reg = <1>; 1073 1074 fe1_out_be0: endpoint@0 { 1075 reg = <0>; 1076 remote-endpoint = <&be0_in_fe1>; 1077 }; 1078 1079 fe1_out_be1: endpoint@1 { 1080 reg = <1>; 1081 remote-endpoint = <&be1_in_fe1>; 1082 }; 1083 }; 1084 }; 1085 }; 1086 1087 be1: display-backend@1e40000 { 1088 compatible = "allwinner,sun4i-a10-display-backend"; 1089 reg = <0x01e40000 0x10000>; 1090 interrupts = <48>; 1091 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, 1092 <&ccu CLK_DRAM_DE_BE1>; 1093 clock-names = "ahb", "mod", 1094 "ram"; 1095 resets = <&ccu RST_DE_BE1>; 1096 1097 ports { 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 be1_in: port@0 { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 reg = <0>; 1105 1106 be1_in_fe0: endpoint@0 { 1107 reg = <0>; 1108 remote-endpoint = <&fe0_out_be1>; 1109 }; 1110 1111 be1_in_fe1: endpoint@1 { 1112 reg = <1>; 1113 remote-endpoint = <&fe1_out_be1>; 1114 }; 1115 }; 1116 1117 be1_out: port@1 { 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 reg = <1>; 1121 1122 be1_out_tcon0: endpoint@0 { 1123 reg = <0>; 1124 remote-endpoint = <&tcon0_in_be1>; 1125 }; 1126 1127 be1_out_tcon1: endpoint@1 { 1128 reg = <1>; 1129 remote-endpoint = <&tcon1_in_be1>; 1130 }; 1131 }; 1132 }; 1133 }; 1134 1135 be0: display-backend@1e60000 { 1136 compatible = "allwinner,sun4i-a10-display-backend"; 1137 reg = <0x01e60000 0x10000>; 1138 interrupts = <47>; 1139 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 1140 <&ccu CLK_DRAM_DE_BE0>; 1141 clock-names = "ahb", "mod", 1142 "ram"; 1143 resets = <&ccu RST_DE_BE0>; 1144 1145 ports { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 be0_in: port@0 { 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 reg = <0>; 1153 1154 be0_in_fe0: endpoint@0 { 1155 reg = <0>; 1156 remote-endpoint = <&fe0_out_be0>; 1157 }; 1158 1159 be0_in_fe1: endpoint@1 { 1160 reg = <1>; 1161 remote-endpoint = <&fe1_out_be0>; 1162 }; 1163 }; 1164 1165 be0_out: port@1 { 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 reg = <1>; 1169 1170 be0_out_tcon0: endpoint@0 { 1171 reg = <0>; 1172 remote-endpoint = <&tcon0_in_be0>; 1173 }; 1174 1175 be0_out_tcon1: endpoint@1 { 1176 reg = <1>; 1177 remote-endpoint = <&tcon1_in_be0>; 1178 }; 1179 }; 1180 }; 1181 }; 1182 }; 1183}; 1184