1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/thermal/thermal.h> 49#include <dt-bindings/dma/sun4i-a10.h> 50#include <dt-bindings/clock/sun7i-a20-ccu.h> 51#include <dt-bindings/reset/sun4i-a10-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 56 aliases { 57 ethernet0 = &gmac; 58 }; 59 60 chosen { 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges; 64 65 framebuffer@0 { 66 compatible = "allwinner,simple-framebuffer", 67 "simple-framebuffer"; 68 allwinner,pipeline = "de_be0-lcd0-hdmi"; 69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, 70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, 72 <&ccu CLK_HDMI>; 73 status = "disabled"; 74 }; 75 76 framebuffer@1 { 77 compatible = "allwinner,simple-framebuffer", 78 "simple-framebuffer"; 79 allwinner,pipeline = "de_be0-lcd0"; 80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, 81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, 82 <&ccu CLK_DRAM_DE_BE0>; 83 status = "disabled"; 84 }; 85 86 framebuffer@2 { 87 compatible = "allwinner,simple-framebuffer", 88 "simple-framebuffer"; 89 allwinner,pipeline = "de_be0-lcd0-tve0"; 90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, 91 <&ccu CLK_AHB_DE_BE0>, 92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, 93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; 94 status = "disabled"; 95 }; 96 }; 97 98 cpus { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 cpu0: cpu@0 { 103 compatible = "arm,cortex-a7"; 104 device_type = "cpu"; 105 reg = <0>; 106 clocks = <&ccu CLK_CPU>; 107 clock-latency = <244144>; /* 8 32k periods */ 108 operating-points = < 109 /* kHz uV */ 110 960000 1400000 111 912000 1400000 112 864000 1300000 113 720000 1200000 114 528000 1100000 115 312000 1000000 116 144000 1000000 117 >; 118 #cooling-cells = <2>; 119 }; 120 121 cpu@1 { 122 compatible = "arm,cortex-a7"; 123 device_type = "cpu"; 124 reg = <1>; 125 clocks = <&ccu CLK_CPU>; 126 clock-latency = <244144>; /* 8 32k periods */ 127 operating-points = < 128 /* kHz uV */ 129 960000 1400000 130 912000 1400000 131 864000 1300000 132 720000 1200000 133 528000 1100000 134 312000 1000000 135 144000 1000000 136 >; 137 #cooling-cells = <2>; 138 }; 139 }; 140 141 thermal-zones { 142 cpu_thermal { 143 /* milliseconds */ 144 polling-delay-passive = <250>; 145 polling-delay = <1000>; 146 thermal-sensors = <&rtp>; 147 148 cooling-maps { 149 map0 { 150 trip = <&cpu_alert0>; 151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 152 }; 153 }; 154 155 trips { 156 cpu_alert0: cpu_alert0 { 157 /* milliCelsius */ 158 temperature = <75000>; 159 hysteresis = <2000>; 160 type = "passive"; 161 }; 162 163 cpu_crit: cpu_crit { 164 /* milliCelsius */ 165 temperature = <100000>; 166 hysteresis = <2000>; 167 type = "critical"; 168 }; 169 }; 170 }; 171 }; 172 173 memory { 174 reg = <0x40000000 0x80000000>; 175 }; 176 177 timer { 178 compatible = "arm,armv7-timer"; 179 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 180 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 181 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 182 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 183 }; 184 185 pmu { 186 compatible = "arm,cortex-a7-pmu"; 187 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 clocks { 192 #address-cells = <1>; 193 #size-cells = <1>; 194 ranges; 195 196 osc24M: clk@1c20050 { 197 #clock-cells = <0>; 198 compatible = "fixed-clock"; 199 clock-frequency = <24000000>; 200 clock-output-names = "osc24M"; 201 }; 202 203 osc32k: clk@0 { 204 #clock-cells = <0>; 205 compatible = "fixed-clock"; 206 clock-frequency = <32768>; 207 clock-output-names = "osc32k"; 208 }; 209 210 /* 211 * The following two are dummy clocks, placeholders 212 * used in the gmac_tx clock. The gmac driver will 213 * choose one parent depending on the PHY interface 214 * mode, using clk_set_rate auto-reparenting. 215 * 216 * The actual TX clock rate is not controlled by the 217 * gmac_tx clock. 218 */ 219 mii_phy_tx_clk: clk@1 { 220 #clock-cells = <0>; 221 compatible = "fixed-clock"; 222 clock-frequency = <25000000>; 223 clock-output-names = "mii_phy_tx"; 224 }; 225 226 gmac_int_tx_clk: clk@2 { 227 #clock-cells = <0>; 228 compatible = "fixed-clock"; 229 clock-frequency = <125000000>; 230 clock-output-names = "gmac_int_tx"; 231 }; 232 233 gmac_tx_clk: clk@1c20164 { 234 #clock-cells = <0>; 235 compatible = "allwinner,sun7i-a20-gmac-clk"; 236 reg = <0x01c20164 0x4>; 237 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 238 clock-output-names = "gmac_tx"; 239 }; 240 }; 241 242 243 de: display-engine { 244 compatible = "allwinner,sun7i-a20-display-engine"; 245 allwinner,pipelines = <&fe0>, <&fe1>; 246 status = "disabled"; 247 }; 248 249 soc@1c00000 { 250 compatible = "simple-bus"; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges; 254 255 system-control@1c00000 { 256 compatible = "allwinner,sun7i-a20-system-control", 257 "allwinner,sun4i-a10-system-control"; 258 reg = <0x01c00000 0x30>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 ranges; 262 263 sram_a: sram@0 { 264 compatible = "mmio-sram"; 265 reg = <0x00000000 0xc000>; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 ranges = <0 0x00000000 0xc000>; 269 270 emac_sram: sram-section@8000 { 271 compatible = "allwinner,sun7i-a20-sram-a3-a4", 272 "allwinner,sun4i-a10-sram-a3-a4"; 273 reg = <0x8000 0x4000>; 274 status = "disabled"; 275 }; 276 }; 277 278 sram_d: sram@10000 { 279 compatible = "mmio-sram"; 280 reg = <0x00010000 0x1000>; 281 #address-cells = <1>; 282 #size-cells = <1>; 283 ranges = <0 0x00010000 0x1000>; 284 285 otg_sram: sram-section@0 { 286 compatible = "allwinner,sun7i-a20-sram-d", 287 "allwinner,sun4i-a10-sram-d"; 288 reg = <0x0000 0x1000>; 289 status = "disabled"; 290 }; 291 }; 292 293 sram_c: sram@1d00000 { 294 compatible = "mmio-sram"; 295 reg = <0x01d00000 0xd0000>; 296 #address-cells = <1>; 297 #size-cells = <1>; 298 ranges = <0 0x01d00000 0xd0000>; 299 300 ve_sram: sram-section@0 { 301 compatible = "allwinner,sun7i-a20-sram-c1", 302 "allwinner,sun4i-a10-sram-c1"; 303 reg = <0x000000 0x80000>; 304 }; 305 }; 306 }; 307 308 nmi_intc: interrupt-controller@1c00030 { 309 compatible = "allwinner,sun7i-a20-sc-nmi"; 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 reg = <0x01c00030 0x0c>; 313 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 dma: dma-controller@1c02000 { 317 compatible = "allwinner,sun4i-a10-dma"; 318 reg = <0x01c02000 0x1000>; 319 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&ccu CLK_AHB_DMA>; 321 #dma-cells = <2>; 322 }; 323 324 nfc: nand@1c03000 { 325 compatible = "allwinner,sun4i-a10-nand"; 326 reg = <0x01c03000 0x1000>; 327 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; 329 clock-names = "ahb", "mod"; 330 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 331 dma-names = "rxtx"; 332 status = "disabled"; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 }; 336 337 spi0: spi@1c05000 { 338 compatible = "allwinner,sun4i-a10-spi"; 339 reg = <0x01c05000 0x1000>; 340 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; 342 clock-names = "ahb", "mod"; 343 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 344 <&dma SUN4I_DMA_DEDICATED 26>; 345 dma-names = "rx", "tx"; 346 status = "disabled"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 num-cs = <4>; 350 }; 351 352 spi1: spi@1c06000 { 353 compatible = "allwinner,sun4i-a10-spi"; 354 reg = <0x01c06000 0x1000>; 355 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; 357 clock-names = "ahb", "mod"; 358 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 359 <&dma SUN4I_DMA_DEDICATED 8>; 360 dma-names = "rx", "tx"; 361 status = "disabled"; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 num-cs = <1>; 365 }; 366 367 emac: ethernet@1c0b000 { 368 compatible = "allwinner,sun4i-a10-emac"; 369 reg = <0x01c0b000 0x1000>; 370 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&ccu CLK_AHB_EMAC>; 372 allwinner,sram = <&emac_sram 1>; 373 status = "disabled"; 374 }; 375 376 mdio: mdio@1c0b080 { 377 compatible = "allwinner,sun4i-a10-mdio"; 378 reg = <0x01c0b080 0x14>; 379 status = "disabled"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 }; 383 384 tcon0: lcd-controller@1c0c000 { 385 compatible = "allwinner,sun7i-a20-tcon"; 386 reg = <0x01c0c000 0x1000>; 387 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 388 resets = <&ccu RST_TCON0>; 389 reset-names = "lcd"; 390 clocks = <&ccu CLK_AHB_LCD0>, 391 <&ccu CLK_TCON0_CH0>, 392 <&ccu CLK_TCON0_CH1>; 393 clock-names = "ahb", 394 "tcon-ch0", 395 "tcon-ch1"; 396 clock-output-names = "tcon0-pixel-clock"; 397 dmas = <&dma SUN4I_DMA_DEDICATED 14>; 398 399 ports { 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 tcon0_in: port@0 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0>; 407 408 tcon0_in_be0: endpoint@0 { 409 reg = <0>; 410 remote-endpoint = <&be0_out_tcon0>; 411 }; 412 413 tcon0_in_be1: endpoint@1 { 414 reg = <1>; 415 remote-endpoint = <&be1_out_tcon0>; 416 }; 417 }; 418 419 tcon0_out: port@1 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <1>; 423 424 tcon0_out_hdmi: endpoint@1 { 425 reg = <1>; 426 remote-endpoint = <&hdmi_in_tcon0>; 427 allwinner,tcon-channel = <1>; 428 }; 429 }; 430 }; 431 }; 432 433 tcon1: lcd-controller@1c0d000 { 434 compatible = "allwinner,sun7i-a20-tcon"; 435 reg = <0x01c0d000 0x1000>; 436 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 437 resets = <&ccu RST_TCON1>; 438 reset-names = "lcd"; 439 clocks = <&ccu CLK_AHB_LCD1>, 440 <&ccu CLK_TCON1_CH0>, 441 <&ccu CLK_TCON1_CH1>; 442 clock-names = "ahb", 443 "tcon-ch0", 444 "tcon-ch1"; 445 clock-output-names = "tcon1-pixel-clock"; 446 dmas = <&dma SUN4I_DMA_DEDICATED 15>; 447 448 ports { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 452 tcon1_in: port@0 { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 reg = <0>; 456 457 tcon1_in_be0: endpoint@0 { 458 reg = <0>; 459 remote-endpoint = <&be0_out_tcon1>; 460 }; 461 462 tcon1_in_be1: endpoint@1 { 463 reg = <1>; 464 remote-endpoint = <&be1_out_tcon1>; 465 }; 466 }; 467 468 tcon1_out: port@1 { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 reg = <1>; 472 473 tcon1_out_hdmi: endpoint@1 { 474 reg = <1>; 475 remote-endpoint = <&hdmi_in_tcon1>; 476 allwinner,tcon-channel = <1>; 477 }; 478 }; 479 }; 480 }; 481 482 mmc0: mmc@1c0f000 { 483 compatible = "allwinner,sun7i-a20-mmc"; 484 reg = <0x01c0f000 0x1000>; 485 clocks = <&ccu CLK_AHB_MMC0>, 486 <&ccu CLK_MMC0>, 487 <&ccu CLK_MMC0_OUTPUT>, 488 <&ccu CLK_MMC0_SAMPLE>; 489 clock-names = "ahb", 490 "mmc", 491 "output", 492 "sample"; 493 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 494 status = "disabled"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 }; 498 499 mmc1: mmc@1c10000 { 500 compatible = "allwinner,sun7i-a20-mmc"; 501 reg = <0x01c10000 0x1000>; 502 clocks = <&ccu CLK_AHB_MMC1>, 503 <&ccu CLK_MMC1>, 504 <&ccu CLK_MMC1_OUTPUT>, 505 <&ccu CLK_MMC1_SAMPLE>; 506 clock-names = "ahb", 507 "mmc", 508 "output", 509 "sample"; 510 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 511 status = "disabled"; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 }; 515 516 mmc2: mmc@1c11000 { 517 compatible = "allwinner,sun7i-a20-mmc"; 518 reg = <0x01c11000 0x1000>; 519 clocks = <&ccu CLK_AHB_MMC2>, 520 <&ccu CLK_MMC2>, 521 <&ccu CLK_MMC2_OUTPUT>, 522 <&ccu CLK_MMC2_SAMPLE>; 523 clock-names = "ahb", 524 "mmc", 525 "output", 526 "sample"; 527 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 528 status = "disabled"; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 }; 532 533 mmc3: mmc@1c12000 { 534 compatible = "allwinner,sun7i-a20-mmc"; 535 reg = <0x01c12000 0x1000>; 536 clocks = <&ccu CLK_AHB_MMC3>, 537 <&ccu CLK_MMC3>, 538 <&ccu CLK_MMC3_OUTPUT>, 539 <&ccu CLK_MMC3_SAMPLE>; 540 clock-names = "ahb", 541 "mmc", 542 "output", 543 "sample"; 544 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 545 status = "disabled"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 }; 549 550 usb_otg: usb@1c13000 { 551 compatible = "allwinner,sun4i-a10-musb"; 552 reg = <0x01c13000 0x0400>; 553 clocks = <&ccu CLK_AHB_OTG>; 554 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 555 interrupt-names = "mc"; 556 phys = <&usbphy 0>; 557 phy-names = "usb"; 558 extcon = <&usbphy 0>; 559 allwinner,sram = <&otg_sram 1>; 560 status = "disabled"; 561 }; 562 563 usbphy: phy@1c13400 { 564 #phy-cells = <1>; 565 compatible = "allwinner,sun7i-a20-usb-phy"; 566 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 567 reg-names = "phy_ctrl", "pmu1", "pmu2"; 568 clocks = <&ccu CLK_USB_PHY>; 569 clock-names = "usb_phy"; 570 resets = <&ccu RST_USB_PHY0>, 571 <&ccu RST_USB_PHY1>, 572 <&ccu RST_USB_PHY2>; 573 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 574 status = "disabled"; 575 }; 576 577 ehci0: usb@1c14000 { 578 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 579 reg = <0x01c14000 0x100>; 580 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&ccu CLK_AHB_EHCI0>; 582 phys = <&usbphy 1>; 583 phy-names = "usb"; 584 status = "disabled"; 585 }; 586 587 ohci0: usb@1c14400 { 588 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 589 reg = <0x01c14400 0x100>; 590 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; 592 phys = <&usbphy 1>; 593 phy-names = "usb"; 594 status = "disabled"; 595 }; 596 597 crypto: crypto-engine@1c15000 { 598 compatible = "allwinner,sun7i-a20-crypto", 599 "allwinner,sun4i-a10-crypto"; 600 reg = <0x01c15000 0x1000>; 601 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; 603 clock-names = "ahb", "mod"; 604 }; 605 606 hdmi: hdmi@1c16000 { 607 compatible = "allwinner,sun7i-a20-hdmi", 608 "allwinner,sun5i-a10s-hdmi"; 609 reg = <0x01c16000 0x1000>; 610 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, 612 <&ccu CLK_PLL_VIDEO0_2X>, 613 <&ccu CLK_PLL_VIDEO1_2X>; 614 clock-names = "ahb", "mod", "pll-0", "pll-1"; 615 dmas = <&dma SUN4I_DMA_NORMAL 16>, 616 <&dma SUN4I_DMA_NORMAL 16>, 617 <&dma SUN4I_DMA_DEDICATED 24>; 618 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 619 status = "disabled"; 620 621 ports { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 625 hdmi_in: port@0 { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 reg = <0>; 629 630 hdmi_in_tcon0: endpoint@0 { 631 reg = <0>; 632 remote-endpoint = <&tcon0_out_hdmi>; 633 }; 634 635 hdmi_in_tcon1: endpoint@1 { 636 reg = <1>; 637 remote-endpoint = <&tcon1_out_hdmi>; 638 }; 639 }; 640 641 hdmi_out: port@1 { 642 reg = <1>; 643 }; 644 }; 645 }; 646 647 spi2: spi@1c17000 { 648 compatible = "allwinner,sun4i-a10-spi"; 649 reg = <0x01c17000 0x1000>; 650 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; 652 clock-names = "ahb", "mod"; 653 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 654 <&dma SUN4I_DMA_DEDICATED 28>; 655 dma-names = "rx", "tx"; 656 status = "disabled"; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 num-cs = <1>; 660 }; 661 662 ahci: sata@1c18000 { 663 compatible = "allwinner,sun4i-a10-ahci"; 664 reg = <0x01c18000 0x1000>; 665 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; 667 status = "disabled"; 668 }; 669 670 ehci1: usb@1c1c000 { 671 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 672 reg = <0x01c1c000 0x100>; 673 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&ccu CLK_AHB_EHCI1>; 675 phys = <&usbphy 2>; 676 phy-names = "usb"; 677 status = "disabled"; 678 }; 679 680 ohci1: usb@1c1c400 { 681 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 682 reg = <0x01c1c400 0x100>; 683 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; 685 phys = <&usbphy 2>; 686 phy-names = "usb"; 687 status = "disabled"; 688 }; 689 690 spi3: spi@1c1f000 { 691 compatible = "allwinner,sun4i-a10-spi"; 692 reg = <0x01c1f000 0x1000>; 693 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; 695 clock-names = "ahb", "mod"; 696 dmas = <&dma SUN4I_DMA_DEDICATED 31>, 697 <&dma SUN4I_DMA_DEDICATED 30>; 698 dma-names = "rx", "tx"; 699 status = "disabled"; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 num-cs = <1>; 703 }; 704 705 ccu: clock@1c20000 { 706 compatible = "allwinner,sun7i-a20-ccu"; 707 reg = <0x01c20000 0x400>; 708 clocks = <&osc24M>, <&osc32k>; 709 clock-names = "hosc", "losc"; 710 #clock-cells = <1>; 711 #reset-cells = <1>; 712 }; 713 714 pio: pinctrl@1c20800 { 715 compatible = "allwinner,sun7i-a20-pinctrl"; 716 reg = <0x01c20800 0x400>; 717 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 719 clock-names = "apb", "hosc", "losc"; 720 gpio-controller; 721 interrupt-controller; 722 #interrupt-cells = <3>; 723 #gpio-cells = <3>; 724 725 can0_pins_a: can0@0 { 726 pins = "PH20", "PH21"; 727 function = "can"; 728 }; 729 730 clk_out_a_pins_a: clk_out_a@0 { 731 pins = "PI12"; 732 function = "clk_out_a"; 733 }; 734 735 clk_out_b_pins_a: clk_out_b@0 { 736 pins = "PI13"; 737 function = "clk_out_b"; 738 }; 739 740 emac_pins_a: emac0@0 { 741 pins = "PA0", "PA1", "PA2", 742 "PA3", "PA4", "PA5", "PA6", 743 "PA7", "PA8", "PA9", "PA10", 744 "PA11", "PA12", "PA13", "PA14", 745 "PA15", "PA16"; 746 function = "emac"; 747 }; 748 749 gmac_pins_mii_a: gmac_mii@0 { 750 pins = "PA0", "PA1", "PA2", 751 "PA3", "PA4", "PA5", "PA6", 752 "PA7", "PA8", "PA9", "PA10", 753 "PA11", "PA12", "PA13", "PA14", 754 "PA15", "PA16"; 755 function = "gmac"; 756 }; 757 758 gmac_pins_rgmii_a: gmac_rgmii@0 { 759 pins = "PA0", "PA1", "PA2", 760 "PA3", "PA4", "PA5", "PA6", 761 "PA7", "PA8", "PA10", 762 "PA11", "PA12", "PA13", 763 "PA15", "PA16"; 764 function = "gmac"; 765 /* 766 * data lines in RGMII mode use DDR mode 767 * and need a higher signal drive strength 768 */ 769 drive-strength = <40>; 770 }; 771 772 i2c0_pins_a: i2c0@0 { 773 pins = "PB0", "PB1"; 774 function = "i2c0"; 775 }; 776 777 i2c1_pins_a: i2c1@0 { 778 pins = "PB18", "PB19"; 779 function = "i2c1"; 780 }; 781 782 i2c2_pins_a: i2c2@0 { 783 pins = "PB20", "PB21"; 784 function = "i2c2"; 785 }; 786 787 i2c3_pins_a: i2c3@0 { 788 pins = "PI0", "PI1"; 789 function = "i2c3"; 790 }; 791 792 ir0_rx_pins_a: ir0@0 { 793 pins = "PB4"; 794 function = "ir0"; 795 }; 796 797 ir0_tx_pins_a: ir0@1 { 798 pins = "PB3"; 799 function = "ir0"; 800 }; 801 802 ir1_rx_pins_a: ir1@0 { 803 pins = "PB23"; 804 function = "ir1"; 805 }; 806 807 ir1_tx_pins_a: ir1@1 { 808 pins = "PB22"; 809 function = "ir1"; 810 }; 811 812 mmc0_pins_a: mmc0@0 { 813 pins = "PF0", "PF1", "PF2", 814 "PF3", "PF4", "PF5"; 815 function = "mmc0"; 816 drive-strength = <30>; 817 bias-pull-up; 818 }; 819 820 mmc2_pins_a: mmc2@0 { 821 pins = "PC6", "PC7", "PC8", 822 "PC9", "PC10", "PC11"; 823 function = "mmc2"; 824 drive-strength = <30>; 825 bias-pull-up; 826 }; 827 828 mmc3_pins_a: mmc3@0 { 829 pins = "PI4", "PI5", "PI6", 830 "PI7", "PI8", "PI9"; 831 function = "mmc3"; 832 drive-strength = <30>; 833 bias-pull-up; 834 }; 835 836 ps20_pins_a: ps20@0 { 837 pins = "PI20", "PI21"; 838 function = "ps2"; 839 }; 840 841 ps21_pins_a: ps21@0 { 842 pins = "PH12", "PH13"; 843 function = "ps2"; 844 }; 845 846 pwm0_pins_a: pwm0@0 { 847 pins = "PB2"; 848 function = "pwm"; 849 }; 850 851 pwm1_pins_a: pwm1@0 { 852 pins = "PI3"; 853 function = "pwm"; 854 }; 855 856 spdif_tx_pins_a: spdif@0 { 857 pins = "PB13"; 858 function = "spdif"; 859 bias-pull-up; 860 }; 861 862 spi0_pins_a: spi0@0 { 863 pins = "PI11", "PI12", "PI13"; 864 function = "spi0"; 865 }; 866 867 spi0_cs0_pins_a: spi0_cs0@0 { 868 pins = "PI10"; 869 function = "spi0"; 870 }; 871 872 spi0_cs1_pins_a: spi0_cs1@0 { 873 pins = "PI14"; 874 function = "spi0"; 875 }; 876 877 spi1_pins_a: spi1@0 { 878 pins = "PI17", "PI18", "PI19"; 879 function = "spi1"; 880 }; 881 882 spi1_cs0_pins_a: spi1_cs0@0 { 883 pins = "PI16"; 884 function = "spi1"; 885 }; 886 887 spi2_pins_a: spi2@0 { 888 pins = "PC20", "PC21", "PC22"; 889 function = "spi2"; 890 }; 891 892 spi2_pins_b: spi2@1 { 893 pins = "PB15", "PB16", "PB17"; 894 function = "spi2"; 895 }; 896 897 spi2_cs0_pins_a: spi2_cs0@0 { 898 pins = "PC19"; 899 function = "spi2"; 900 }; 901 902 spi2_cs0_pins_b: spi2_cs0@1 { 903 pins = "PB14"; 904 function = "spi2"; 905 }; 906 907 uart0_pins_a: uart0@0 { 908 pins = "PB22", "PB23"; 909 function = "uart0"; 910 }; 911 912 uart2_pins_a: uart2@0 { 913 pins = "PI16", "PI17", "PI18", "PI19"; 914 function = "uart2"; 915 }; 916 917 uart3_pins_a: uart3@0 { 918 pins = "PG6", "PG7", "PG8", "PG9"; 919 function = "uart3"; 920 }; 921 922 uart3_pins_b: uart3@1 { 923 pins = "PH0", "PH1"; 924 function = "uart3"; 925 }; 926 927 uart4_pins_a: uart4@0 { 928 pins = "PG10", "PG11"; 929 function = "uart4"; 930 }; 931 932 uart4_pins_b: uart4@1 { 933 pins = "PH4", "PH5"; 934 function = "uart4"; 935 }; 936 937 uart5_pins_a: uart5@0 { 938 pins = "PI10", "PI11"; 939 function = "uart5"; 940 }; 941 942 uart6_pins_a: uart6@0 { 943 pins = "PI12", "PI13"; 944 function = "uart6"; 945 }; 946 947 uart7_pins_a: uart7@0 { 948 pins = "PI20", "PI21"; 949 function = "uart7"; 950 }; 951 }; 952 953 timer@1c20c00 { 954 compatible = "allwinner,sun4i-a10-timer"; 955 reg = <0x01c20c00 0x90>; 956 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&osc24M>; 963 }; 964 965 wdt: watchdog@1c20c90 { 966 compatible = "allwinner,sun4i-a10-wdt"; 967 reg = <0x01c20c90 0x10>; 968 }; 969 970 rtc: rtc@1c20d00 { 971 compatible = "allwinner,sun7i-a20-rtc"; 972 reg = <0x01c20d00 0x20>; 973 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 974 }; 975 976 pwm: pwm@1c20e00 { 977 compatible = "allwinner,sun7i-a20-pwm"; 978 reg = <0x01c20e00 0xc>; 979 clocks = <&osc24M>; 980 #pwm-cells = <3>; 981 status = "disabled"; 982 }; 983 984 spdif: spdif@1c21000 { 985 #sound-dai-cells = <0>; 986 compatible = "allwinner,sun4i-a10-spdif"; 987 reg = <0x01c21000 0x400>; 988 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; 990 clock-names = "apb", "spdif"; 991 dmas = <&dma SUN4I_DMA_NORMAL 2>, 992 <&dma SUN4I_DMA_NORMAL 2>; 993 dma-names = "rx", "tx"; 994 status = "disabled"; 995 }; 996 997 ir0: ir@1c21800 { 998 compatible = "allwinner,sun4i-a10-ir"; 999 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; 1000 clock-names = "apb", "ir"; 1001 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1002 reg = <0x01c21800 0x40>; 1003 status = "disabled"; 1004 }; 1005 1006 ir1: ir@1c21c00 { 1007 compatible = "allwinner,sun4i-a10-ir"; 1008 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; 1009 clock-names = "apb", "ir"; 1010 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1011 reg = <0x01c21c00 0x40>; 1012 status = "disabled"; 1013 }; 1014 1015 i2s1: i2s@1c22000 { 1016 #sound-dai-cells = <0>; 1017 compatible = "allwinner,sun4i-a10-i2s"; 1018 reg = <0x01c22000 0x400>; 1019 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; 1021 clock-names = "apb", "mod"; 1022 dmas = <&dma SUN4I_DMA_NORMAL 4>, 1023 <&dma SUN4I_DMA_NORMAL 4>; 1024 dma-names = "rx", "tx"; 1025 status = "disabled"; 1026 }; 1027 1028 i2s0: i2s@1c22400 { 1029 #sound-dai-cells = <0>; 1030 compatible = "allwinner,sun4i-a10-i2s"; 1031 reg = <0x01c22400 0x400>; 1032 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; 1034 clock-names = "apb", "mod"; 1035 dmas = <&dma SUN4I_DMA_NORMAL 3>, 1036 <&dma SUN4I_DMA_NORMAL 3>; 1037 dma-names = "rx", "tx"; 1038 status = "disabled"; 1039 }; 1040 1041 lradc: lradc@1c22800 { 1042 compatible = "allwinner,sun4i-a10-lradc-keys"; 1043 reg = <0x01c22800 0x100>; 1044 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1045 status = "disabled"; 1046 }; 1047 1048 codec: codec@1c22c00 { 1049 #sound-dai-cells = <0>; 1050 compatible = "allwinner,sun7i-a20-codec"; 1051 reg = <0x01c22c00 0x40>; 1052 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; 1054 clock-names = "apb", "codec"; 1055 dmas = <&dma SUN4I_DMA_NORMAL 19>, 1056 <&dma SUN4I_DMA_NORMAL 19>; 1057 dma-names = "rx", "tx"; 1058 status = "disabled"; 1059 }; 1060 1061 sid: eeprom@1c23800 { 1062 compatible = "allwinner,sun7i-a20-sid"; 1063 reg = <0x01c23800 0x200>; 1064 }; 1065 1066 i2s2: i2s@1c24400 { 1067 #sound-dai-cells = <0>; 1068 compatible = "allwinner,sun4i-a10-i2s"; 1069 reg = <0x01c24400 0x400>; 1070 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; 1072 clock-names = "apb", "mod"; 1073 dmas = <&dma SUN4I_DMA_NORMAL 6>, 1074 <&dma SUN4I_DMA_NORMAL 6>; 1075 dma-names = "rx", "tx"; 1076 status = "disabled"; 1077 }; 1078 1079 rtp: rtp@1c25000 { 1080 compatible = "allwinner,sun5i-a13-ts"; 1081 reg = <0x01c25000 0x100>; 1082 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1083 #thermal-sensor-cells = <0>; 1084 }; 1085 1086 uart0: serial@1c28000 { 1087 compatible = "snps,dw-apb-uart"; 1088 reg = <0x01c28000 0x400>; 1089 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1090 reg-shift = <2>; 1091 reg-io-width = <4>; 1092 clocks = <&ccu CLK_APB1_UART0>; 1093 status = "disabled"; 1094 }; 1095 1096 uart1: serial@1c28400 { 1097 compatible = "snps,dw-apb-uart"; 1098 reg = <0x01c28400 0x400>; 1099 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1100 reg-shift = <2>; 1101 reg-io-width = <4>; 1102 clocks = <&ccu CLK_APB1_UART1>; 1103 status = "disabled"; 1104 }; 1105 1106 uart2: serial@1c28800 { 1107 compatible = "snps,dw-apb-uart"; 1108 reg = <0x01c28800 0x400>; 1109 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1110 reg-shift = <2>; 1111 reg-io-width = <4>; 1112 clocks = <&ccu CLK_APB1_UART2>; 1113 status = "disabled"; 1114 }; 1115 1116 uart3: serial@1c28c00 { 1117 compatible = "snps,dw-apb-uart"; 1118 reg = <0x01c28c00 0x400>; 1119 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1120 reg-shift = <2>; 1121 reg-io-width = <4>; 1122 clocks = <&ccu CLK_APB1_UART3>; 1123 status = "disabled"; 1124 }; 1125 1126 uart4: serial@1c29000 { 1127 compatible = "snps,dw-apb-uart"; 1128 reg = <0x01c29000 0x400>; 1129 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1130 reg-shift = <2>; 1131 reg-io-width = <4>; 1132 clocks = <&ccu CLK_APB1_UART4>; 1133 status = "disabled"; 1134 }; 1135 1136 uart5: serial@1c29400 { 1137 compatible = "snps,dw-apb-uart"; 1138 reg = <0x01c29400 0x400>; 1139 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1140 reg-shift = <2>; 1141 reg-io-width = <4>; 1142 clocks = <&ccu CLK_APB1_UART5>; 1143 status = "disabled"; 1144 }; 1145 1146 uart6: serial@1c29800 { 1147 compatible = "snps,dw-apb-uart"; 1148 reg = <0x01c29800 0x400>; 1149 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1150 reg-shift = <2>; 1151 reg-io-width = <4>; 1152 clocks = <&ccu CLK_APB1_UART6>; 1153 status = "disabled"; 1154 }; 1155 1156 uart7: serial@1c29c00 { 1157 compatible = "snps,dw-apb-uart"; 1158 reg = <0x01c29c00 0x400>; 1159 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1160 reg-shift = <2>; 1161 reg-io-width = <4>; 1162 clocks = <&ccu CLK_APB1_UART7>; 1163 status = "disabled"; 1164 }; 1165 1166 ps20: ps2@1c2a000 { 1167 compatible = "allwinner,sun4i-a10-ps2"; 1168 reg = <0x01c2a000 0x400>; 1169 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&ccu CLK_APB1_PS20>; 1171 status = "disabled"; 1172 }; 1173 1174 ps21: ps2@1c2a400 { 1175 compatible = "allwinner,sun4i-a10-ps2"; 1176 reg = <0x01c2a400 0x400>; 1177 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&ccu CLK_APB1_PS21>; 1179 status = "disabled"; 1180 }; 1181 1182 i2c0: i2c@1c2ac00 { 1183 compatible = "allwinner,sun7i-a20-i2c", 1184 "allwinner,sun4i-a10-i2c"; 1185 reg = <0x01c2ac00 0x400>; 1186 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&ccu CLK_APB1_I2C0>; 1188 status = "disabled"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 }; 1192 1193 i2c1: i2c@1c2b000 { 1194 compatible = "allwinner,sun7i-a20-i2c", 1195 "allwinner,sun4i-a10-i2c"; 1196 reg = <0x01c2b000 0x400>; 1197 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&ccu CLK_APB1_I2C1>; 1199 status = "disabled"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 }; 1203 1204 i2c2: i2c@1c2b400 { 1205 compatible = "allwinner,sun7i-a20-i2c", 1206 "allwinner,sun4i-a10-i2c"; 1207 reg = <0x01c2b400 0x400>; 1208 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&ccu CLK_APB1_I2C2>; 1210 status = "disabled"; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 }; 1214 1215 i2c3: i2c@1c2b800 { 1216 compatible = "allwinner,sun7i-a20-i2c", 1217 "allwinner,sun4i-a10-i2c"; 1218 reg = <0x01c2b800 0x400>; 1219 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&ccu CLK_APB1_I2C3>; 1221 status = "disabled"; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 }; 1225 1226 can0: can@1c2bc00 { 1227 compatible = "allwinner,sun7i-a20-can", 1228 "allwinner,sun4i-a10-can"; 1229 reg = <0x01c2bc00 0x400>; 1230 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&ccu CLK_APB1_CAN>; 1232 status = "disabled"; 1233 }; 1234 1235 i2c4: i2c@1c2c000 { 1236 compatible = "allwinner,sun7i-a20-i2c", 1237 "allwinner,sun4i-a10-i2c"; 1238 reg = <0x01c2c000 0x400>; 1239 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&ccu CLK_APB1_I2C4>; 1241 status = "disabled"; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 }; 1245 1246 mali: gpu@1c40000 { 1247 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 1248 reg = <0x01c40000 0x10000>; 1249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1256 interrupt-names = "gp", 1257 "gpmmu", 1258 "pp0", 1259 "ppmmu0", 1260 "pp1", 1261 "ppmmu1", 1262 "pmu"; 1263 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; 1264 clock-names = "bus", "core"; 1265 resets = <&ccu RST_GPU>; 1266 1267 assigned-clocks = <&ccu CLK_GPU>; 1268 assigned-clock-rates = <384000000>; 1269 }; 1270 1271 gmac: ethernet@1c50000 { 1272 compatible = "allwinner,sun7i-a20-gmac"; 1273 reg = <0x01c50000 0x10000>; 1274 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1275 interrupt-names = "macirq"; 1276 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; 1277 clock-names = "stmmaceth", "allwinner_gmac_tx"; 1278 snps,pbl = <2>; 1279 snps,fixed-burst; 1280 snps,force_sf_dma_mode; 1281 status = "disabled"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 }; 1285 1286 hstimer@1c60000 { 1287 compatible = "allwinner,sun7i-a20-hstimer"; 1288 reg = <0x01c60000 0x1000>; 1289 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&ccu CLK_AHB_HSTIMER>; 1294 }; 1295 1296 gic: interrupt-controller@1c81000 { 1297 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 1298 reg = <0x01c81000 0x1000>, 1299 <0x01c82000 0x2000>, 1300 <0x01c84000 0x2000>, 1301 <0x01c86000 0x2000>; 1302 interrupt-controller; 1303 #interrupt-cells = <3>; 1304 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1305 }; 1306 1307 fe0: display-frontend@1e00000 { 1308 compatible = "allwinner,sun7i-a20-display-frontend"; 1309 reg = <0x01e00000 0x20000>; 1310 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1311 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, 1312 <&ccu CLK_DRAM_DE_FE0>; 1313 clock-names = "ahb", "mod", 1314 "ram"; 1315 resets = <&ccu RST_DE_FE0>; 1316 1317 ports { 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 1321 fe0_out: port@1 { 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 reg = <1>; 1325 1326 fe0_out_be0: endpoint@0 { 1327 reg = <0>; 1328 remote-endpoint = <&be0_in_fe0>; 1329 }; 1330 1331 fe0_out_be1: endpoint@1 { 1332 reg = <1>; 1333 remote-endpoint = <&be1_in_fe0>; 1334 }; 1335 }; 1336 }; 1337 }; 1338 1339 fe1: display-frontend@1e20000 { 1340 compatible = "allwinner,sun7i-a20-display-frontend"; 1341 reg = <0x01e20000 0x20000>; 1342 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1343 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, 1344 <&ccu CLK_DRAM_DE_FE1>; 1345 clock-names = "ahb", "mod", 1346 "ram"; 1347 resets = <&ccu RST_DE_FE1>; 1348 1349 ports { 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 1353 fe1_out: port@1 { 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 reg = <1>; 1357 1358 fe1_out_be0: endpoint@0 { 1359 reg = <0>; 1360 remote-endpoint = <&be0_in_fe1>; 1361 }; 1362 1363 fe1_out_be1: endpoint@1 { 1364 reg = <1>; 1365 remote-endpoint = <&be1_in_fe1>; 1366 }; 1367 }; 1368 }; 1369 }; 1370 1371 be1: display-backend@1e40000 { 1372 compatible = "allwinner,sun7i-a20-display-backend"; 1373 reg = <0x01e40000 0x10000>; 1374 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, 1376 <&ccu CLK_DRAM_DE_BE1>; 1377 clock-names = "ahb", "mod", 1378 "ram"; 1379 resets = <&ccu RST_DE_BE1>; 1380 1381 ports { 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 1385 be1_in: port@0 { 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 reg = <0>; 1389 1390 be1_in_fe0: endpoint@0 { 1391 reg = <0>; 1392 remote-endpoint = <&fe0_out_be1>; 1393 }; 1394 1395 be1_in_fe1: endpoint@1 { 1396 reg = <1>; 1397 remote-endpoint = <&fe1_out_be1>; 1398 }; 1399 }; 1400 1401 be1_out: port@1 { 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 reg = <1>; 1405 1406 be1_out_tcon0: endpoint@0 { 1407 reg = <0>; 1408 remote-endpoint = <&tcon0_in_be1>; 1409 }; 1410 1411 be1_out_tcon1: endpoint@1 { 1412 reg = <1>; 1413 remote-endpoint = <&tcon1_in_be1>; 1414 }; 1415 }; 1416 }; 1417 }; 1418 1419 be0: display-backend@1e60000 { 1420 compatible = "allwinner,sun7i-a20-display-backend"; 1421 reg = <0x01e60000 0x10000>; 1422 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, 1424 <&ccu CLK_DRAM_DE_BE0>; 1425 clock-names = "ahb", "mod", 1426 "ram"; 1427 resets = <&ccu RST_DE_BE0>; 1428 1429 ports { 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 be0_in: port@0 { 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 reg = <0>; 1437 1438 be0_in_fe0: endpoint@0 { 1439 reg = <0>; 1440 remote-endpoint = <&fe0_out_be0>; 1441 }; 1442 1443 be0_in_fe1: endpoint@1 { 1444 reg = <1>; 1445 remote-endpoint = <&fe1_out_be0>; 1446 }; 1447 }; 1448 1449 be0_out: port@1 { 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 reg = <1>; 1453 1454 be0_out_tcon0: endpoint@0 { 1455 reg = <0>; 1456 remote-endpoint = <&tcon0_in_be0>; 1457 }; 1458 1459 be0_out_tcon1: endpoint@1 { 1460 reg = <1>; 1461 remote-endpoint = <&tcon1_in_be0>; 1462 }; 1463 }; 1464 }; 1465 }; 1466 }; 1467}; 1468