1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Versatile Express 4 * 5 * CoreTile Express A9x4 6 * Cortex-A9 MPCore (V2P-CA9) 7 * 8 * HBI-0191B 9 */ 10 11/dts-v1/; 12#include "vexpress-v2m.dtsi" 13 14/ { 15 model = "V2P-CA9"; 16 arm,hbi = <0x191>; 17 arm,vexpress,site = <0xf>; 18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 chosen { }; 24 25 aliases { 26 serial0 = &v2m_serial0; 27 serial1 = &v2m_serial1; 28 serial2 = &v2m_serial2; 29 serial3 = &v2m_serial3; 30 i2c0 = &v2m_i2c_dvi; 31 i2c1 = &v2m_i2c_pcie; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 A9_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 reg = <0>; 42 next-level-cache = <&L2>; 43 }; 44 45 A9_1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a9"; 48 reg = <1>; 49 next-level-cache = <&L2>; 50 }; 51 52 A9_2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a9"; 55 reg = <2>; 56 next-level-cache = <&L2>; 57 }; 58 59 A9_3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a9"; 62 reg = <3>; 63 next-level-cache = <&L2>; 64 }; 65 }; 66 67 memory@60000000 { 68 device_type = "memory"; 69 reg = <0x60000000 0x40000000>; 70 }; 71 72 clcd@10020000 { 73 compatible = "arm,pl111", "arm,primecell"; 74 reg = <0x10020000 0x1000>; 75 interrupt-names = "combined"; 76 interrupts = <0 44 4>; 77 clocks = <&oscclk1>, <&oscclk2>; 78 clock-names = "clcdclk", "apb_pclk"; 79 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ 80 81 port { 82 clcd_pads: endpoint { 83 remote-endpoint = <&clcd_panel>; 84 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 85 }; 86 }; 87 88 panel { 89 compatible = "panel-dpi"; 90 91 port { 92 clcd_panel: endpoint { 93 remote-endpoint = <&clcd_pads>; 94 }; 95 }; 96 97 panel-timing { 98 clock-frequency = <63500127>; 99 hactive = <1024>; 100 hback-porch = <152>; 101 hfront-porch = <48>; 102 hsync-len = <104>; 103 vactive = <768>; 104 vback-porch = <23>; 105 vfront-porch = <3>; 106 vsync-len = <4>; 107 }; 108 }; 109 }; 110 111 memory-controller@100e0000 { 112 compatible = "arm,pl341", "arm,primecell"; 113 reg = <0x100e0000 0x1000>; 114 clocks = <&oscclk2>; 115 clock-names = "apb_pclk"; 116 }; 117 118 memory-controller@100e1000 { 119 compatible = "arm,pl354", "arm,primecell"; 120 reg = <0x100e1000 0x1000>; 121 interrupts = <0 45 4>, 122 <0 46 4>; 123 clocks = <&oscclk2>; 124 clock-names = "apb_pclk"; 125 }; 126 127 timer@100e4000 { 128 compatible = "arm,sp804", "arm,primecell"; 129 reg = <0x100e4000 0x1000>; 130 interrupts = <0 48 4>, 131 <0 49 4>; 132 clocks = <&oscclk2>, <&oscclk2>; 133 clock-names = "timclk", "apb_pclk"; 134 status = "disabled"; 135 }; 136 137 watchdog@100e5000 { 138 compatible = "arm,sp805", "arm,primecell"; 139 reg = <0x100e5000 0x1000>; 140 interrupts = <0 51 4>; 141 clocks = <&oscclk2>, <&oscclk2>; 142 clock-names = "wdogclk", "apb_pclk"; 143 }; 144 145 scu@1e000000 { 146 compatible = "arm,cortex-a9-scu"; 147 reg = <0x1e000000 0x58>; 148 }; 149 150 timer@1e000600 { 151 compatible = "arm,cortex-a9-twd-timer"; 152 reg = <0x1e000600 0x20>; 153 interrupts = <1 13 0xf04>; 154 }; 155 156 watchdog@1e000620 { 157 compatible = "arm,cortex-a9-twd-wdt"; 158 reg = <0x1e000620 0x20>; 159 interrupts = <1 14 0xf04>; 160 }; 161 162 gic: interrupt-controller@1e001000 { 163 compatible = "arm,cortex-a9-gic"; 164 #interrupt-cells = <3>; 165 #address-cells = <0>; 166 interrupt-controller; 167 reg = <0x1e001000 0x1000>, 168 <0x1e000100 0x100>; 169 }; 170 171 L2: cache-controller@1e00a000 { 172 compatible = "arm,pl310-cache"; 173 reg = <0x1e00a000 0x1000>; 174 interrupts = <0 43 4>; 175 cache-unified; 176 cache-level = <2>; 177 arm,data-latency = <1 1 1>; 178 arm,tag-latency = <1 1 1>; 179 }; 180 181 pmu { 182 compatible = "arm,cortex-a9-pmu"; 183 interrupts = <0 60 4>, 184 <0 61 4>, 185 <0 62 4>, 186 <0 63 4>; 187 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; 188 189 }; 190 191 dcc { 192 compatible = "arm,vexpress,config-bus"; 193 arm,vexpress,config-bridge = <&v2m_sysreg>; 194 195 oscclk0: extsaxiclk { 196 /* ACLK clock to the AXI master port on the test chip */ 197 compatible = "arm,vexpress-osc"; 198 arm,vexpress-sysreg,func = <1 0>; 199 freq-range = <30000000 50000000>; 200 #clock-cells = <0>; 201 clock-output-names = "extsaxiclk"; 202 }; 203 204 oscclk1: clcdclk { 205 /* Reference clock for the CLCD */ 206 compatible = "arm,vexpress-osc"; 207 arm,vexpress-sysreg,func = <1 1>; 208 freq-range = <10000000 80000000>; 209 #clock-cells = <0>; 210 clock-output-names = "clcdclk"; 211 }; 212 213 smbclk: oscclk2: tcrefclk { 214 /* Reference clock for the test chip internal PLLs */ 215 compatible = "arm,vexpress-osc"; 216 arm,vexpress-sysreg,func = <1 2>; 217 freq-range = <33000000 100000000>; 218 #clock-cells = <0>; 219 clock-output-names = "tcrefclk"; 220 }; 221 222 volt-vd10 { 223 /* Test Chip internal logic voltage */ 224 compatible = "arm,vexpress-volt"; 225 arm,vexpress-sysreg,func = <2 0>; 226 regulator-name = "VD10"; 227 regulator-always-on; 228 label = "VD10"; 229 }; 230 231 volt-vd10-s2 { 232 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 233 compatible = "arm,vexpress-volt"; 234 arm,vexpress-sysreg,func = <2 1>; 235 regulator-name = "VD10_S2"; 236 regulator-always-on; 237 label = "VD10_S2"; 238 }; 239 240 volt-vd10-s3 { 241 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 242 compatible = "arm,vexpress-volt"; 243 arm,vexpress-sysreg,func = <2 2>; 244 regulator-name = "VD10_S3"; 245 regulator-always-on; 246 label = "VD10_S3"; 247 }; 248 249 volt-vcc1v8 { 250 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ 251 compatible = "arm,vexpress-volt"; 252 arm,vexpress-sysreg,func = <2 3>; 253 regulator-name = "VCC1V8"; 254 regulator-always-on; 255 label = "VCC1V8"; 256 }; 257 258 volt-ddr2vtt { 259 /* DDR2 SDRAM VTT termination voltage */ 260 compatible = "arm,vexpress-volt"; 261 arm,vexpress-sysreg,func = <2 4>; 262 regulator-name = "DDR2VTT"; 263 regulator-always-on; 264 label = "DDR2VTT"; 265 }; 266 267 volt-vcc3v3 { 268 /* Local board supply for miscellaneous logic external to the Test Chip */ 269 arm,vexpress-sysreg,func = <2 5>; 270 compatible = "arm,vexpress-volt"; 271 regulator-name = "VCC3V3"; 272 regulator-always-on; 273 label = "VCC3V3"; 274 }; 275 276 amp-vd10-s2 { 277 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 278 compatible = "arm,vexpress-amp"; 279 arm,vexpress-sysreg,func = <3 0>; 280 label = "VD10_S2"; 281 }; 282 283 amp-vd10-s3 { 284 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 285 compatible = "arm,vexpress-amp"; 286 arm,vexpress-sysreg,func = <3 1>; 287 label = "VD10_S3"; 288 }; 289 290 power-vd10-s2 { 291 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 292 compatible = "arm,vexpress-power"; 293 arm,vexpress-sysreg,func = <12 0>; 294 label = "PVD10_S2"; 295 }; 296 297 power-vd10-s3 { 298 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 299 compatible = "arm,vexpress-power"; 300 arm,vexpress-sysreg,func = <12 1>; 301 label = "PVD10_S3"; 302 }; 303 }; 304 305 smb: smb@4000000 { 306 compatible = "simple-bus"; 307 308 #address-cells = <2>; 309 #size-cells = <1>; 310 ranges = <0 0 0x40000000 0x04000000>, 311 <1 0 0x44000000 0x04000000>, 312 <2 0 0x48000000 0x04000000>, 313 <3 0 0x4c000000 0x04000000>, 314 <7 0 0x10000000 0x00020000>; 315 316 #interrupt-cells = <1>; 317 interrupt-map-mask = <0 0 63>; 318 interrupt-map = <0 0 0 &gic 0 0 4>, 319 <0 0 1 &gic 0 1 4>, 320 <0 0 2 &gic 0 2 4>, 321 <0 0 3 &gic 0 3 4>, 322 <0 0 4 &gic 0 4 4>, 323 <0 0 5 &gic 0 5 4>, 324 <0 0 6 &gic 0 6 4>, 325 <0 0 7 &gic 0 7 4>, 326 <0 0 8 &gic 0 8 4>, 327 <0 0 9 &gic 0 9 4>, 328 <0 0 10 &gic 0 10 4>, 329 <0 0 11 &gic 0 11 4>, 330 <0 0 12 &gic 0 12 4>, 331 <0 0 13 &gic 0 13 4>, 332 <0 0 14 &gic 0 14 4>, 333 <0 0 15 &gic 0 15 4>, 334 <0 0 16 &gic 0 16 4>, 335 <0 0 17 &gic 0 17 4>, 336 <0 0 18 &gic 0 18 4>, 337 <0 0 19 &gic 0 19 4>, 338 <0 0 20 &gic 0 20 4>, 339 <0 0 21 &gic 0 21 4>, 340 <0 0 22 &gic 0 22 4>, 341 <0 0 23 &gic 0 23 4>, 342 <0 0 24 &gic 0 24 4>, 343 <0 0 25 &gic 0 25 4>, 344 <0 0 26 &gic 0 26 4>, 345 <0 0 27 &gic 0 27 4>, 346 <0 0 28 &gic 0 28 4>, 347 <0 0 29 &gic 0 29 4>, 348 <0 0 30 &gic 0 30 4>, 349 <0 0 31 &gic 0 31 4>, 350 <0 0 32 &gic 0 32 4>, 351 <0 0 33 &gic 0 33 4>, 352 <0 0 34 &gic 0 34 4>, 353 <0 0 35 &gic 0 35 4>, 354 <0 0 36 &gic 0 36 4>, 355 <0 0 37 &gic 0 37 4>, 356 <0 0 38 &gic 0 38 4>, 357 <0 0 39 &gic 0 39 4>, 358 <0 0 40 &gic 0 40 4>, 359 <0 0 41 &gic 0 41 4>, 360 <0 0 42 &gic 0 42 4>; 361 }; 362 363 site2: hsb@e0000000 { 364 compatible = "simple-bus"; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 ranges = <0 0xe0000000 0x20000000>; 368 #interrupt-cells = <1>; 369 interrupt-map-mask = <0 3>; 370 interrupt-map = <0 0 &gic 0 36 4>, 371 <0 1 &gic 0 37 4>, 372 <0 2 &gic 0 38 4>, 373 <0 3 &gic 0 39 4>; 374 }; 375}; 376