1 /*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/pm.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/cdev.h>
34 #include <linux/slab.h>
35 #include <linux/clk.h>
36 #include <linux/regulator/consumer.h>
37
38 #include <sound/tlv320aic32x4.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/soc.h>
43 #include <sound/soc-dapm.h>
44 #include <sound/initval.h>
45 #include <sound/tlv.h>
46
47 #include "tlv320aic32x4.h"
48
49 struct aic32x4_rate_divs {
50 u32 mclk;
51 u32 rate;
52 u8 p_val;
53 u8 pll_j;
54 u16 pll_d;
55 u16 dosr;
56 u8 ndac;
57 u8 mdac;
58 u8 aosr;
59 u8 nadc;
60 u8 madc;
61 u8 blck_N;
62 };
63
64 struct aic32x4_priv {
65 struct regmap *regmap;
66 u32 sysclk;
67 u32 power_cfg;
68 u32 micpga_routing;
69 bool swapdacs;
70 int rstn_gpio;
71 struct clk *mclk;
72
73 struct regulator *supply_ldo;
74 struct regulator *supply_iov;
75 struct regulator *supply_dv;
76 struct regulator *supply_av;
77
78 struct aic32x4_setup_data *setup;
79 struct device *dev;
80 };
81
aic32x4_get_mfp1_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)82 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
83 struct snd_ctl_elem_value *ucontrol)
84 {
85 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
86 u8 val;
87
88 val = snd_soc_component_read32(component, AIC32X4_DINCTL);
89
90 ucontrol->value.integer.value[0] = (val & 0x01);
91
92 return 0;
93 };
94
aic32x4_set_mfp2_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)95 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
96 struct snd_ctl_elem_value *ucontrol)
97 {
98 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
99 u8 val;
100 u8 gpio_check;
101
102 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL);
103 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
104 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
105 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
106 __func__);
107 return -EINVAL;
108 }
109
110 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
111 return 0;
112
113 if (ucontrol->value.integer.value[0])
114 val |= ucontrol->value.integer.value[0];
115 else
116 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
117
118 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
119
120 return 0;
121 };
122
aic32x4_get_mfp3_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)123 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
124 struct snd_ctl_elem_value *ucontrol)
125 {
126 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
127 u8 val;
128
129 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL);
130
131 ucontrol->value.integer.value[0] = (val & 0x01);
132
133 return 0;
134 };
135
aic32x4_set_mfp4_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)136 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
137 struct snd_ctl_elem_value *ucontrol)
138 {
139 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
140 u8 val;
141 u8 gpio_check;
142
143 val = snd_soc_component_read32(component, AIC32X4_MISOCTL);
144 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
145 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
146 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
147 __func__);
148 return -EINVAL;
149 }
150
151 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
152 return 0;
153
154 if (ucontrol->value.integer.value[0])
155 val |= ucontrol->value.integer.value[0];
156 else
157 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
158
159 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
160
161 return 0;
162 };
163
aic32x4_get_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)164 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
165 struct snd_ctl_elem_value *ucontrol)
166 {
167 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
168 u8 val;
169
170 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
171 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
172
173 return 0;
174 };
175
aic32x4_set_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)176 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
177 struct snd_ctl_elem_value *ucontrol)
178 {
179 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
180 u8 val;
181 u8 gpio_check;
182
183 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
184 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
185 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
186 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
187 __func__);
188 return -EINVAL;
189 }
190
191 if (ucontrol->value.integer.value[0] == (val & 0x1))
192 return 0;
193
194 if (ucontrol->value.integer.value[0])
195 val |= ucontrol->value.integer.value[0];
196 else
197 val &= 0xfe;
198
199 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
200
201 return 0;
202 };
203
204 static const struct snd_kcontrol_new aic32x4_mfp1[] = {
205 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
206 };
207
208 static const struct snd_kcontrol_new aic32x4_mfp2[] = {
209 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
210 };
211
212 static const struct snd_kcontrol_new aic32x4_mfp3[] = {
213 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
214 };
215
216 static const struct snd_kcontrol_new aic32x4_mfp4[] = {
217 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
218 };
219
220 static const struct snd_kcontrol_new aic32x4_mfp5[] = {
221 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
222 aic32x4_set_mfp5_gpio),
223 };
224
225 /* 0dB min, 0.5dB steps */
226 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
227 /* -63.5dB min, 0.5dB steps */
228 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
229 /* -6dB min, 1dB steps */
230 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
231 /* -12dB min, 0.5dB steps */
232 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
233
234 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
235 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
236 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
237 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
238 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
239 tlv_driver_gain),
240 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
241 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
242 tlv_driver_gain),
243 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
244 AIC32X4_HPRGAIN, 6, 0x01, 1),
245 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
246 AIC32X4_LORGAIN, 6, 0x01, 1),
247 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
248 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
249
250 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
251 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
252
253 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
254 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
255 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
256 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
257
258 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
259
260 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
261 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
262 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
263 4, 0x07, 0),
264 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
265 0, 0x03, 0),
266 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
267 6, 0x03, 0),
268 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
269 1, 0x1F, 0),
270 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
271 0, 0x7F, 0),
272 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
273 3, 0x1F, 0),
274 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
275 3, 0x1F, 0),
276 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
277 0, 0x1F, 0),
278 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
279 0, 0x0F, 0),
280 };
281
282 static const struct aic32x4_rate_divs aic32x4_divs[] = {
283 /* 8k rate */
284 {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
285 {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
286 {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
287 /* 11.025k rate */
288 {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
289 {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
290 /* 16k rate */
291 {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
292 {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
293 {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
294 /* 22.05k rate */
295 {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
296 {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
297 {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
298 /* 32k rate */
299 {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
300 {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
301 /* 44.1k rate */
302 {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
303 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
304 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
305 /* 48k rate */
306 {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
307 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
308 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
309
310 /* 96k rate */
311 {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
312 };
313
314 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
315 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
316 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
317 };
318
319 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
320 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
321 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
322 };
323
324 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
325 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
326 };
327
328 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
329 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
330 };
331
332 static const char * const resistor_text[] = {
333 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
334 };
335
336 /* Left mixer pins */
337 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
338 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
339 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
340 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
341
342 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
343 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
344 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
345
346 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
347 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
348 };
349 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
350 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
351 };
352 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
353 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
354 };
355 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
356 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
357 };
358 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
359 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
360 };
361 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
362 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
363 };
364 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
365 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
366 };
367
368 /* Right mixer pins */
369 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
370 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
371 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
372 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
373 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
374 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
375 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
376
377 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
378 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
379 };
380 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
381 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
382 };
383 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
384 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
385 };
386 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
387 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
388 };
389 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
390 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
391 };
392 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
393 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
394 };
395 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
396 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
397 };
398
399 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
400 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
401 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
402 &hpl_output_mixer_controls[0],
403 ARRAY_SIZE(hpl_output_mixer_controls)),
404 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
405
406 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
407 &lol_output_mixer_controls[0],
408 ARRAY_SIZE(lol_output_mixer_controls)),
409 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
410
411 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
412 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
413 &hpr_output_mixer_controls[0],
414 ARRAY_SIZE(hpr_output_mixer_controls)),
415 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
416 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
417 &lor_output_mixer_controls[0],
418 ARRAY_SIZE(lor_output_mixer_controls)),
419 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
420
421 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
422 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
423 in1r_to_rmixer_controls),
424 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
425 in2r_to_rmixer_controls),
426 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
427 in3r_to_rmixer_controls),
428 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
429 in2l_to_rmixer_controls),
430 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
431 cmr_to_rmixer_controls),
432 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
433 in1l_to_rmixer_controls),
434 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
435 in3l_to_rmixer_controls),
436
437 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
438 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
439 in1l_to_lmixer_controls),
440 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
441 in2l_to_lmixer_controls),
442 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
443 in3l_to_lmixer_controls),
444 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
445 in1r_to_lmixer_controls),
446 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
447 cml_to_lmixer_controls),
448 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
449 in2r_to_lmixer_controls),
450 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
451 in3r_to_lmixer_controls),
452
453 SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
454
455 SND_SOC_DAPM_OUTPUT("HPL"),
456 SND_SOC_DAPM_OUTPUT("HPR"),
457 SND_SOC_DAPM_OUTPUT("LOL"),
458 SND_SOC_DAPM_OUTPUT("LOR"),
459 SND_SOC_DAPM_INPUT("IN1_L"),
460 SND_SOC_DAPM_INPUT("IN1_R"),
461 SND_SOC_DAPM_INPUT("IN2_L"),
462 SND_SOC_DAPM_INPUT("IN2_R"),
463 SND_SOC_DAPM_INPUT("IN3_L"),
464 SND_SOC_DAPM_INPUT("IN3_R"),
465 SND_SOC_DAPM_INPUT("CM_L"),
466 SND_SOC_DAPM_INPUT("CM_R"),
467 };
468
469 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
470 /* Left Output */
471 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
472 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
473
474 {"HPL Power", NULL, "HPL Output Mixer"},
475 {"HPL", NULL, "HPL Power"},
476
477 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
478
479 {"LOL Power", NULL, "LOL Output Mixer"},
480 {"LOL", NULL, "LOL Power"},
481
482 /* Right Output */
483 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
484 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
485
486 {"HPR Power", NULL, "HPR Output Mixer"},
487 {"HPR", NULL, "HPR Power"},
488
489 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
490
491 {"LOR Power", NULL, "LOR Output Mixer"},
492 {"LOR", NULL, "LOR Power"},
493
494 /* Right Input */
495 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
496 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
497 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
498 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
499
500 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
501 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
502 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
503 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
504
505 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
506 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
507 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
508 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
509
510 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
511 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
512 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
513 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
514
515 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
516 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
517 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
518 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
519
520 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
521 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
522 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
523 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
524
525 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
526 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
527 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
528 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
529
530 /* Left Input */
531 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
532 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
533 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
534 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
535
536 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
537 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
538 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
539 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
540
541 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
542 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
543 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
544 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
545
546 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
547 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
548 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
549 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
550
551 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
552 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
553 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
554 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
555
556 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
557 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
558 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
559 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
560
561 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
562 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
563 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
564 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
565 };
566
567 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
568 {
569 .selector_reg = 0,
570 .selector_mask = 0xff,
571 .window_start = 0,
572 .window_len = 128,
573 .range_min = 0,
574 .range_max = AIC32X4_RMICPGAVOL,
575 },
576 };
577
578 const struct regmap_config aic32x4_regmap_config = {
579 .max_register = AIC32X4_RMICPGAVOL,
580 .ranges = aic32x4_regmap_pages,
581 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
582 };
583 EXPORT_SYMBOL(aic32x4_regmap_config);
584
aic32x4_get_divs(int mclk,int rate)585 static inline int aic32x4_get_divs(int mclk, int rate)
586 {
587 int i;
588
589 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
590 if ((aic32x4_divs[i].rate == rate)
591 && (aic32x4_divs[i].mclk == mclk)) {
592 return i;
593 }
594 }
595 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
596 return -EINVAL;
597 }
598
aic32x4_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)599 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
600 int clk_id, unsigned int freq, int dir)
601 {
602 struct snd_soc_component *component = codec_dai->component;
603 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
604
605 switch (freq) {
606 case 12000000:
607 case 24000000:
608 case 25000000:
609 aic32x4->sysclk = freq;
610 return 0;
611 }
612 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
613 return -EINVAL;
614 }
615
aic32x4_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)616 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
617 {
618 struct snd_soc_component *component = codec_dai->component;
619 u8 iface_reg_1 = 0;
620 u8 iface_reg_2 = 0;
621 u8 iface_reg_3 = 0;
622
623 /* set master/slave audio interface */
624 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
625 case SND_SOC_DAIFMT_CBM_CFM:
626 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
627 break;
628 case SND_SOC_DAIFMT_CBS_CFS:
629 break;
630 default:
631 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
632 return -EINVAL;
633 }
634
635 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
636 case SND_SOC_DAIFMT_I2S:
637 break;
638 case SND_SOC_DAIFMT_DSP_A:
639 iface_reg_1 |= (AIC32X4_DSP_MODE <<
640 AIC32X4_IFACE1_DATATYPE_SHIFT);
641 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
642 iface_reg_2 = 0x01; /* add offset 1 */
643 break;
644 case SND_SOC_DAIFMT_DSP_B:
645 iface_reg_1 |= (AIC32X4_DSP_MODE <<
646 AIC32X4_IFACE1_DATATYPE_SHIFT);
647 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
648 break;
649 case SND_SOC_DAIFMT_RIGHT_J:
650 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
651 AIC32X4_IFACE1_DATATYPE_SHIFT);
652 break;
653 case SND_SOC_DAIFMT_LEFT_J:
654 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
655 AIC32X4_IFACE1_DATATYPE_SHIFT);
656 break;
657 default:
658 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
659 return -EINVAL;
660 }
661
662 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
663 AIC32X4_IFACE1_DATATYPE_MASK |
664 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
665 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
666 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
667 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
668 AIC32X4_BCLKINV_MASK, iface_reg_3);
669
670 return 0;
671 }
672
aic32x4_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)673 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
674 struct snd_pcm_hw_params *params,
675 struct snd_soc_dai *dai)
676 {
677 struct snd_soc_component *component = dai->component;
678 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
679 u8 iface1_reg = 0;
680 u8 dacsetup_reg = 0;
681 int i;
682
683 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
684 if (i < 0) {
685 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
686 return i;
687 }
688
689 /* MCLK as PLL_CLKIN */
690 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
691 AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
692 /* PLL as CODEC_CLKIN */
693 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
694 AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
695 /* DAC_MOD_CLK as BDIV_CLKIN */
696 snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
697 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
698
699 /* We will fix R value to 1 and will make P & J=K.D as variable */
700 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
701
702 /* PLL P value */
703 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
704 aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
705
706 /* PLL J value */
707 snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
708
709 /* PLL D value */
710 snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
711 snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
712
713 /* NDAC divider value */
714 snd_soc_component_update_bits(component, AIC32X4_NDAC,
715 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
716
717 /* MDAC divider value */
718 snd_soc_component_update_bits(component, AIC32X4_MDAC,
719 AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
720
721 /* DOSR MSB & LSB values */
722 snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
723 snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
724
725 /* NADC divider value */
726 snd_soc_component_update_bits(component, AIC32X4_NADC,
727 AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
728
729 /* MADC divider value */
730 snd_soc_component_update_bits(component, AIC32X4_MADC,
731 AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
732
733 /* AOSR value */
734 snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
735
736 /* BCLK N divider */
737 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
738 AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
739
740 switch (params_width(params)) {
741 case 16:
742 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
743 AIC32X4_IFACE1_DATALEN_SHIFT);
744 break;
745 case 20:
746 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
747 AIC32X4_IFACE1_DATALEN_SHIFT);
748 break;
749 case 24:
750 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
751 AIC32X4_IFACE1_DATALEN_SHIFT);
752 break;
753 case 32:
754 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
755 AIC32X4_IFACE1_DATALEN_SHIFT);
756 break;
757 }
758 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
759 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
760
761 if (params_channels(params) == 1) {
762 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
763 } else {
764 if (aic32x4->swapdacs)
765 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
766 else
767 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
768 }
769 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
770 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
771
772 return 0;
773 }
774
aic32x4_mute(struct snd_soc_dai * dai,int mute)775 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
776 {
777 struct snd_soc_component *component = dai->component;
778
779 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
780 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
781
782 return 0;
783 }
784
aic32x4_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)785 static int aic32x4_set_bias_level(struct snd_soc_component *component,
786 enum snd_soc_bias_level level)
787 {
788 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
789 int ret;
790
791 switch (level) {
792 case SND_SOC_BIAS_ON:
793 /* Switch on master clock */
794 ret = clk_prepare_enable(aic32x4->mclk);
795 if (ret) {
796 dev_err(component->dev, "Failed to enable master clock\n");
797 return ret;
798 }
799
800 /* Switch on PLL */
801 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
802 AIC32X4_PLLEN, AIC32X4_PLLEN);
803
804 /* Switch on NDAC Divider */
805 snd_soc_component_update_bits(component, AIC32X4_NDAC,
806 AIC32X4_NDACEN, AIC32X4_NDACEN);
807
808 /* Switch on MDAC Divider */
809 snd_soc_component_update_bits(component, AIC32X4_MDAC,
810 AIC32X4_MDACEN, AIC32X4_MDACEN);
811
812 /* Switch on NADC Divider */
813 snd_soc_component_update_bits(component, AIC32X4_NADC,
814 AIC32X4_NADCEN, AIC32X4_NADCEN);
815
816 /* Switch on MADC Divider */
817 snd_soc_component_update_bits(component, AIC32X4_MADC,
818 AIC32X4_MADCEN, AIC32X4_MADCEN);
819
820 /* Switch on BCLK_N Divider */
821 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
822 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
823 break;
824 case SND_SOC_BIAS_PREPARE:
825 break;
826 case SND_SOC_BIAS_STANDBY:
827 /* Initial cold start */
828 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
829 break;
830
831 /* Switch off BCLK_N Divider */
832 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
833 AIC32X4_BCLKEN, 0);
834
835 /* Switch off MADC Divider */
836 snd_soc_component_update_bits(component, AIC32X4_MADC,
837 AIC32X4_MADCEN, 0);
838
839 /* Switch off NADC Divider */
840 snd_soc_component_update_bits(component, AIC32X4_NADC,
841 AIC32X4_NADCEN, 0);
842
843 /* Switch off MDAC Divider */
844 snd_soc_component_update_bits(component, AIC32X4_MDAC,
845 AIC32X4_MDACEN, 0);
846
847 /* Switch off NDAC Divider */
848 snd_soc_component_update_bits(component, AIC32X4_NDAC,
849 AIC32X4_NDACEN, 0);
850
851 /* Switch off PLL */
852 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
853 AIC32X4_PLLEN, 0);
854
855 /* Switch off master clock */
856 clk_disable_unprepare(aic32x4->mclk);
857 break;
858 case SND_SOC_BIAS_OFF:
859 break;
860 }
861 return 0;
862 }
863
864 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
865 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
866 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
867
868 static const struct snd_soc_dai_ops aic32x4_ops = {
869 .hw_params = aic32x4_hw_params,
870 .digital_mute = aic32x4_mute,
871 .set_fmt = aic32x4_set_dai_fmt,
872 .set_sysclk = aic32x4_set_dai_sysclk,
873 };
874
875 static struct snd_soc_dai_driver aic32x4_dai = {
876 .name = "tlv320aic32x4-hifi",
877 .playback = {
878 .stream_name = "Playback",
879 .channels_min = 1,
880 .channels_max = 2,
881 .rates = AIC32X4_RATES,
882 .formats = AIC32X4_FORMATS,},
883 .capture = {
884 .stream_name = "Capture",
885 .channels_min = 1,
886 .channels_max = 2,
887 .rates = AIC32X4_RATES,
888 .formats = AIC32X4_FORMATS,},
889 .ops = &aic32x4_ops,
890 .symmetric_rates = 1,
891 };
892
aic32x4_setup_gpios(struct snd_soc_component * component)893 static void aic32x4_setup_gpios(struct snd_soc_component *component)
894 {
895 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
896
897 /* setup GPIO functions */
898 /* MFP1 */
899 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
900 snd_soc_component_write(component, AIC32X4_DINCTL,
901 aic32x4->setup->gpio_func[0]);
902 snd_soc_add_component_controls(component, aic32x4_mfp1,
903 ARRAY_SIZE(aic32x4_mfp1));
904 }
905
906 /* MFP2 */
907 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
908 snd_soc_component_write(component, AIC32X4_DOUTCTL,
909 aic32x4->setup->gpio_func[1]);
910 snd_soc_add_component_controls(component, aic32x4_mfp2,
911 ARRAY_SIZE(aic32x4_mfp2));
912 }
913
914 /* MFP3 */
915 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
916 snd_soc_component_write(component, AIC32X4_SCLKCTL,
917 aic32x4->setup->gpio_func[2]);
918 snd_soc_add_component_controls(component, aic32x4_mfp3,
919 ARRAY_SIZE(aic32x4_mfp3));
920 }
921
922 /* MFP4 */
923 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
924 snd_soc_component_write(component, AIC32X4_MISOCTL,
925 aic32x4->setup->gpio_func[3]);
926 snd_soc_add_component_controls(component, aic32x4_mfp4,
927 ARRAY_SIZE(aic32x4_mfp4));
928 }
929
930 /* MFP5 */
931 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
932 snd_soc_component_write(component, AIC32X4_GPIOCTL,
933 aic32x4->setup->gpio_func[4]);
934 snd_soc_add_component_controls(component, aic32x4_mfp5,
935 ARRAY_SIZE(aic32x4_mfp5));
936 }
937 }
938
aic32x4_component_probe(struct snd_soc_component * component)939 static int aic32x4_component_probe(struct snd_soc_component *component)
940 {
941 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
942 u32 tmp_reg;
943
944 if (gpio_is_valid(aic32x4->rstn_gpio)) {
945 ndelay(10);
946 gpio_set_value(aic32x4->rstn_gpio, 1);
947 }
948
949 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
950
951 if (aic32x4->setup)
952 aic32x4_setup_gpios(component);
953
954 /* Power platform configuration */
955 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
956 snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
957 AIC32X4_MICBIAS_2075V);
958 }
959 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
960 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
961
962 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
963 AIC32X4_LDOCTLEN : 0;
964 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
965
966 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE);
967 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
968 tmp_reg |= AIC32X4_LDOIN_18_36;
969 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
970 tmp_reg |= AIC32X4_LDOIN2HP;
971 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
972
973 /* Mic PGA routing */
974 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
975 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
976 AIC32X4_LMICPGANIN_IN2R_10K);
977 else
978 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
979 AIC32X4_LMICPGANIN_CM1L_10K);
980 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
981 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
982 AIC32X4_RMICPGANIN_IN1L_10K);
983 else
984 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
985 AIC32X4_RMICPGANIN_CM1R_10K);
986
987 /*
988 * Workaround: for an unknown reason, the ADC needs to be powered up
989 * and down for the first capture to work properly. It seems related to
990 * a HW BUG or some kind of behavior not documented in the datasheet.
991 */
992 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
993 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
994 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
995 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
996
997 return 0;
998 }
999
1000 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1001 .probe = aic32x4_component_probe,
1002 .set_bias_level = aic32x4_set_bias_level,
1003 .controls = aic32x4_snd_controls,
1004 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1005 .dapm_widgets = aic32x4_dapm_widgets,
1006 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1007 .dapm_routes = aic32x4_dapm_routes,
1008 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1009 .suspend_bias_off = 1,
1010 .idle_bias_on = 1,
1011 .use_pmdown_time = 1,
1012 .endianness = 1,
1013 .non_legacy_dai_naming = 1,
1014 };
1015
aic32x4_parse_dt(struct aic32x4_priv * aic32x4,struct device_node * np)1016 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1017 struct device_node *np)
1018 {
1019 struct aic32x4_setup_data *aic32x4_setup;
1020
1021 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1022 GFP_KERNEL);
1023 if (!aic32x4_setup)
1024 return -ENOMEM;
1025
1026 aic32x4->swapdacs = false;
1027 aic32x4->micpga_routing = 0;
1028 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1029
1030 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1031 aic32x4_setup->gpio_func, 5) >= 0)
1032 aic32x4->setup = aic32x4_setup;
1033 return 0;
1034 }
1035
aic32x4_disable_regulators(struct aic32x4_priv * aic32x4)1036 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1037 {
1038 regulator_disable(aic32x4->supply_iov);
1039
1040 if (!IS_ERR(aic32x4->supply_ldo))
1041 regulator_disable(aic32x4->supply_ldo);
1042
1043 if (!IS_ERR(aic32x4->supply_dv))
1044 regulator_disable(aic32x4->supply_dv);
1045
1046 if (!IS_ERR(aic32x4->supply_av))
1047 regulator_disable(aic32x4->supply_av);
1048 }
1049
aic32x4_setup_regulators(struct device * dev,struct aic32x4_priv * aic32x4)1050 static int aic32x4_setup_regulators(struct device *dev,
1051 struct aic32x4_priv *aic32x4)
1052 {
1053 int ret = 0;
1054
1055 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1056 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1057 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1058 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1059
1060 /* Check if the regulator requirements are fulfilled */
1061
1062 if (IS_ERR(aic32x4->supply_iov)) {
1063 dev_err(dev, "Missing supply 'iov'\n");
1064 return PTR_ERR(aic32x4->supply_iov);
1065 }
1066
1067 if (IS_ERR(aic32x4->supply_ldo)) {
1068 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1069 return -EPROBE_DEFER;
1070
1071 if (IS_ERR(aic32x4->supply_dv)) {
1072 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1073 return PTR_ERR(aic32x4->supply_dv);
1074 }
1075 if (IS_ERR(aic32x4->supply_av)) {
1076 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1077 return PTR_ERR(aic32x4->supply_av);
1078 }
1079 } else {
1080 if (IS_ERR(aic32x4->supply_dv) &&
1081 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1082 return -EPROBE_DEFER;
1083 if (IS_ERR(aic32x4->supply_av) &&
1084 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1085 return -EPROBE_DEFER;
1086 }
1087
1088 ret = regulator_enable(aic32x4->supply_iov);
1089 if (ret) {
1090 dev_err(dev, "Failed to enable regulator iov\n");
1091 return ret;
1092 }
1093
1094 if (!IS_ERR(aic32x4->supply_ldo)) {
1095 ret = regulator_enable(aic32x4->supply_ldo);
1096 if (ret) {
1097 dev_err(dev, "Failed to enable regulator ldo\n");
1098 goto error_ldo;
1099 }
1100 }
1101
1102 if (!IS_ERR(aic32x4->supply_dv)) {
1103 ret = regulator_enable(aic32x4->supply_dv);
1104 if (ret) {
1105 dev_err(dev, "Failed to enable regulator dv\n");
1106 goto error_dv;
1107 }
1108 }
1109
1110 if (!IS_ERR(aic32x4->supply_av)) {
1111 ret = regulator_enable(aic32x4->supply_av);
1112 if (ret) {
1113 dev_err(dev, "Failed to enable regulator av\n");
1114 goto error_av;
1115 }
1116 }
1117
1118 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1119 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1120
1121 return 0;
1122
1123 error_av:
1124 if (!IS_ERR(aic32x4->supply_dv))
1125 regulator_disable(aic32x4->supply_dv);
1126
1127 error_dv:
1128 if (!IS_ERR(aic32x4->supply_ldo))
1129 regulator_disable(aic32x4->supply_ldo);
1130
1131 error_ldo:
1132 regulator_disable(aic32x4->supply_iov);
1133 return ret;
1134 }
1135
aic32x4_probe(struct device * dev,struct regmap * regmap)1136 int aic32x4_probe(struct device *dev, struct regmap *regmap)
1137 {
1138 struct aic32x4_priv *aic32x4;
1139 struct aic32x4_pdata *pdata = dev->platform_data;
1140 struct device_node *np = dev->of_node;
1141 int ret;
1142
1143 if (IS_ERR(regmap))
1144 return PTR_ERR(regmap);
1145
1146 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1147 GFP_KERNEL);
1148 if (aic32x4 == NULL)
1149 return -ENOMEM;
1150
1151 aic32x4->dev = dev;
1152 dev_set_drvdata(dev, aic32x4);
1153
1154 if (pdata) {
1155 aic32x4->power_cfg = pdata->power_cfg;
1156 aic32x4->swapdacs = pdata->swapdacs;
1157 aic32x4->micpga_routing = pdata->micpga_routing;
1158 aic32x4->rstn_gpio = pdata->rstn_gpio;
1159 } else if (np) {
1160 ret = aic32x4_parse_dt(aic32x4, np);
1161 if (ret) {
1162 dev_err(dev, "Failed to parse DT node\n");
1163 return ret;
1164 }
1165 } else {
1166 aic32x4->power_cfg = 0;
1167 aic32x4->swapdacs = false;
1168 aic32x4->micpga_routing = 0;
1169 aic32x4->rstn_gpio = -1;
1170 }
1171
1172 aic32x4->mclk = devm_clk_get(dev, "mclk");
1173 if (IS_ERR(aic32x4->mclk)) {
1174 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
1175 return PTR_ERR(aic32x4->mclk);
1176 }
1177
1178 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1179 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1180 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1181 if (ret != 0)
1182 return ret;
1183 }
1184
1185 ret = aic32x4_setup_regulators(dev, aic32x4);
1186 if (ret) {
1187 dev_err(dev, "Failed to setup regulators\n");
1188 return ret;
1189 }
1190
1191 ret = devm_snd_soc_register_component(dev,
1192 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1193 if (ret) {
1194 dev_err(dev, "Failed to register component\n");
1195 aic32x4_disable_regulators(aic32x4);
1196 return ret;
1197 }
1198
1199 return 0;
1200 }
1201 EXPORT_SYMBOL(aic32x4_probe);
1202
aic32x4_remove(struct device * dev)1203 int aic32x4_remove(struct device *dev)
1204 {
1205 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1206
1207 aic32x4_disable_regulators(aic32x4);
1208
1209 return 0;
1210 }
1211 EXPORT_SYMBOL(aic32x4_remove);
1212
1213 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1214 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1215 MODULE_LICENSE("GPL");
1216