1 /*
2 * IMG parallel output controller driver
3 *
4 * Copyright (C) 2015 Imagination Technologies Ltd.
5 *
6 * Author: Damien Horsley <Damien.Horsley@imgtec.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21
22 #include <sound/core.h>
23 #include <sound/dmaengine_pcm.h>
24 #include <sound/initval.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28
29 #define IMG_PRL_OUT_TX_FIFO 0
30
31 #define IMG_PRL_OUT_CTL 0x4
32 #define IMG_PRL_OUT_CTL_CH_MASK BIT(4)
33 #define IMG_PRL_OUT_CTL_PACKH_MASK BIT(3)
34 #define IMG_PRL_OUT_CTL_EDGE_MASK BIT(2)
35 #define IMG_PRL_OUT_CTL_ME_MASK BIT(1)
36 #define IMG_PRL_OUT_CTL_SRST_MASK BIT(0)
37
38 struct img_prl_out {
39 void __iomem *base;
40 struct clk *clk_sys;
41 struct clk *clk_ref;
42 struct snd_dmaengine_dai_dma_data dma_data;
43 struct device *dev;
44 struct reset_control *rst;
45 };
46
img_prl_out_suspend(struct device * dev)47 static int img_prl_out_suspend(struct device *dev)
48 {
49 struct img_prl_out *prl = dev_get_drvdata(dev);
50
51 clk_disable_unprepare(prl->clk_ref);
52
53 return 0;
54 }
55
img_prl_out_resume(struct device * dev)56 static int img_prl_out_resume(struct device *dev)
57 {
58 struct img_prl_out *prl = dev_get_drvdata(dev);
59 int ret;
60
61 ret = clk_prepare_enable(prl->clk_ref);
62 if (ret) {
63 dev_err(dev, "clk_enable failed: %d\n", ret);
64 return ret;
65 }
66
67 return 0;
68 }
69
img_prl_out_writel(struct img_prl_out * prl,u32 val,u32 reg)70 static inline void img_prl_out_writel(struct img_prl_out *prl,
71 u32 val, u32 reg)
72 {
73 writel(val, prl->base + reg);
74 }
75
img_prl_out_readl(struct img_prl_out * prl,u32 reg)76 static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg)
77 {
78 return readl(prl->base + reg);
79 }
80
img_prl_out_reset(struct img_prl_out * prl)81 static void img_prl_out_reset(struct img_prl_out *prl)
82 {
83 u32 ctl;
84
85 ctl = img_prl_out_readl(prl, IMG_PRL_OUT_CTL) &
86 ~IMG_PRL_OUT_CTL_ME_MASK;
87
88 reset_control_assert(prl->rst);
89 reset_control_deassert(prl->rst);
90
91 img_prl_out_writel(prl, ctl, IMG_PRL_OUT_CTL);
92 }
93
img_prl_out_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)94 static int img_prl_out_trigger(struct snd_pcm_substream *substream, int cmd,
95 struct snd_soc_dai *dai)
96 {
97 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
98 u32 reg;
99
100 switch (cmd) {
101 case SNDRV_PCM_TRIGGER_START:
102 case SNDRV_PCM_TRIGGER_RESUME:
103 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
104 reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
105 reg |= IMG_PRL_OUT_CTL_ME_MASK;
106 img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
107 break;
108 case SNDRV_PCM_TRIGGER_STOP:
109 case SNDRV_PCM_TRIGGER_SUSPEND:
110 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
111 img_prl_out_reset(prl);
112 break;
113 default:
114 return -EINVAL;
115 }
116
117 return 0;
118 }
119
img_prl_out_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)120 static int img_prl_out_hw_params(struct snd_pcm_substream *substream,
121 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
122 {
123 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
124 unsigned int rate, channels;
125 u32 reg, control_set = 0;
126
127 rate = params_rate(params);
128 channels = params_channels(params);
129
130 switch (params_format(params)) {
131 case SNDRV_PCM_FORMAT_S32_LE:
132 control_set |= IMG_PRL_OUT_CTL_PACKH_MASK;
133 break;
134 case SNDRV_PCM_FORMAT_S24_LE:
135 break;
136 default:
137 return -EINVAL;
138 }
139
140 if (channels != 2)
141 return -EINVAL;
142
143 clk_set_rate(prl->clk_ref, rate * 256);
144
145 reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
146 reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set;
147 img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
148
149 return 0;
150 }
151
img_prl_out_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)152 static int img_prl_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
153 {
154 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
155 u32 reg, control_set = 0;
156 int ret;
157
158 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
159 case SND_SOC_DAIFMT_NB_NF:
160 break;
161 case SND_SOC_DAIFMT_NB_IF:
162 control_set |= IMG_PRL_OUT_CTL_EDGE_MASK;
163 break;
164 default:
165 return -EINVAL;
166 }
167
168 ret = pm_runtime_get_sync(prl->dev);
169 if (ret < 0) {
170 pm_runtime_put_noidle(prl->dev);
171 return ret;
172 }
173
174 reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
175 reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set;
176 img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
177 pm_runtime_put(prl->dev);
178
179 return 0;
180 }
181
182 static const struct snd_soc_dai_ops img_prl_out_dai_ops = {
183 .trigger = img_prl_out_trigger,
184 .hw_params = img_prl_out_hw_params,
185 .set_fmt = img_prl_out_set_fmt
186 };
187
img_prl_out_dai_probe(struct snd_soc_dai * dai)188 static int img_prl_out_dai_probe(struct snd_soc_dai *dai)
189 {
190 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
191
192 snd_soc_dai_init_dma_data(dai, &prl->dma_data, NULL);
193
194 return 0;
195 }
196
197 static struct snd_soc_dai_driver img_prl_out_dai = {
198 .probe = img_prl_out_dai_probe,
199 .playback = {
200 .channels_min = 2,
201 .channels_max = 2,
202 .rates = SNDRV_PCM_RATE_8000_192000,
203 .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE
204 },
205 .ops = &img_prl_out_dai_ops
206 };
207
208 static const struct snd_soc_component_driver img_prl_out_component = {
209 .name = "img-prl-out"
210 };
211
img_prl_out_probe(struct platform_device * pdev)212 static int img_prl_out_probe(struct platform_device *pdev)
213 {
214 struct img_prl_out *prl;
215 struct resource *res;
216 void __iomem *base;
217 int ret;
218 struct device *dev = &pdev->dev;
219
220 prl = devm_kzalloc(&pdev->dev, sizeof(*prl), GFP_KERNEL);
221 if (!prl)
222 return -ENOMEM;
223
224 platform_set_drvdata(pdev, prl);
225
226 prl->dev = &pdev->dev;
227
228 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
229 base = devm_ioremap_resource(&pdev->dev, res);
230 if (IS_ERR(base))
231 return PTR_ERR(base);
232
233 prl->base = base;
234
235 prl->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
236 if (IS_ERR(prl->rst)) {
237 if (PTR_ERR(prl->rst) != -EPROBE_DEFER)
238 dev_err(&pdev->dev, "No top level reset found\n");
239 return PTR_ERR(prl->rst);
240 }
241
242 prl->clk_sys = devm_clk_get(&pdev->dev, "sys");
243 if (IS_ERR(prl->clk_sys)) {
244 if (PTR_ERR(prl->clk_sys) != -EPROBE_DEFER)
245 dev_err(dev, "Failed to acquire clock 'sys'\n");
246 return PTR_ERR(prl->clk_sys);
247 }
248
249 prl->clk_ref = devm_clk_get(&pdev->dev, "ref");
250 if (IS_ERR(prl->clk_ref)) {
251 if (PTR_ERR(prl->clk_ref) != -EPROBE_DEFER)
252 dev_err(dev, "Failed to acquire clock 'ref'\n");
253 return PTR_ERR(prl->clk_ref);
254 }
255
256 ret = clk_prepare_enable(prl->clk_sys);
257 if (ret)
258 return ret;
259
260 img_prl_out_writel(prl, IMG_PRL_OUT_CTL_EDGE_MASK, IMG_PRL_OUT_CTL);
261 img_prl_out_reset(prl);
262
263 pm_runtime_enable(&pdev->dev);
264 if (!pm_runtime_enabled(&pdev->dev)) {
265 ret = img_prl_out_resume(&pdev->dev);
266 if (ret)
267 goto err_pm_disable;
268 }
269
270 prl->dma_data.addr = res->start + IMG_PRL_OUT_TX_FIFO;
271 prl->dma_data.addr_width = 4;
272 prl->dma_data.maxburst = 4;
273
274 ret = devm_snd_soc_register_component(&pdev->dev,
275 &img_prl_out_component,
276 &img_prl_out_dai, 1);
277 if (ret)
278 goto err_suspend;
279
280 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
281 if (ret)
282 goto err_suspend;
283
284 return 0;
285
286 err_suspend:
287 if (!pm_runtime_status_suspended(&pdev->dev))
288 img_prl_out_suspend(&pdev->dev);
289 err_pm_disable:
290 pm_runtime_disable(&pdev->dev);
291 clk_disable_unprepare(prl->clk_sys);
292
293 return ret;
294 }
295
img_prl_out_dev_remove(struct platform_device * pdev)296 static int img_prl_out_dev_remove(struct platform_device *pdev)
297 {
298 struct img_prl_out *prl = platform_get_drvdata(pdev);
299
300 pm_runtime_disable(&pdev->dev);
301 if (!pm_runtime_status_suspended(&pdev->dev))
302 img_prl_out_suspend(&pdev->dev);
303
304 clk_disable_unprepare(prl->clk_sys);
305
306 return 0;
307 }
308
309 static const struct of_device_id img_prl_out_of_match[] = {
310 { .compatible = "img,parallel-out" },
311 {}
312 };
313 MODULE_DEVICE_TABLE(of, img_prl_out_of_match);
314
315 static const struct dev_pm_ops img_prl_out_pm_ops = {
316 SET_RUNTIME_PM_OPS(img_prl_out_suspend,
317 img_prl_out_resume, NULL)
318 };
319
320 static struct platform_driver img_prl_out_driver = {
321 .driver = {
322 .name = "img-parallel-out",
323 .of_match_table = img_prl_out_of_match,
324 .pm = &img_prl_out_pm_ops
325 },
326 .probe = img_prl_out_probe,
327 .remove = img_prl_out_dev_remove
328 };
329 module_platform_driver(img_prl_out_driver);
330
331 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
332 MODULE_DESCRIPTION("IMG Parallel Output Driver");
333 MODULE_LICENSE("GPL v2");
334