1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #define pr_fmt(fmt) "GICv3: " fmt
8
9 #include <linux/acpi.h>
10 #include <linux/cpu.h>
11 #include <linux/cpu_pm.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/percpu.h>
19 #include <linux/refcount.h>
20 #include <linux/slab.h>
21
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
26
27 #include <asm/cputype.h>
28 #include <asm/exception.h>
29 #include <asm/smp_plat.h>
30 #include <asm/virt.h>
31
32 #include "irq-gic-common.h"
33
34 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
35
36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
37 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
38
39 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
40
41 struct redist_region {
42 void __iomem *redist_base;
43 phys_addr_t phys_base;
44 bool single_redist;
45 };
46
47 struct gic_chip_data {
48 struct fwnode_handle *fwnode;
49 void __iomem *dist_base;
50 struct redist_region *redist_regions;
51 struct rdists rdists;
52 struct irq_domain *domain;
53 u64 redist_stride;
54 u32 nr_redist_regions;
55 u64 flags;
56 bool has_rss;
57 unsigned int ppi_nr;
58 struct partition_desc **ppi_descs;
59 };
60
61 static struct gic_chip_data gic_data __read_mostly;
62 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
63
64 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
65 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
66 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
67
68 /*
69 * The behaviours of RPR and PMR registers differ depending on the value of
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
71 * distributor and redistributors depends on whether security is enabled in the
72 * GIC.
73 *
74 * When security is enabled, non-secure priority values from the (re)distributor
75 * are presented to the GIC CPUIF as follow:
76 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
77 *
78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
79 * EL1 are subject to a similar operation thus matching the priorities presented
80 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
81 * these values are unchanched by the GIC.
82 *
83 * see GICv3/GICv4 Architecture Specification (IHI0069D):
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
85 * priorities.
86 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
87 * interrupt.
88 */
89 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
90
91 /*
92 * Global static key controlling whether an update to PMR allowing more
93 * interrupts requires to be propagated to the redistributor (DSB SY).
94 * And this needs to be exported for modules to be able to enable
95 * interrupts...
96 */
97 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
98 EXPORT_SYMBOL(gic_pmr_sync);
99
100 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
101 EXPORT_SYMBOL(gic_nonsecure_priorities);
102
103 /*
104 * When the Non-secure world has access to group 0 interrupts (as a
105 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
106 * return the Distributor's view of the interrupt priority.
107 *
108 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
109 * written by software is moved to the Non-secure range by the Distributor.
110 *
111 * If both are true (which is when gic_nonsecure_priorities gets enabled),
112 * we need to shift down the priority programmed by software to match it
113 * against the value returned by ICC_RPR_EL1.
114 */
115 #define GICD_INT_RPR_PRI(priority) \
116 ({ \
117 u32 __priority = (priority); \
118 if (static_branch_unlikely(&gic_nonsecure_priorities)) \
119 __priority = 0x80 | (__priority >> 1); \
120 \
121 __priority; \
122 })
123
124 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
125 static refcount_t *ppi_nmi_refs;
126
127 static struct gic_kvm_info gic_v3_kvm_info;
128 static DEFINE_PER_CPU(bool, has_rss);
129
130 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
131 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
132 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
133 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
134
135 /* Our default, arbitrary priority value. Linux only uses one anyway. */
136 #define DEFAULT_PMR_VALUE 0xf0
137
138 enum gic_intid_range {
139 SGI_RANGE,
140 PPI_RANGE,
141 SPI_RANGE,
142 EPPI_RANGE,
143 ESPI_RANGE,
144 LPI_RANGE,
145 __INVALID_RANGE__
146 };
147
__get_intid_range(irq_hw_number_t hwirq)148 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
149 {
150 switch (hwirq) {
151 case 0 ... 15:
152 return SGI_RANGE;
153 case 16 ... 31:
154 return PPI_RANGE;
155 case 32 ... 1019:
156 return SPI_RANGE;
157 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
158 return EPPI_RANGE;
159 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
160 return ESPI_RANGE;
161 case 8192 ... GENMASK(23, 0):
162 return LPI_RANGE;
163 default:
164 return __INVALID_RANGE__;
165 }
166 }
167
get_intid_range(struct irq_data * d)168 static enum gic_intid_range get_intid_range(struct irq_data *d)
169 {
170 return __get_intid_range(d->hwirq);
171 }
172
gic_irq(struct irq_data * d)173 static inline unsigned int gic_irq(struct irq_data *d)
174 {
175 return d->hwirq;
176 }
177
gic_irq_in_rdist(struct irq_data * d)178 static inline bool gic_irq_in_rdist(struct irq_data *d)
179 {
180 switch (get_intid_range(d)) {
181 case SGI_RANGE:
182 case PPI_RANGE:
183 case EPPI_RANGE:
184 return true;
185 default:
186 return false;
187 }
188 }
189
gic_dist_base(struct irq_data * d)190 static inline void __iomem *gic_dist_base(struct irq_data *d)
191 {
192 switch (get_intid_range(d)) {
193 case SGI_RANGE:
194 case PPI_RANGE:
195 case EPPI_RANGE:
196 /* SGI+PPI -> SGI_base for this CPU */
197 return gic_data_rdist_sgi_base();
198
199 case SPI_RANGE:
200 case ESPI_RANGE:
201 /* SPI -> dist_base */
202 return gic_data.dist_base;
203
204 default:
205 return NULL;
206 }
207 }
208
gic_do_wait_for_rwp(void __iomem * base)209 static void gic_do_wait_for_rwp(void __iomem *base)
210 {
211 u32 count = 1000000; /* 1s! */
212
213 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
214 count--;
215 if (!count) {
216 pr_err_ratelimited("RWP timeout, gone fishing\n");
217 return;
218 }
219 cpu_relax();
220 udelay(1);
221 }
222 }
223
224 /* Wait for completion of a distributor change */
gic_dist_wait_for_rwp(void)225 static void gic_dist_wait_for_rwp(void)
226 {
227 gic_do_wait_for_rwp(gic_data.dist_base);
228 }
229
230 /* Wait for completion of a redistributor change */
gic_redist_wait_for_rwp(void)231 static void gic_redist_wait_for_rwp(void)
232 {
233 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
234 }
235
236 #ifdef CONFIG_ARM64
237
gic_read_iar(void)238 static u64 __maybe_unused gic_read_iar(void)
239 {
240 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
241 return gic_read_iar_cavium_thunderx();
242 else
243 return gic_read_iar_common();
244 }
245 #endif
246
gic_enable_redist(bool enable)247 static void gic_enable_redist(bool enable)
248 {
249 void __iomem *rbase;
250 u32 count = 1000000; /* 1s! */
251 u32 val;
252
253 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
254 return;
255
256 rbase = gic_data_rdist_rd_base();
257
258 val = readl_relaxed(rbase + GICR_WAKER);
259 if (enable)
260 /* Wake up this CPU redistributor */
261 val &= ~GICR_WAKER_ProcessorSleep;
262 else
263 val |= GICR_WAKER_ProcessorSleep;
264 writel_relaxed(val, rbase + GICR_WAKER);
265
266 if (!enable) { /* Check that GICR_WAKER is writeable */
267 val = readl_relaxed(rbase + GICR_WAKER);
268 if (!(val & GICR_WAKER_ProcessorSleep))
269 return; /* No PM support in this redistributor */
270 }
271
272 while (--count) {
273 val = readl_relaxed(rbase + GICR_WAKER);
274 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
275 break;
276 cpu_relax();
277 udelay(1);
278 }
279 if (!count)
280 pr_err_ratelimited("redistributor failed to %s...\n",
281 enable ? "wakeup" : "sleep");
282 }
283
284 /*
285 * Routines to disable, enable, EOI and route interrupts
286 */
convert_offset_index(struct irq_data * d,u32 offset,u32 * index)287 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
288 {
289 switch (get_intid_range(d)) {
290 case SGI_RANGE:
291 case PPI_RANGE:
292 case SPI_RANGE:
293 *index = d->hwirq;
294 return offset;
295 case EPPI_RANGE:
296 /*
297 * Contrary to the ESPI range, the EPPI range is contiguous
298 * to the PPI range in the registers, so let's adjust the
299 * displacement accordingly. Consistency is overrated.
300 */
301 *index = d->hwirq - EPPI_BASE_INTID + 32;
302 return offset;
303 case ESPI_RANGE:
304 *index = d->hwirq - ESPI_BASE_INTID;
305 switch (offset) {
306 case GICD_ISENABLER:
307 return GICD_ISENABLERnE;
308 case GICD_ICENABLER:
309 return GICD_ICENABLERnE;
310 case GICD_ISPENDR:
311 return GICD_ISPENDRnE;
312 case GICD_ICPENDR:
313 return GICD_ICPENDRnE;
314 case GICD_ISACTIVER:
315 return GICD_ISACTIVERnE;
316 case GICD_ICACTIVER:
317 return GICD_ICACTIVERnE;
318 case GICD_IPRIORITYR:
319 return GICD_IPRIORITYRnE;
320 case GICD_ICFGR:
321 return GICD_ICFGRnE;
322 case GICD_IROUTER:
323 return GICD_IROUTERnE;
324 default:
325 break;
326 }
327 break;
328 default:
329 break;
330 }
331
332 WARN_ON(1);
333 *index = d->hwirq;
334 return offset;
335 }
336
gic_peek_irq(struct irq_data * d,u32 offset)337 static int gic_peek_irq(struct irq_data *d, u32 offset)
338 {
339 void __iomem *base;
340 u32 index, mask;
341
342 offset = convert_offset_index(d, offset, &index);
343 mask = 1 << (index % 32);
344
345 if (gic_irq_in_rdist(d))
346 base = gic_data_rdist_sgi_base();
347 else
348 base = gic_data.dist_base;
349
350 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
351 }
352
gic_poke_irq(struct irq_data * d,u32 offset)353 static void gic_poke_irq(struct irq_data *d, u32 offset)
354 {
355 void (*rwp_wait)(void);
356 void __iomem *base;
357 u32 index, mask;
358
359 offset = convert_offset_index(d, offset, &index);
360 mask = 1 << (index % 32);
361
362 if (gic_irq_in_rdist(d)) {
363 base = gic_data_rdist_sgi_base();
364 rwp_wait = gic_redist_wait_for_rwp;
365 } else {
366 base = gic_data.dist_base;
367 rwp_wait = gic_dist_wait_for_rwp;
368 }
369
370 writel_relaxed(mask, base + offset + (index / 32) * 4);
371 rwp_wait();
372 }
373
gic_mask_irq(struct irq_data * d)374 static void gic_mask_irq(struct irq_data *d)
375 {
376 gic_poke_irq(d, GICD_ICENABLER);
377 }
378
gic_eoimode1_mask_irq(struct irq_data * d)379 static void gic_eoimode1_mask_irq(struct irq_data *d)
380 {
381 gic_mask_irq(d);
382 /*
383 * When masking a forwarded interrupt, make sure it is
384 * deactivated as well.
385 *
386 * This ensures that an interrupt that is getting
387 * disabled/masked will not get "stuck", because there is
388 * noone to deactivate it (guest is being terminated).
389 */
390 if (irqd_is_forwarded_to_vcpu(d))
391 gic_poke_irq(d, GICD_ICACTIVER);
392 }
393
gic_unmask_irq(struct irq_data * d)394 static void gic_unmask_irq(struct irq_data *d)
395 {
396 gic_poke_irq(d, GICD_ISENABLER);
397 }
398
gic_supports_nmi(void)399 static inline bool gic_supports_nmi(void)
400 {
401 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
402 static_branch_likely(&supports_pseudo_nmis);
403 }
404
gic_irq_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool val)405 static int gic_irq_set_irqchip_state(struct irq_data *d,
406 enum irqchip_irq_state which, bool val)
407 {
408 u32 reg;
409
410 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
411 return -EINVAL;
412
413 switch (which) {
414 case IRQCHIP_STATE_PENDING:
415 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
416 break;
417
418 case IRQCHIP_STATE_ACTIVE:
419 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
420 break;
421
422 case IRQCHIP_STATE_MASKED:
423 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
424 break;
425
426 default:
427 return -EINVAL;
428 }
429
430 gic_poke_irq(d, reg);
431 return 0;
432 }
433
gic_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * val)434 static int gic_irq_get_irqchip_state(struct irq_data *d,
435 enum irqchip_irq_state which, bool *val)
436 {
437 if (d->hwirq >= 8192) /* PPI/SPI only */
438 return -EINVAL;
439
440 switch (which) {
441 case IRQCHIP_STATE_PENDING:
442 *val = gic_peek_irq(d, GICD_ISPENDR);
443 break;
444
445 case IRQCHIP_STATE_ACTIVE:
446 *val = gic_peek_irq(d, GICD_ISACTIVER);
447 break;
448
449 case IRQCHIP_STATE_MASKED:
450 *val = !gic_peek_irq(d, GICD_ISENABLER);
451 break;
452
453 default:
454 return -EINVAL;
455 }
456
457 return 0;
458 }
459
gic_irq_set_prio(struct irq_data * d,u8 prio)460 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
461 {
462 void __iomem *base = gic_dist_base(d);
463 u32 offset, index;
464
465 offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
466
467 writeb_relaxed(prio, base + offset + index);
468 }
469
gic_get_ppi_index(struct irq_data * d)470 static u32 gic_get_ppi_index(struct irq_data *d)
471 {
472 switch (get_intid_range(d)) {
473 case PPI_RANGE:
474 return d->hwirq - 16;
475 case EPPI_RANGE:
476 return d->hwirq - EPPI_BASE_INTID + 16;
477 default:
478 unreachable();
479 }
480 }
481
gic_irq_nmi_setup(struct irq_data * d)482 static int gic_irq_nmi_setup(struct irq_data *d)
483 {
484 struct irq_desc *desc = irq_to_desc(d->irq);
485
486 if (!gic_supports_nmi())
487 return -EINVAL;
488
489 if (gic_peek_irq(d, GICD_ISENABLER)) {
490 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
491 return -EINVAL;
492 }
493
494 /*
495 * A secondary irq_chip should be in charge of LPI request,
496 * it should not be possible to get there
497 */
498 if (WARN_ON(gic_irq(d) >= 8192))
499 return -EINVAL;
500
501 /* desc lock should already be held */
502 if (gic_irq_in_rdist(d)) {
503 u32 idx = gic_get_ppi_index(d);
504
505 /* Setting up PPI as NMI, only switch handler for first NMI */
506 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
507 refcount_set(&ppi_nmi_refs[idx], 1);
508 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
509 }
510 } else {
511 desc->handle_irq = handle_fasteoi_nmi;
512 }
513
514 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
515
516 return 0;
517 }
518
gic_irq_nmi_teardown(struct irq_data * d)519 static void gic_irq_nmi_teardown(struct irq_data *d)
520 {
521 struct irq_desc *desc = irq_to_desc(d->irq);
522
523 if (WARN_ON(!gic_supports_nmi()))
524 return;
525
526 if (gic_peek_irq(d, GICD_ISENABLER)) {
527 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
528 return;
529 }
530
531 /*
532 * A secondary irq_chip should be in charge of LPI request,
533 * it should not be possible to get there
534 */
535 if (WARN_ON(gic_irq(d) >= 8192))
536 return;
537
538 /* desc lock should already be held */
539 if (gic_irq_in_rdist(d)) {
540 u32 idx = gic_get_ppi_index(d);
541
542 /* Tearing down NMI, only switch handler for last NMI */
543 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
544 desc->handle_irq = handle_percpu_devid_irq;
545 } else {
546 desc->handle_irq = handle_fasteoi_irq;
547 }
548
549 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
550 }
551
gic_eoi_irq(struct irq_data * d)552 static void gic_eoi_irq(struct irq_data *d)
553 {
554 gic_write_eoir(gic_irq(d));
555 }
556
gic_eoimode1_eoi_irq(struct irq_data * d)557 static void gic_eoimode1_eoi_irq(struct irq_data *d)
558 {
559 /*
560 * No need to deactivate an LPI, or an interrupt that
561 * is is getting forwarded to a vcpu.
562 */
563 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
564 return;
565 gic_write_dir(gic_irq(d));
566 }
567
gic_set_type(struct irq_data * d,unsigned int type)568 static int gic_set_type(struct irq_data *d, unsigned int type)
569 {
570 enum gic_intid_range range;
571 unsigned int irq = gic_irq(d);
572 void (*rwp_wait)(void);
573 void __iomem *base;
574 u32 offset, index;
575 int ret;
576
577 range = get_intid_range(d);
578
579 /* Interrupt configuration for SGIs can't be changed */
580 if (range == SGI_RANGE)
581 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
582
583 /* SPIs have restrictions on the supported types */
584 if ((range == SPI_RANGE || range == ESPI_RANGE) &&
585 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
586 return -EINVAL;
587
588 if (gic_irq_in_rdist(d)) {
589 base = gic_data_rdist_sgi_base();
590 rwp_wait = gic_redist_wait_for_rwp;
591 } else {
592 base = gic_data.dist_base;
593 rwp_wait = gic_dist_wait_for_rwp;
594 }
595
596 offset = convert_offset_index(d, GICD_ICFGR, &index);
597
598 ret = gic_configure_irq(index, type, base + offset, rwp_wait);
599 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
600 /* Misconfigured PPIs are usually not fatal */
601 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
602 ret = 0;
603 }
604
605 return ret;
606 }
607
gic_irq_set_vcpu_affinity(struct irq_data * d,void * vcpu)608 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
609 {
610 if (get_intid_range(d) == SGI_RANGE)
611 return -EINVAL;
612
613 if (vcpu)
614 irqd_set_forwarded_to_vcpu(d);
615 else
616 irqd_clr_forwarded_to_vcpu(d);
617 return 0;
618 }
619
gic_mpidr_to_affinity(unsigned long mpidr)620 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
621 {
622 u64 aff;
623
624 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
625 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
626 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
627 MPIDR_AFFINITY_LEVEL(mpidr, 0));
628
629 return aff;
630 }
631
gic_deactivate_unhandled(u32 irqnr)632 static void gic_deactivate_unhandled(u32 irqnr)
633 {
634 if (static_branch_likely(&supports_deactivate_key)) {
635 if (irqnr < 8192)
636 gic_write_dir(irqnr);
637 } else {
638 gic_write_eoir(irqnr);
639 }
640 }
641
gic_handle_nmi(u32 irqnr,struct pt_regs * regs)642 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
643 {
644 bool irqs_enabled = interrupts_enabled(regs);
645 int err;
646
647 if (irqs_enabled)
648 nmi_enter();
649
650 if (static_branch_likely(&supports_deactivate_key))
651 gic_write_eoir(irqnr);
652 /*
653 * Leave the PSR.I bit set to prevent other NMIs to be
654 * received while handling this one.
655 * PSR.I will be restored when we ERET to the
656 * interrupted context.
657 */
658 err = handle_domain_nmi(gic_data.domain, irqnr, regs);
659 if (err)
660 gic_deactivate_unhandled(irqnr);
661
662 if (irqs_enabled)
663 nmi_exit();
664 }
665
do_read_iar(struct pt_regs * regs)666 static u32 do_read_iar(struct pt_regs *regs)
667 {
668 u32 iar;
669
670 if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) {
671 u64 pmr;
672
673 /*
674 * We were in a context with IRQs disabled. However, the
675 * entry code has set PMR to a value that allows any
676 * interrupt to be acknowledged, and not just NMIs. This can
677 * lead to surprising effects if the NMI has been retired in
678 * the meantime, and that there is an IRQ pending. The IRQ
679 * would then be taken in NMI context, something that nobody
680 * wants to debug twice.
681 *
682 * Until we sort this, drop PMR again to a level that will
683 * actually only allow NMIs before reading IAR, and then
684 * restore it to what it was.
685 */
686 pmr = gic_read_pmr();
687 gic_pmr_mask_irqs();
688 isb();
689
690 iar = gic_read_iar();
691
692 gic_write_pmr(pmr);
693 } else {
694 iar = gic_read_iar();
695 }
696
697 return iar;
698 }
699
gic_handle_irq(struct pt_regs * regs)700 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
701 {
702 u32 irqnr;
703
704 irqnr = do_read_iar(regs);
705
706 /* Check for special IDs first */
707 if ((irqnr >= 1020 && irqnr <= 1023))
708 return;
709
710 if (gic_supports_nmi() &&
711 unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {
712 gic_handle_nmi(irqnr, regs);
713 return;
714 }
715
716 if (gic_prio_masking_enabled()) {
717 gic_pmr_mask_irqs();
718 gic_arch_enable_irqs();
719 }
720
721 if (static_branch_likely(&supports_deactivate_key))
722 gic_write_eoir(irqnr);
723 else
724 isb();
725
726 if (handle_domain_irq(gic_data.domain, irqnr, regs)) {
727 WARN_ONCE(true, "Unexpected interrupt received!\n");
728 gic_deactivate_unhandled(irqnr);
729 }
730 }
731
gic_get_pribits(void)732 static u32 gic_get_pribits(void)
733 {
734 u32 pribits;
735
736 pribits = gic_read_ctlr();
737 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
738 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
739 pribits++;
740
741 return pribits;
742 }
743
gic_has_group0(void)744 static bool gic_has_group0(void)
745 {
746 u32 val;
747 u32 old_pmr;
748
749 old_pmr = gic_read_pmr();
750
751 /*
752 * Let's find out if Group0 is under control of EL3 or not by
753 * setting the highest possible, non-zero priority in PMR.
754 *
755 * If SCR_EL3.FIQ is set, the priority gets shifted down in
756 * order for the CPU interface to set bit 7, and keep the
757 * actual priority in the non-secure range. In the process, it
758 * looses the least significant bit and the actual priority
759 * becomes 0x80. Reading it back returns 0, indicating that
760 * we're don't have access to Group0.
761 */
762 gic_write_pmr(BIT(8 - gic_get_pribits()));
763 val = gic_read_pmr();
764
765 gic_write_pmr(old_pmr);
766
767 return val != 0;
768 }
769
gic_dist_init(void)770 static void __init gic_dist_init(void)
771 {
772 unsigned int i;
773 u64 affinity;
774 void __iomem *base = gic_data.dist_base;
775 u32 val;
776
777 /* Disable the distributor */
778 writel_relaxed(0, base + GICD_CTLR);
779 gic_dist_wait_for_rwp();
780
781 /*
782 * Configure SPIs as non-secure Group-1. This will only matter
783 * if the GIC only has a single security state. This will not
784 * do the right thing if the kernel is running in secure mode,
785 * but that's not the intended use case anyway.
786 */
787 for (i = 32; i < GIC_LINE_NR; i += 32)
788 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
789
790 /* Extended SPI range, not handled by the GICv2/GICv3 common code */
791 for (i = 0; i < GIC_ESPI_NR; i += 32) {
792 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
793 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
794 }
795
796 for (i = 0; i < GIC_ESPI_NR; i += 32)
797 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
798
799 for (i = 0; i < GIC_ESPI_NR; i += 16)
800 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
801
802 for (i = 0; i < GIC_ESPI_NR; i += 4)
803 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
804
805 /* Now do the common stuff, and wait for the distributor to drain */
806 gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
807
808 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
809 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
810 pr_info("Enabling SGIs without active state\n");
811 val |= GICD_CTLR_nASSGIreq;
812 }
813
814 /* Enable distributor with ARE, Group1 */
815 writel_relaxed(val, base + GICD_CTLR);
816
817 /*
818 * Set all global interrupts to the boot CPU only. ARE must be
819 * enabled.
820 */
821 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
822 for (i = 32; i < GIC_LINE_NR; i++)
823 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
824
825 for (i = 0; i < GIC_ESPI_NR; i++)
826 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
827 }
828
gic_iterate_rdists(int (* fn)(struct redist_region *,void __iomem *))829 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
830 {
831 int ret = -ENODEV;
832 int i;
833
834 for (i = 0; i < gic_data.nr_redist_regions; i++) {
835 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
836 u64 typer;
837 u32 reg;
838
839 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
840 if (reg != GIC_PIDR2_ARCH_GICv3 &&
841 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
842 pr_warn("No redistributor present @%p\n", ptr);
843 break;
844 }
845
846 do {
847 typer = gic_read_typer(ptr + GICR_TYPER);
848 ret = fn(gic_data.redist_regions + i, ptr);
849 if (!ret)
850 return 0;
851
852 if (gic_data.redist_regions[i].single_redist)
853 break;
854
855 if (gic_data.redist_stride) {
856 ptr += gic_data.redist_stride;
857 } else {
858 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
859 if (typer & GICR_TYPER_VLPIS)
860 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
861 }
862 } while (!(typer & GICR_TYPER_LAST));
863 }
864
865 return ret ? -ENODEV : 0;
866 }
867
__gic_populate_rdist(struct redist_region * region,void __iomem * ptr)868 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
869 {
870 unsigned long mpidr = cpu_logical_map(smp_processor_id());
871 u64 typer;
872 u32 aff;
873
874 /*
875 * Convert affinity to a 32bit value that can be matched to
876 * GICR_TYPER bits [63:32].
877 */
878 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
879 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
880 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
881 MPIDR_AFFINITY_LEVEL(mpidr, 0));
882
883 typer = gic_read_typer(ptr + GICR_TYPER);
884 if ((typer >> 32) == aff) {
885 u64 offset = ptr - region->redist_base;
886 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
887 gic_data_rdist_rd_base() = ptr;
888 gic_data_rdist()->phys_base = region->phys_base + offset;
889
890 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
891 smp_processor_id(), mpidr,
892 (int)(region - gic_data.redist_regions),
893 &gic_data_rdist()->phys_base);
894 return 0;
895 }
896
897 /* Try next one */
898 return 1;
899 }
900
gic_populate_rdist(void)901 static int gic_populate_rdist(void)
902 {
903 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
904 return 0;
905
906 /* We couldn't even deal with ourselves... */
907 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
908 smp_processor_id(),
909 (unsigned long)cpu_logical_map(smp_processor_id()));
910 return -ENODEV;
911 }
912
__gic_update_rdist_properties(struct redist_region * region,void __iomem * ptr)913 static int __gic_update_rdist_properties(struct redist_region *region,
914 void __iomem *ptr)
915 {
916 u64 typer = gic_read_typer(ptr + GICR_TYPER);
917
918 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
919
920 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
921 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
922 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
923 gic_data.rdists.has_rvpeid);
924 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
925
926 /* Detect non-sensical configurations */
927 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
928 gic_data.rdists.has_direct_lpi = false;
929 gic_data.rdists.has_vlpis = false;
930 gic_data.rdists.has_rvpeid = false;
931 }
932
933 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
934
935 return 1;
936 }
937
gic_update_rdist_properties(void)938 static void gic_update_rdist_properties(void)
939 {
940 gic_data.ppi_nr = UINT_MAX;
941 gic_iterate_rdists(__gic_update_rdist_properties);
942 if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
943 gic_data.ppi_nr = 0;
944 pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
945 if (gic_data.rdists.has_vlpis)
946 pr_info("GICv4 features: %s%s%s\n",
947 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
948 gic_data.rdists.has_rvpeid ? "RVPEID " : "",
949 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
950 }
951
952 /* Check whether it's single security state view */
gic_dist_security_disabled(void)953 static inline bool gic_dist_security_disabled(void)
954 {
955 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
956 }
957
gic_cpu_sys_reg_init(void)958 static void gic_cpu_sys_reg_init(void)
959 {
960 int i, cpu = smp_processor_id();
961 u64 mpidr = cpu_logical_map(cpu);
962 u64 need_rss = MPIDR_RS(mpidr);
963 bool group0;
964 u32 pribits;
965
966 /*
967 * Need to check that the SRE bit has actually been set. If
968 * not, it means that SRE is disabled at EL2. We're going to
969 * die painfully, and there is nothing we can do about it.
970 *
971 * Kindly inform the luser.
972 */
973 if (!gic_enable_sre())
974 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
975
976 pribits = gic_get_pribits();
977
978 group0 = gic_has_group0();
979
980 /* Set priority mask register */
981 if (!gic_prio_masking_enabled()) {
982 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
983 } else if (gic_supports_nmi()) {
984 /*
985 * Mismatch configuration with boot CPU, the system is likely
986 * to die as interrupt masking will not work properly on all
987 * CPUs
988 *
989 * The boot CPU calls this function before enabling NMI support,
990 * and as a result we'll never see this warning in the boot path
991 * for that CPU.
992 */
993 if (static_branch_unlikely(&gic_nonsecure_priorities))
994 WARN_ON(!group0 || gic_dist_security_disabled());
995 else
996 WARN_ON(group0 && !gic_dist_security_disabled());
997 }
998
999 /*
1000 * Some firmwares hand over to the kernel with the BPR changed from
1001 * its reset value (and with a value large enough to prevent
1002 * any pre-emptive interrupts from working at all). Writing a zero
1003 * to BPR restores is reset value.
1004 */
1005 gic_write_bpr1(0);
1006
1007 if (static_branch_likely(&supports_deactivate_key)) {
1008 /* EOI drops priority only (mode 1) */
1009 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
1010 } else {
1011 /* EOI deactivates interrupt too (mode 0) */
1012 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
1013 }
1014
1015 /* Always whack Group0 before Group1 */
1016 if (group0) {
1017 switch(pribits) {
1018 case 8:
1019 case 7:
1020 write_gicreg(0, ICC_AP0R3_EL1);
1021 write_gicreg(0, ICC_AP0R2_EL1);
1022 fallthrough;
1023 case 6:
1024 write_gicreg(0, ICC_AP0R1_EL1);
1025 fallthrough;
1026 case 5:
1027 case 4:
1028 write_gicreg(0, ICC_AP0R0_EL1);
1029 }
1030
1031 isb();
1032 }
1033
1034 switch(pribits) {
1035 case 8:
1036 case 7:
1037 write_gicreg(0, ICC_AP1R3_EL1);
1038 write_gicreg(0, ICC_AP1R2_EL1);
1039 fallthrough;
1040 case 6:
1041 write_gicreg(0, ICC_AP1R1_EL1);
1042 fallthrough;
1043 case 5:
1044 case 4:
1045 write_gicreg(0, ICC_AP1R0_EL1);
1046 }
1047
1048 isb();
1049
1050 /* ... and let's hit the road... */
1051 gic_write_grpen1(1);
1052
1053 /* Keep the RSS capability status in per_cpu variable */
1054 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1055
1056 /* Check all the CPUs have capable of sending SGIs to other CPUs */
1057 for_each_online_cpu(i) {
1058 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1059
1060 need_rss |= MPIDR_RS(cpu_logical_map(i));
1061 if (need_rss && (!have_rss))
1062 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1063 cpu, (unsigned long)mpidr,
1064 i, (unsigned long)cpu_logical_map(i));
1065 }
1066
1067 /**
1068 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1069 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1070 * UNPREDICTABLE choice of :
1071 * - The write is ignored.
1072 * - The RS field is treated as 0.
1073 */
1074 if (need_rss && (!gic_data.has_rss))
1075 pr_crit_once("RSS is required but GICD doesn't support it\n");
1076 }
1077
1078 static bool gicv3_nolpi;
1079
gicv3_nolpi_cfg(char * buf)1080 static int __init gicv3_nolpi_cfg(char *buf)
1081 {
1082 return strtobool(buf, &gicv3_nolpi);
1083 }
1084 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1085
gic_dist_supports_lpis(void)1086 static int gic_dist_supports_lpis(void)
1087 {
1088 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1089 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1090 !gicv3_nolpi);
1091 }
1092
gic_cpu_init(void)1093 static void gic_cpu_init(void)
1094 {
1095 void __iomem *rbase;
1096 int i;
1097
1098 /* Register ourselves with the rest of the world */
1099 if (gic_populate_rdist())
1100 return;
1101
1102 gic_enable_redist(true);
1103
1104 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1105 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1106 "Distributor has extended ranges, but CPU%d doesn't\n",
1107 smp_processor_id());
1108
1109 rbase = gic_data_rdist_sgi_base();
1110
1111 /* Configure SGIs/PPIs as non-secure Group-1 */
1112 for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1113 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1114
1115 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1116
1117 /* initialise system registers */
1118 gic_cpu_sys_reg_init();
1119 }
1120
1121 #ifdef CONFIG_SMP
1122
1123 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1124 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
1125
gic_starting_cpu(unsigned int cpu)1126 static int gic_starting_cpu(unsigned int cpu)
1127 {
1128 gic_cpu_init();
1129
1130 if (gic_dist_supports_lpis())
1131 its_cpu_init();
1132
1133 return 0;
1134 }
1135
gic_compute_target_list(int * base_cpu,const struct cpumask * mask,unsigned long cluster_id)1136 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1137 unsigned long cluster_id)
1138 {
1139 int next_cpu, cpu = *base_cpu;
1140 unsigned long mpidr = cpu_logical_map(cpu);
1141 u16 tlist = 0;
1142
1143 while (cpu < nr_cpu_ids) {
1144 tlist |= 1 << (mpidr & 0xf);
1145
1146 next_cpu = cpumask_next(cpu, mask);
1147 if (next_cpu >= nr_cpu_ids)
1148 goto out;
1149 cpu = next_cpu;
1150
1151 mpidr = cpu_logical_map(cpu);
1152
1153 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1154 cpu--;
1155 goto out;
1156 }
1157 }
1158 out:
1159 *base_cpu = cpu;
1160 return tlist;
1161 }
1162
1163 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1164 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1165 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1166
gic_send_sgi(u64 cluster_id,u16 tlist,unsigned int irq)1167 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1168 {
1169 u64 val;
1170
1171 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1172 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
1173 irq << ICC_SGI1R_SGI_ID_SHIFT |
1174 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
1175 MPIDR_TO_SGI_RS(cluster_id) |
1176 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1177
1178 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1179 gic_write_sgi1r(val);
1180 }
1181
gic_ipi_send_mask(struct irq_data * d,const struct cpumask * mask)1182 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1183 {
1184 int cpu;
1185
1186 if (WARN_ON(d->hwirq >= 16))
1187 return;
1188
1189 /*
1190 * Ensure that stores to Normal memory are visible to the
1191 * other CPUs before issuing the IPI.
1192 */
1193 wmb();
1194
1195 for_each_cpu(cpu, mask) {
1196 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
1197 u16 tlist;
1198
1199 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1200 gic_send_sgi(cluster_id, tlist, d->hwirq);
1201 }
1202
1203 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1204 isb();
1205 }
1206
gic_smp_init(void)1207 static void __init gic_smp_init(void)
1208 {
1209 struct irq_fwspec sgi_fwspec = {
1210 .fwnode = gic_data.fwnode,
1211 .param_count = 1,
1212 };
1213 int base_sgi;
1214
1215 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1216 "irqchip/arm/gicv3:starting",
1217 gic_starting_cpu, NULL);
1218
1219 /* Register all 8 non-secure SGIs */
1220 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,
1221 NUMA_NO_NODE, &sgi_fwspec,
1222 false, NULL);
1223 if (WARN_ON(base_sgi <= 0))
1224 return;
1225
1226 set_smp_ipi_range(base_sgi, 8);
1227 }
1228
gic_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)1229 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1230 bool force)
1231 {
1232 unsigned int cpu;
1233 u32 offset, index;
1234 void __iomem *reg;
1235 int enabled;
1236 u64 val;
1237
1238 if (force)
1239 cpu = cpumask_first(mask_val);
1240 else
1241 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1242
1243 if (cpu >= nr_cpu_ids)
1244 return -EINVAL;
1245
1246 if (gic_irq_in_rdist(d))
1247 return -EINVAL;
1248
1249 /* If interrupt was enabled, disable it first */
1250 enabled = gic_peek_irq(d, GICD_ISENABLER);
1251 if (enabled)
1252 gic_mask_irq(d);
1253
1254 offset = convert_offset_index(d, GICD_IROUTER, &index);
1255 reg = gic_dist_base(d) + offset + (index * 8);
1256 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1257
1258 gic_write_irouter(val, reg);
1259
1260 /*
1261 * If the interrupt was enabled, enabled it again. Otherwise,
1262 * just wait for the distributor to have digested our changes.
1263 */
1264 if (enabled)
1265 gic_unmask_irq(d);
1266 else
1267 gic_dist_wait_for_rwp();
1268
1269 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1270
1271 return IRQ_SET_MASK_OK_DONE;
1272 }
1273 #else
1274 #define gic_set_affinity NULL
1275 #define gic_ipi_send_mask NULL
1276 #define gic_smp_init() do { } while(0)
1277 #endif
1278
gic_retrigger(struct irq_data * data)1279 static int gic_retrigger(struct irq_data *data)
1280 {
1281 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
1282 }
1283
1284 #ifdef CONFIG_CPU_PM
gic_cpu_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)1285 static int gic_cpu_pm_notifier(struct notifier_block *self,
1286 unsigned long cmd, void *v)
1287 {
1288 if (cmd == CPU_PM_EXIT) {
1289 if (gic_dist_security_disabled())
1290 gic_enable_redist(true);
1291 gic_cpu_sys_reg_init();
1292 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1293 gic_write_grpen1(0);
1294 gic_enable_redist(false);
1295 }
1296 return NOTIFY_OK;
1297 }
1298
1299 static struct notifier_block gic_cpu_pm_notifier_block = {
1300 .notifier_call = gic_cpu_pm_notifier,
1301 };
1302
gic_cpu_pm_init(void)1303 static void gic_cpu_pm_init(void)
1304 {
1305 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1306 }
1307
1308 #else
gic_cpu_pm_init(void)1309 static inline void gic_cpu_pm_init(void) { }
1310 #endif /* CONFIG_CPU_PM */
1311
1312 static struct irq_chip gic_chip = {
1313 .name = "GICv3",
1314 .irq_mask = gic_mask_irq,
1315 .irq_unmask = gic_unmask_irq,
1316 .irq_eoi = gic_eoi_irq,
1317 .irq_set_type = gic_set_type,
1318 .irq_set_affinity = gic_set_affinity,
1319 .irq_retrigger = gic_retrigger,
1320 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1321 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1322 .irq_nmi_setup = gic_irq_nmi_setup,
1323 .irq_nmi_teardown = gic_irq_nmi_teardown,
1324 .ipi_send_mask = gic_ipi_send_mask,
1325 .flags = IRQCHIP_SET_TYPE_MASKED |
1326 IRQCHIP_SKIP_SET_WAKE |
1327 IRQCHIP_MASK_ON_SUSPEND,
1328 };
1329
1330 static struct irq_chip gic_eoimode1_chip = {
1331 .name = "GICv3",
1332 .irq_mask = gic_eoimode1_mask_irq,
1333 .irq_unmask = gic_unmask_irq,
1334 .irq_eoi = gic_eoimode1_eoi_irq,
1335 .irq_set_type = gic_set_type,
1336 .irq_set_affinity = gic_set_affinity,
1337 .irq_retrigger = gic_retrigger,
1338 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1339 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1340 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
1341 .irq_nmi_setup = gic_irq_nmi_setup,
1342 .irq_nmi_teardown = gic_irq_nmi_teardown,
1343 .ipi_send_mask = gic_ipi_send_mask,
1344 .flags = IRQCHIP_SET_TYPE_MASKED |
1345 IRQCHIP_SKIP_SET_WAKE |
1346 IRQCHIP_MASK_ON_SUSPEND,
1347 };
1348
gic_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)1349 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1350 irq_hw_number_t hw)
1351 {
1352 struct irq_chip *chip = &gic_chip;
1353 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1354
1355 if (static_branch_likely(&supports_deactivate_key))
1356 chip = &gic_eoimode1_chip;
1357
1358 switch (__get_intid_range(hw)) {
1359 case SGI_RANGE:
1360 irq_set_percpu_devid(irq);
1361 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1362 handle_percpu_devid_fasteoi_ipi,
1363 NULL, NULL);
1364 break;
1365
1366 case PPI_RANGE:
1367 case EPPI_RANGE:
1368 irq_set_percpu_devid(irq);
1369 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1370 handle_percpu_devid_irq, NULL, NULL);
1371 break;
1372
1373 case SPI_RANGE:
1374 case ESPI_RANGE:
1375 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1376 handle_fasteoi_irq, NULL, NULL);
1377 irq_set_probe(irq);
1378 irqd_set_single_target(irqd);
1379 break;
1380
1381 case LPI_RANGE:
1382 if (!gic_dist_supports_lpis())
1383 return -EPERM;
1384 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1385 handle_fasteoi_irq, NULL, NULL);
1386 break;
1387
1388 default:
1389 return -EPERM;
1390 }
1391
1392 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1393 irqd_set_handle_enforce_irqctx(irqd);
1394 return 0;
1395 }
1396
gic_irq_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1397 static int gic_irq_domain_translate(struct irq_domain *d,
1398 struct irq_fwspec *fwspec,
1399 unsigned long *hwirq,
1400 unsigned int *type)
1401 {
1402 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1403 *hwirq = fwspec->param[0];
1404 *type = IRQ_TYPE_EDGE_RISING;
1405 return 0;
1406 }
1407
1408 if (is_of_node(fwspec->fwnode)) {
1409 if (fwspec->param_count < 3)
1410 return -EINVAL;
1411
1412 switch (fwspec->param[0]) {
1413 case 0: /* SPI */
1414 *hwirq = fwspec->param[1] + 32;
1415 break;
1416 case 1: /* PPI */
1417 *hwirq = fwspec->param[1] + 16;
1418 break;
1419 case 2: /* ESPI */
1420 *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1421 break;
1422 case 3: /* EPPI */
1423 *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1424 break;
1425 case GIC_IRQ_TYPE_LPI: /* LPI */
1426 *hwirq = fwspec->param[1];
1427 break;
1428 case GIC_IRQ_TYPE_PARTITION:
1429 *hwirq = fwspec->param[1];
1430 if (fwspec->param[1] >= 16)
1431 *hwirq += EPPI_BASE_INTID - 16;
1432 else
1433 *hwirq += 16;
1434 break;
1435 default:
1436 return -EINVAL;
1437 }
1438
1439 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1440
1441 /*
1442 * Make it clear that broken DTs are... broken.
1443 * Partitionned PPIs are an unfortunate exception.
1444 */
1445 WARN_ON(*type == IRQ_TYPE_NONE &&
1446 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1447 return 0;
1448 }
1449
1450 if (is_fwnode_irqchip(fwspec->fwnode)) {
1451 if(fwspec->param_count != 2)
1452 return -EINVAL;
1453
1454 *hwirq = fwspec->param[0];
1455 *type = fwspec->param[1];
1456
1457 WARN_ON(*type == IRQ_TYPE_NONE);
1458 return 0;
1459 }
1460
1461 return -EINVAL;
1462 }
1463
gic_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)1464 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1465 unsigned int nr_irqs, void *arg)
1466 {
1467 int i, ret;
1468 irq_hw_number_t hwirq;
1469 unsigned int type = IRQ_TYPE_NONE;
1470 struct irq_fwspec *fwspec = arg;
1471
1472 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1473 if (ret)
1474 return ret;
1475
1476 for (i = 0; i < nr_irqs; i++) {
1477 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1478 if (ret)
1479 return ret;
1480 }
1481
1482 return 0;
1483 }
1484
gic_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)1485 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1486 unsigned int nr_irqs)
1487 {
1488 int i;
1489
1490 for (i = 0; i < nr_irqs; i++) {
1491 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1492 irq_set_handler(virq + i, NULL);
1493 irq_domain_reset_irq_data(d);
1494 }
1495 }
1496
gic_irq_domain_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)1497 static int gic_irq_domain_select(struct irq_domain *d,
1498 struct irq_fwspec *fwspec,
1499 enum irq_domain_bus_token bus_token)
1500 {
1501 /* Not for us */
1502 if (fwspec->fwnode != d->fwnode)
1503 return 0;
1504
1505 /* If this is not DT, then we have a single domain */
1506 if (!is_of_node(fwspec->fwnode))
1507 return 1;
1508
1509 /*
1510 * If this is a PPI and we have a 4th (non-null) parameter,
1511 * then we need to match the partition domain.
1512 */
1513 if (fwspec->param_count >= 4 &&
1514 fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
1515 gic_data.ppi_descs)
1516 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1517
1518 return d == gic_data.domain;
1519 }
1520
1521 static const struct irq_domain_ops gic_irq_domain_ops = {
1522 .translate = gic_irq_domain_translate,
1523 .alloc = gic_irq_domain_alloc,
1524 .free = gic_irq_domain_free,
1525 .select = gic_irq_domain_select,
1526 };
1527
partition_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1528 static int partition_domain_translate(struct irq_domain *d,
1529 struct irq_fwspec *fwspec,
1530 unsigned long *hwirq,
1531 unsigned int *type)
1532 {
1533 struct device_node *np;
1534 int ret;
1535
1536 if (!gic_data.ppi_descs)
1537 return -ENOMEM;
1538
1539 np = of_find_node_by_phandle(fwspec->param[3]);
1540 if (WARN_ON(!np))
1541 return -EINVAL;
1542
1543 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1544 of_node_to_fwnode(np));
1545 if (ret < 0)
1546 return ret;
1547
1548 *hwirq = ret;
1549 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1550
1551 return 0;
1552 }
1553
1554 static const struct irq_domain_ops partition_domain_ops = {
1555 .translate = partition_domain_translate,
1556 .select = gic_irq_domain_select,
1557 };
1558
gic_enable_quirk_msm8996(void * data)1559 static bool gic_enable_quirk_msm8996(void *data)
1560 {
1561 struct gic_chip_data *d = data;
1562
1563 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1564
1565 return true;
1566 }
1567
gic_enable_quirk_cavium_38539(void * data)1568 static bool gic_enable_quirk_cavium_38539(void *data)
1569 {
1570 struct gic_chip_data *d = data;
1571
1572 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1573
1574 return true;
1575 }
1576
gic_enable_quirk_hip06_07(void * data)1577 static bool gic_enable_quirk_hip06_07(void *data)
1578 {
1579 struct gic_chip_data *d = data;
1580
1581 /*
1582 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1583 * not being an actual ARM implementation). The saving grace is
1584 * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1585 * HIP07 doesn't even have a proper IIDR, and still pretends to
1586 * have ESPI. In both cases, put them right.
1587 */
1588 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1589 /* Zero both ESPI and the RES0 field next to it... */
1590 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1591 return true;
1592 }
1593
1594 return false;
1595 }
1596
1597 static const struct gic_quirk gic_quirks[] = {
1598 {
1599 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1600 .compatible = "qcom,msm8996-gic-v3",
1601 .init = gic_enable_quirk_msm8996,
1602 },
1603 {
1604 .desc = "GICv3: HIP06 erratum 161010803",
1605 .iidr = 0x0204043b,
1606 .mask = 0xffffffff,
1607 .init = gic_enable_quirk_hip06_07,
1608 },
1609 {
1610 .desc = "GICv3: HIP07 erratum 161010803",
1611 .iidr = 0x00000000,
1612 .mask = 0xffffffff,
1613 .init = gic_enable_quirk_hip06_07,
1614 },
1615 {
1616 /*
1617 * Reserved register accesses generate a Synchronous
1618 * External Abort. This erratum applies to:
1619 * - ThunderX: CN88xx
1620 * - OCTEON TX: CN83xx, CN81xx
1621 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1622 */
1623 .desc = "GICv3: Cavium erratum 38539",
1624 .iidr = 0xa000034c,
1625 .mask = 0xe8f00fff,
1626 .init = gic_enable_quirk_cavium_38539,
1627 },
1628 {
1629 }
1630 };
1631
gic_enable_nmi_support(void)1632 static void gic_enable_nmi_support(void)
1633 {
1634 int i;
1635
1636 if (!gic_prio_masking_enabled())
1637 return;
1638
1639 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1640 if (!ppi_nmi_refs)
1641 return;
1642
1643 for (i = 0; i < gic_data.ppi_nr; i++)
1644 refcount_set(&ppi_nmi_refs[i], 0);
1645
1646 /*
1647 * Linux itself doesn't use 1:N distribution, so has no need to
1648 * set PMHE. The only reason to have it set is if EL3 requires it
1649 * (and we can't change it).
1650 */
1651 if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1652 static_branch_enable(&gic_pmr_sync);
1653
1654 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
1655 static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
1656
1657 /*
1658 * How priority values are used by the GIC depends on two things:
1659 * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
1660 * and if Group 0 interrupts can be delivered to Linux in the non-secure
1661 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
1662 * the ICC_PMR_EL1 register and the priority that software assigns to
1663 * interrupts:
1664 *
1665 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
1666 * -----------------------------------------------------------
1667 * 1 | - | unchanged | unchanged
1668 * -----------------------------------------------------------
1669 * 0 | 1 | non-secure | non-secure
1670 * -----------------------------------------------------------
1671 * 0 | 0 | unchanged | non-secure
1672 *
1673 * where non-secure means that the value is right-shifted by one and the
1674 * MSB bit set, to make it fit in the non-secure priority range.
1675 *
1676 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
1677 * are both either modified or unchanged, we can use the same set of
1678 * priorities.
1679 *
1680 * In the last case, where only the interrupt priorities are modified to
1681 * be in the non-secure range, we use a different PMR value to mask IRQs
1682 * and the rest of the values that we use remain unchanged.
1683 */
1684 if (gic_has_group0() && !gic_dist_security_disabled())
1685 static_branch_enable(&gic_nonsecure_priorities);
1686
1687 static_branch_enable(&supports_pseudo_nmis);
1688
1689 if (static_branch_likely(&supports_deactivate_key))
1690 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1691 else
1692 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1693 }
1694
gic_init_bases(void __iomem * dist_base,struct redist_region * rdist_regs,u32 nr_redist_regions,u64 redist_stride,struct fwnode_handle * handle)1695 static int __init gic_init_bases(void __iomem *dist_base,
1696 struct redist_region *rdist_regs,
1697 u32 nr_redist_regions,
1698 u64 redist_stride,
1699 struct fwnode_handle *handle)
1700 {
1701 u32 typer;
1702 int err;
1703
1704 if (!is_hyp_mode_available())
1705 static_branch_disable(&supports_deactivate_key);
1706
1707 if (static_branch_likely(&supports_deactivate_key))
1708 pr_info("GIC: Using split EOI/Deactivate mode\n");
1709
1710 gic_data.fwnode = handle;
1711 gic_data.dist_base = dist_base;
1712 gic_data.redist_regions = rdist_regs;
1713 gic_data.nr_redist_regions = nr_redist_regions;
1714 gic_data.redist_stride = redist_stride;
1715
1716 /*
1717 * Find out how many interrupts are supported.
1718 */
1719 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1720 gic_data.rdists.gicd_typer = typer;
1721
1722 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1723 gic_quirks, &gic_data);
1724
1725 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1726 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1727
1728 /*
1729 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1730 * architecture spec (which says that reserved registers are RES0).
1731 */
1732 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1733 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1734
1735 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1736 &gic_data);
1737 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1738 gic_data.rdists.has_rvpeid = true;
1739 gic_data.rdists.has_vlpis = true;
1740 gic_data.rdists.has_direct_lpi = true;
1741 gic_data.rdists.has_vpend_valid_dirty = true;
1742
1743 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1744 err = -ENOMEM;
1745 goto out_free;
1746 }
1747
1748 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1749
1750 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1751 pr_info("Distributor has %sRange Selector support\n",
1752 gic_data.has_rss ? "" : "no ");
1753
1754 if (typer & GICD_TYPER_MBIS) {
1755 err = mbi_init(handle, gic_data.domain);
1756 if (err)
1757 pr_err("Failed to initialize MBIs\n");
1758 }
1759
1760 set_handle_irq(gic_handle_irq);
1761
1762 gic_update_rdist_properties();
1763
1764 gic_dist_init();
1765 gic_cpu_init();
1766 gic_smp_init();
1767 gic_cpu_pm_init();
1768
1769 if (gic_dist_supports_lpis()) {
1770 its_init(handle, &gic_data.rdists, gic_data.domain);
1771 its_cpu_init();
1772 } else {
1773 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1774 gicv2m_init(handle, gic_data.domain);
1775 }
1776
1777 gic_enable_nmi_support();
1778
1779 return 0;
1780
1781 out_free:
1782 if (gic_data.domain)
1783 irq_domain_remove(gic_data.domain);
1784 free_percpu(gic_data.rdists.rdist);
1785 return err;
1786 }
1787
gic_validate_dist_version(void __iomem * dist_base)1788 static int __init gic_validate_dist_version(void __iomem *dist_base)
1789 {
1790 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1791
1792 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1793 return -ENODEV;
1794
1795 return 0;
1796 }
1797
1798 /* Create all possible partitions at boot time */
gic_populate_ppi_partitions(struct device_node * gic_node)1799 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1800 {
1801 struct device_node *parts_node, *child_part;
1802 int part_idx = 0, i;
1803 int nr_parts;
1804 struct partition_affinity *parts;
1805
1806 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1807 if (!parts_node)
1808 return;
1809
1810 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1811 if (!gic_data.ppi_descs)
1812 return;
1813
1814 nr_parts = of_get_child_count(parts_node);
1815
1816 if (!nr_parts)
1817 goto out_put_node;
1818
1819 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1820 if (WARN_ON(!parts))
1821 goto out_put_node;
1822
1823 for_each_child_of_node(parts_node, child_part) {
1824 struct partition_affinity *part;
1825 int n;
1826
1827 part = &parts[part_idx];
1828
1829 part->partition_id = of_node_to_fwnode(child_part);
1830
1831 pr_info("GIC: PPI partition %pOFn[%d] { ",
1832 child_part, part_idx);
1833
1834 n = of_property_count_elems_of_size(child_part, "affinity",
1835 sizeof(u32));
1836 WARN_ON(n <= 0);
1837
1838 for (i = 0; i < n; i++) {
1839 int err, cpu;
1840 u32 cpu_phandle;
1841 struct device_node *cpu_node;
1842
1843 err = of_property_read_u32_index(child_part, "affinity",
1844 i, &cpu_phandle);
1845 if (WARN_ON(err))
1846 continue;
1847
1848 cpu_node = of_find_node_by_phandle(cpu_phandle);
1849 if (WARN_ON(!cpu_node))
1850 continue;
1851
1852 cpu = of_cpu_node_to_id(cpu_node);
1853 if (WARN_ON(cpu < 0))
1854 continue;
1855
1856 pr_cont("%pOF[%d] ", cpu_node, cpu);
1857
1858 cpumask_set_cpu(cpu, &part->mask);
1859 }
1860
1861 pr_cont("}\n");
1862 part_idx++;
1863 }
1864
1865 for (i = 0; i < gic_data.ppi_nr; i++) {
1866 unsigned int irq;
1867 struct partition_desc *desc;
1868 struct irq_fwspec ppi_fwspec = {
1869 .fwnode = gic_data.fwnode,
1870 .param_count = 3,
1871 .param = {
1872 [0] = GIC_IRQ_TYPE_PARTITION,
1873 [1] = i,
1874 [2] = IRQ_TYPE_NONE,
1875 },
1876 };
1877
1878 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1879 if (WARN_ON(!irq))
1880 continue;
1881 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1882 irq, &partition_domain_ops);
1883 if (WARN_ON(!desc))
1884 continue;
1885
1886 gic_data.ppi_descs[i] = desc;
1887 }
1888
1889 out_put_node:
1890 of_node_put(parts_node);
1891 }
1892
gic_of_setup_kvm_info(struct device_node * node)1893 static void __init gic_of_setup_kvm_info(struct device_node *node)
1894 {
1895 int ret;
1896 struct resource r;
1897 u32 gicv_idx;
1898
1899 gic_v3_kvm_info.type = GIC_V3;
1900
1901 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1902 if (!gic_v3_kvm_info.maint_irq)
1903 return;
1904
1905 if (of_property_read_u32(node, "#redistributor-regions",
1906 &gicv_idx))
1907 gicv_idx = 1;
1908
1909 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1910 ret = of_address_to_resource(node, gicv_idx, &r);
1911 if (!ret)
1912 gic_v3_kvm_info.vcpu = r;
1913
1914 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1915 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
1916 gic_set_kvm_info(&gic_v3_kvm_info);
1917 }
1918
gic_of_init(struct device_node * node,struct device_node * parent)1919 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1920 {
1921 void __iomem *dist_base;
1922 struct redist_region *rdist_regs;
1923 u64 redist_stride;
1924 u32 nr_redist_regions;
1925 int err, i;
1926
1927 dist_base = of_iomap(node, 0);
1928 if (!dist_base) {
1929 pr_err("%pOF: unable to map gic dist registers\n", node);
1930 return -ENXIO;
1931 }
1932
1933 err = gic_validate_dist_version(dist_base);
1934 if (err) {
1935 pr_err("%pOF: no distributor detected, giving up\n", node);
1936 goto out_unmap_dist;
1937 }
1938
1939 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1940 nr_redist_regions = 1;
1941
1942 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1943 GFP_KERNEL);
1944 if (!rdist_regs) {
1945 err = -ENOMEM;
1946 goto out_unmap_dist;
1947 }
1948
1949 for (i = 0; i < nr_redist_regions; i++) {
1950 struct resource res;
1951 int ret;
1952
1953 ret = of_address_to_resource(node, 1 + i, &res);
1954 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1955 if (ret || !rdist_regs[i].redist_base) {
1956 pr_err("%pOF: couldn't map region %d\n", node, i);
1957 err = -ENODEV;
1958 goto out_unmap_rdist;
1959 }
1960 rdist_regs[i].phys_base = res.start;
1961 }
1962
1963 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1964 redist_stride = 0;
1965
1966 gic_enable_of_quirks(node, gic_quirks, &gic_data);
1967
1968 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1969 redist_stride, &node->fwnode);
1970 if (err)
1971 goto out_unmap_rdist;
1972
1973 gic_populate_ppi_partitions(node);
1974
1975 if (static_branch_likely(&supports_deactivate_key))
1976 gic_of_setup_kvm_info(node);
1977 return 0;
1978
1979 out_unmap_rdist:
1980 for (i = 0; i < nr_redist_regions; i++)
1981 if (rdist_regs[i].redist_base)
1982 iounmap(rdist_regs[i].redist_base);
1983 kfree(rdist_regs);
1984 out_unmap_dist:
1985 iounmap(dist_base);
1986 return err;
1987 }
1988
1989 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1990
1991 #ifdef CONFIG_ACPI
1992 static struct
1993 {
1994 void __iomem *dist_base;
1995 struct redist_region *redist_regs;
1996 u32 nr_redist_regions;
1997 bool single_redist;
1998 int enabled_rdists;
1999 u32 maint_irq;
2000 int maint_irq_mode;
2001 phys_addr_t vcpu_base;
2002 } acpi_data __initdata;
2003
2004 static void __init
gic_acpi_register_redist(phys_addr_t phys_base,void __iomem * redist_base)2005 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
2006 {
2007 static int count = 0;
2008
2009 acpi_data.redist_regs[count].phys_base = phys_base;
2010 acpi_data.redist_regs[count].redist_base = redist_base;
2011 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
2012 count++;
2013 }
2014
2015 static int __init
gic_acpi_parse_madt_redist(union acpi_subtable_headers * header,const unsigned long end)2016 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
2017 const unsigned long end)
2018 {
2019 struct acpi_madt_generic_redistributor *redist =
2020 (struct acpi_madt_generic_redistributor *)header;
2021 void __iomem *redist_base;
2022
2023 redist_base = ioremap(redist->base_address, redist->length);
2024 if (!redist_base) {
2025 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
2026 return -ENOMEM;
2027 }
2028
2029 gic_acpi_register_redist(redist->base_address, redist_base);
2030 return 0;
2031 }
2032
2033 static int __init
gic_acpi_parse_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2034 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
2035 const unsigned long end)
2036 {
2037 struct acpi_madt_generic_interrupt *gicc =
2038 (struct acpi_madt_generic_interrupt *)header;
2039 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2040 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
2041 void __iomem *redist_base;
2042
2043 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
2044 if (!(gicc->flags & ACPI_MADT_ENABLED))
2045 return 0;
2046
2047 redist_base = ioremap(gicc->gicr_base_address, size);
2048 if (!redist_base)
2049 return -ENOMEM;
2050
2051 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
2052 return 0;
2053 }
2054
gic_acpi_collect_gicr_base(void)2055 static int __init gic_acpi_collect_gicr_base(void)
2056 {
2057 acpi_tbl_entry_handler redist_parser;
2058 enum acpi_madt_type type;
2059
2060 if (acpi_data.single_redist) {
2061 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
2062 redist_parser = gic_acpi_parse_madt_gicc;
2063 } else {
2064 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
2065 redist_parser = gic_acpi_parse_madt_redist;
2066 }
2067
2068 /* Collect redistributor base addresses in GICR entries */
2069 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
2070 return 0;
2071
2072 pr_info("No valid GICR entries exist\n");
2073 return -ENODEV;
2074 }
2075
gic_acpi_match_gicr(union acpi_subtable_headers * header,const unsigned long end)2076 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
2077 const unsigned long end)
2078 {
2079 /* Subtable presence means that redist exists, that's it */
2080 return 0;
2081 }
2082
gic_acpi_match_gicc(union acpi_subtable_headers * header,const unsigned long end)2083 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
2084 const unsigned long end)
2085 {
2086 struct acpi_madt_generic_interrupt *gicc =
2087 (struct acpi_madt_generic_interrupt *)header;
2088
2089 /*
2090 * If GICC is enabled and has valid gicr base address, then it means
2091 * GICR base is presented via GICC
2092 */
2093 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
2094 acpi_data.enabled_rdists++;
2095 return 0;
2096 }
2097
2098 /*
2099 * It's perfectly valid firmware can pass disabled GICC entry, driver
2100 * should not treat as errors, skip the entry instead of probe fail.
2101 */
2102 if (!(gicc->flags & ACPI_MADT_ENABLED))
2103 return 0;
2104
2105 return -ENODEV;
2106 }
2107
gic_acpi_count_gicr_regions(void)2108 static int __init gic_acpi_count_gicr_regions(void)
2109 {
2110 int count;
2111
2112 /*
2113 * Count how many redistributor regions we have. It is not allowed
2114 * to mix redistributor description, GICR and GICC subtables have to be
2115 * mutually exclusive.
2116 */
2117 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2118 gic_acpi_match_gicr, 0);
2119 if (count > 0) {
2120 acpi_data.single_redist = false;
2121 return count;
2122 }
2123
2124 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2125 gic_acpi_match_gicc, 0);
2126 if (count > 0) {
2127 acpi_data.single_redist = true;
2128 count = acpi_data.enabled_rdists;
2129 }
2130
2131 return count;
2132 }
2133
acpi_validate_gic_table(struct acpi_subtable_header * header,struct acpi_probe_entry * ape)2134 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2135 struct acpi_probe_entry *ape)
2136 {
2137 struct acpi_madt_generic_distributor *dist;
2138 int count;
2139
2140 dist = (struct acpi_madt_generic_distributor *)header;
2141 if (dist->version != ape->driver_data)
2142 return false;
2143
2144 /* We need to do that exercise anyway, the sooner the better */
2145 count = gic_acpi_count_gicr_regions();
2146 if (count <= 0)
2147 return false;
2148
2149 acpi_data.nr_redist_regions = count;
2150 return true;
2151 }
2152
gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers * header,const unsigned long end)2153 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2154 const unsigned long end)
2155 {
2156 struct acpi_madt_generic_interrupt *gicc =
2157 (struct acpi_madt_generic_interrupt *)header;
2158 int maint_irq_mode;
2159 static int first_madt = true;
2160
2161 /* Skip unusable CPUs */
2162 if (!(gicc->flags & ACPI_MADT_ENABLED))
2163 return 0;
2164
2165 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2166 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2167
2168 if (first_madt) {
2169 first_madt = false;
2170
2171 acpi_data.maint_irq = gicc->vgic_interrupt;
2172 acpi_data.maint_irq_mode = maint_irq_mode;
2173 acpi_data.vcpu_base = gicc->gicv_base_address;
2174
2175 return 0;
2176 }
2177
2178 /*
2179 * The maintenance interrupt and GICV should be the same for every CPU
2180 */
2181 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2182 (acpi_data.maint_irq_mode != maint_irq_mode) ||
2183 (acpi_data.vcpu_base != gicc->gicv_base_address))
2184 return -EINVAL;
2185
2186 return 0;
2187 }
2188
gic_acpi_collect_virt_info(void)2189 static bool __init gic_acpi_collect_virt_info(void)
2190 {
2191 int count;
2192
2193 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2194 gic_acpi_parse_virt_madt_gicc, 0);
2195
2196 return (count > 0);
2197 }
2198
2199 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2200 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
2201 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
2202
gic_acpi_setup_kvm_info(void)2203 static void __init gic_acpi_setup_kvm_info(void)
2204 {
2205 int irq;
2206
2207 if (!gic_acpi_collect_virt_info()) {
2208 pr_warn("Unable to get hardware information used for virtualization\n");
2209 return;
2210 }
2211
2212 gic_v3_kvm_info.type = GIC_V3;
2213
2214 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2215 acpi_data.maint_irq_mode,
2216 ACPI_ACTIVE_HIGH);
2217 if (irq <= 0)
2218 return;
2219
2220 gic_v3_kvm_info.maint_irq = irq;
2221
2222 if (acpi_data.vcpu_base) {
2223 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2224
2225 vcpu->flags = IORESOURCE_MEM;
2226 vcpu->start = acpi_data.vcpu_base;
2227 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2228 }
2229
2230 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2231 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2232 gic_set_kvm_info(&gic_v3_kvm_info);
2233 }
2234
2235 static int __init
gic_acpi_init(union acpi_subtable_headers * header,const unsigned long end)2236 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
2237 {
2238 struct acpi_madt_generic_distributor *dist;
2239 struct fwnode_handle *domain_handle;
2240 size_t size;
2241 int i, err;
2242
2243 /* Get distributor base address */
2244 dist = (struct acpi_madt_generic_distributor *)header;
2245 acpi_data.dist_base = ioremap(dist->base_address,
2246 ACPI_GICV3_DIST_MEM_SIZE);
2247 if (!acpi_data.dist_base) {
2248 pr_err("Unable to map GICD registers\n");
2249 return -ENOMEM;
2250 }
2251
2252 err = gic_validate_dist_version(acpi_data.dist_base);
2253 if (err) {
2254 pr_err("No distributor detected at @%p, giving up\n",
2255 acpi_data.dist_base);
2256 goto out_dist_unmap;
2257 }
2258
2259 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2260 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2261 if (!acpi_data.redist_regs) {
2262 err = -ENOMEM;
2263 goto out_dist_unmap;
2264 }
2265
2266 err = gic_acpi_collect_gicr_base();
2267 if (err)
2268 goto out_redist_unmap;
2269
2270 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2271 if (!domain_handle) {
2272 err = -ENOMEM;
2273 goto out_redist_unmap;
2274 }
2275
2276 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2277 acpi_data.nr_redist_regions, 0, domain_handle);
2278 if (err)
2279 goto out_fwhandle_free;
2280
2281 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
2282
2283 if (static_branch_likely(&supports_deactivate_key))
2284 gic_acpi_setup_kvm_info();
2285
2286 return 0;
2287
2288 out_fwhandle_free:
2289 irq_domain_free_fwnode(domain_handle);
2290 out_redist_unmap:
2291 for (i = 0; i < acpi_data.nr_redist_regions; i++)
2292 if (acpi_data.redist_regs[i].redist_base)
2293 iounmap(acpi_data.redist_regs[i].redist_base);
2294 kfree(acpi_data.redist_regs);
2295 out_dist_unmap:
2296 iounmap(acpi_data.dist_base);
2297 return err;
2298 }
2299 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2300 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2301 gic_acpi_init);
2302 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2303 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2304 gic_acpi_init);
2305 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2306 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
2307 gic_acpi_init);
2308 #endif
2309