1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16
17 #include "xhci.h"
18 #include "xhci-trace.h"
19 #include "xhci-pci.h"
20
21 #define SSIC_PORT_NUM 2
22 #define SSIC_PORT_CFG2 0x880c
23 #define SSIC_PORT_CFG2_OFFSET 0x30
24 #define PROG_DONE (1 << 30)
25 #define SSIC_PORT_UNUSED (1 << 31)
26 #define SPARSE_DISABLE_BIT 17
27 #define SPARSE_CNTL_ENABLE 0xC12C
28
29 /* Device for a quirk */
30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
35
36 #define PCI_VENDOR_ID_ETRON 0x1b6f
37 #define PCI_DEVICE_ID_EJ168 0x7023
38
39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
62
63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
67 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
68 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
69 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
70 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
71 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
72
73 static const char hcd_name[] = "xhci_hcd";
74
75 static struct hc_driver __read_mostly xhci_pci_hc_driver;
76
77 static int xhci_pci_setup(struct usb_hcd *hcd);
78
79 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
80 .reset = xhci_pci_setup,
81 };
82
83 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)84 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
85 {
86 /*
87 * TODO: Implement finding debug ports later.
88 * TODO: see if there are any quirks that need to be added to handle
89 * new extended capabilities.
90 */
91
92 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
93 if (!pci_set_mwi(pdev))
94 xhci_dbg(xhci, "MWI active\n");
95
96 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
97 return 0;
98 }
99
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)100 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
101 {
102 struct pci_dev *pdev = to_pci_dev(dev);
103 struct xhci_driver_data *driver_data;
104 const struct pci_device_id *id;
105
106 id = pci_match_id(pdev->driver->id_table, pdev);
107
108 if (id && id->driver_data) {
109 driver_data = (struct xhci_driver_data *)id->driver_data;
110 xhci->quirks |= driver_data->quirks;
111 }
112
113 /* Look for vendor-specific quirks */
114 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
115 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
116 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 ||
117 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
118 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
119 pdev->revision == 0x0) {
120 xhci->quirks |= XHCI_RESET_EP_QUIRK;
121 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
122 "QUIRK: Fresco Logic xHC needs configure"
123 " endpoint cmd after reset endpoint");
124 }
125 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
126 pdev->revision == 0x4) {
127 xhci->quirks |= XHCI_SLOW_SUSPEND;
128 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
129 "QUIRK: Fresco Logic xHC revision %u"
130 "must be suspended extra slowly",
131 pdev->revision);
132 }
133 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
134 xhci->quirks |= XHCI_BROKEN_STREAMS;
135 /* Fresco Logic confirms: all revisions of this chip do not
136 * support MSI, even though some of them claim to in their PCI
137 * capabilities.
138 */
139 xhci->quirks |= XHCI_BROKEN_MSI;
140 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
141 "QUIRK: Fresco Logic revision %u "
142 "has broken MSI implementation",
143 pdev->revision);
144 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
145 }
146
147 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
148 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
149 xhci->quirks |= XHCI_BROKEN_STREAMS;
150
151 if (pdev->vendor == PCI_VENDOR_ID_NEC)
152 xhci->quirks |= XHCI_NEC_HOST;
153
154 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
155 xhci->quirks |= XHCI_AMD_0x96_HOST;
156
157 /* AMD PLL quirk */
158 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
159 xhci->quirks |= XHCI_AMD_PLL_FIX;
160
161 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
162 (pdev->device == 0x145c ||
163 pdev->device == 0x15e0 ||
164 pdev->device == 0x15e1 ||
165 pdev->device == 0x43bb))
166 xhci->quirks |= XHCI_SUSPEND_DELAY;
167
168 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
169 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
170 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
171
172 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
173 xhci->quirks |= XHCI_DISABLE_SPARSE;
174 xhci->quirks |= XHCI_RESET_ON_RESUME;
175 }
176
177 if (pdev->vendor == PCI_VENDOR_ID_AMD)
178 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
179
180 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
181 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
182 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
183 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
184 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
185 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
186
187 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
188 xhci->quirks |= XHCI_LPM_SUPPORT;
189 xhci->quirks |= XHCI_INTEL_HOST;
190 xhci->quirks |= XHCI_AVOID_BEI;
191 }
192 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
193 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
194 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
195 xhci->limit_active_eps = 64;
196 xhci->quirks |= XHCI_SW_BW_CHECKING;
197 /*
198 * PPT desktop boards DH77EB and DH77DF will power back on after
199 * a few seconds of being shutdown. The fix for this is to
200 * switch the ports from xHCI to EHCI on shutdown. We can't use
201 * DMI information to find those particular boards (since each
202 * vendor will change the board name), so we have to key off all
203 * PPT chipsets.
204 */
205 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
206 }
207 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
208 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
209 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
210 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
211 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
212 }
213 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
214 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
215 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
216 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
217 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
218 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
219 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
220 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
221 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
222 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
223 }
224 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
225 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
226 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
227 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
228 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
229 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
230 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
231 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
232 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
233 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
234 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
235 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
236 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
237 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
238 xhci->quirks |= XHCI_MISSING_CAS;
239
240 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
241 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
242 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
243 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
244 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
245 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
246 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
247 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
248 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
249 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
250 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
251 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
252 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
253 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
254
255 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
256 pdev->device == PCI_DEVICE_ID_EJ168) {
257 xhci->quirks |= XHCI_RESET_ON_RESUME;
258 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
259 xhci->quirks |= XHCI_BROKEN_STREAMS;
260 }
261 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
262 pdev->device == 0x0014) {
263 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
264 xhci->quirks |= XHCI_ZERO_64B_REGS;
265 }
266 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
267 pdev->device == 0x0015) {
268 xhci->quirks |= XHCI_RESET_ON_RESUME;
269 xhci->quirks |= XHCI_ZERO_64B_REGS;
270 }
271 if (pdev->vendor == PCI_VENDOR_ID_VIA)
272 xhci->quirks |= XHCI_RESET_ON_RESUME;
273
274 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
275 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
276 pdev->device == 0x3432)
277 xhci->quirks |= XHCI_BROKEN_STREAMS;
278
279 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
280 xhci->quirks |= XHCI_LPM_SUPPORT;
281 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
282 }
283
284 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
285 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
286 xhci->quirks |= XHCI_BROKEN_STREAMS;
287 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
288 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
289 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
290 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
291 }
292 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
293 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
294 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
295 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
296 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
297
298 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
299 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
300 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
301
302 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
303 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
304
305 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
306 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
307 pdev->device == 0x9026)
308 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
309
310 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
311 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
312 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
313 xhci->quirks |= XHCI_NO_SOFT_RETRY;
314
315 if (xhci->quirks & XHCI_RESET_ON_RESUME)
316 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
317 "QUIRK: Resetting on resume");
318 }
319
320 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)321 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
322 {
323 static const guid_t intel_dsm_guid =
324 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
325 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
326 union acpi_object *obj;
327
328 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
329 NULL);
330 ACPI_FREE(obj);
331 }
332 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)333 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
334 #endif /* CONFIG_ACPI */
335
336 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)337 static int xhci_pci_setup(struct usb_hcd *hcd)
338 {
339 struct xhci_hcd *xhci;
340 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341 int retval;
342
343 xhci = hcd_to_xhci(hcd);
344 if (!xhci->sbrn)
345 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
346
347 /* imod_interval is the interrupt moderation value in nanoseconds. */
348 xhci->imod_interval = 40000;
349
350 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
351 if (retval)
352 return retval;
353
354 if (!usb_hcd_is_primary_hcd(hcd))
355 return 0;
356
357 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
358 xhci_pme_acpi_rtd3_enable(pdev);
359
360 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
361
362 /* Find any debug ports */
363 return xhci_pci_reinit(xhci, pdev);
364 }
365
366 /*
367 * We need to register our own PCI probe function (instead of the USB core's
368 * function) in order to create a second roothub under xHCI.
369 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)370 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
371 {
372 int retval;
373 struct xhci_hcd *xhci;
374 struct usb_hcd *hcd;
375 struct xhci_driver_data *driver_data;
376 struct reset_control *reset;
377
378 driver_data = (struct xhci_driver_data *)id->driver_data;
379 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
380 retval = renesas_xhci_check_request_fw(dev, id);
381 if (retval)
382 return retval;
383 }
384
385 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
386 if (IS_ERR(reset))
387 return PTR_ERR(reset);
388 reset_control_reset(reset);
389
390 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
391 pm_runtime_get_noresume(&dev->dev);
392
393 /* Register the USB 2.0 roothub.
394 * FIXME: USB core must know to register the USB 2.0 roothub first.
395 * This is sort of silly, because we could just set the HCD driver flags
396 * to say USB 2.0, but I'm not sure what the implications would be in
397 * the other parts of the HCD code.
398 */
399 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
400
401 if (retval)
402 goto put_runtime_pm;
403
404 /* USB 2.0 roothub is stored in the PCI device now. */
405 hcd = dev_get_drvdata(&dev->dev);
406 xhci = hcd_to_xhci(hcd);
407 xhci->reset = reset;
408 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
409 pci_name(dev), hcd);
410 if (!xhci->shared_hcd) {
411 retval = -ENOMEM;
412 goto dealloc_usb2_hcd;
413 }
414
415 retval = xhci_ext_cap_init(xhci);
416 if (retval)
417 goto put_usb3_hcd;
418
419 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
420 IRQF_SHARED);
421 if (retval)
422 goto put_usb3_hcd;
423 /* Roothub already marked as USB 3.0 speed */
424
425 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
426 HCC_MAX_PSA(xhci->hcc_params) >= 4)
427 xhci->shared_hcd->can_do_streams = 1;
428
429 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
430 pm_runtime_put_noidle(&dev->dev);
431
432 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
433 pm_runtime_allow(&dev->dev);
434
435 return 0;
436
437 put_usb3_hcd:
438 usb_put_hcd(xhci->shared_hcd);
439 dealloc_usb2_hcd:
440 usb_hcd_pci_remove(dev);
441 put_runtime_pm:
442 pm_runtime_put_noidle(&dev->dev);
443 return retval;
444 }
445
xhci_pci_remove(struct pci_dev * dev)446 static void xhci_pci_remove(struct pci_dev *dev)
447 {
448 struct xhci_hcd *xhci;
449
450 xhci = hcd_to_xhci(pci_get_drvdata(dev));
451 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
452 renesas_xhci_pci_exit(dev);
453
454 xhci->xhc_state |= XHCI_STATE_REMOVING;
455
456 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
457 pm_runtime_forbid(&dev->dev);
458
459 if (xhci->shared_hcd) {
460 usb_remove_hcd(xhci->shared_hcd);
461 usb_put_hcd(xhci->shared_hcd);
462 xhci->shared_hcd = NULL;
463 }
464
465 /* Workaround for spurious wakeups at shutdown with HSW */
466 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
467 pci_set_power_state(dev, PCI_D3hot);
468
469 usb_hcd_pci_remove(dev);
470 }
471
472 #ifdef CONFIG_PM
473 /*
474 * In some Intel xHCI controllers, in order to get D3 working,
475 * through a vendor specific SSIC CONFIG register at offset 0x883c,
476 * SSIC PORT need to be marked as "unused" before putting xHCI
477 * into D3. After D3 exit, the SSIC port need to be marked as "used".
478 * Without this change, xHCI might not enter D3 state.
479 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)480 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
481 {
482 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
483 u32 val;
484 void __iomem *reg;
485 int i;
486
487 for (i = 0; i < SSIC_PORT_NUM; i++) {
488 reg = (void __iomem *) xhci->cap_regs +
489 SSIC_PORT_CFG2 +
490 i * SSIC_PORT_CFG2_OFFSET;
491
492 /* Notify SSIC that SSIC profile programming is not done. */
493 val = readl(reg) & ~PROG_DONE;
494 writel(val, reg);
495
496 /* Mark SSIC port as unused(suspend) or used(resume) */
497 val = readl(reg);
498 if (suspend)
499 val |= SSIC_PORT_UNUSED;
500 else
501 val &= ~SSIC_PORT_UNUSED;
502 writel(val, reg);
503
504 /* Notify SSIC that SSIC profile programming is done */
505 val = readl(reg) | PROG_DONE;
506 writel(val, reg);
507 readl(reg);
508 }
509 }
510
511 /*
512 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
513 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
514 */
xhci_pme_quirk(struct usb_hcd * hcd)515 static void xhci_pme_quirk(struct usb_hcd *hcd)
516 {
517 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
518 void __iomem *reg;
519 u32 val;
520
521 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
522 val = readl(reg);
523 writel(val | BIT(28), reg);
524 readl(reg);
525 }
526
xhci_sparse_control_quirk(struct usb_hcd * hcd)527 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
528 {
529 u32 reg;
530
531 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
532 reg &= ~BIT(SPARSE_DISABLE_BIT);
533 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
534 }
535
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)536 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
537 {
538 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
539 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
540 int ret;
541
542 /*
543 * Systems with the TI redriver that loses port status change events
544 * need to have the registers polled during D3, so avoid D3cold.
545 */
546 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
547 pci_d3cold_disable(pdev);
548
549 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
550 xhci_pme_quirk(hcd);
551
552 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
553 xhci_ssic_port_unused_quirk(hcd, true);
554
555 if (xhci->quirks & XHCI_DISABLE_SPARSE)
556 xhci_sparse_control_quirk(hcd);
557
558 ret = xhci_suspend(xhci, do_wakeup);
559 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
560 xhci_ssic_port_unused_quirk(hcd, false);
561
562 return ret;
563 }
564
xhci_pci_resume(struct usb_hcd * hcd,bool hibernated)565 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
566 {
567 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
568 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
569 int retval = 0;
570
571 reset_control_reset(xhci->reset);
572
573 /* The BIOS on systems with the Intel Panther Point chipset may or may
574 * not support xHCI natively. That means that during system resume, it
575 * may switch the ports back to EHCI so that users can use their
576 * keyboard to select a kernel from GRUB after resume from hibernate.
577 *
578 * The BIOS is supposed to remember whether the OS had xHCI ports
579 * enabled before resume, and switch the ports back to xHCI when the
580 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
581 * writers.
582 *
583 * Unconditionally switch the ports back to xHCI after a system resume.
584 * It should not matter whether the EHCI or xHCI controller is
585 * resumed first. It's enough to do the switchover in xHCI because
586 * USB core won't notice anything as the hub driver doesn't start
587 * running again until after all the devices (including both EHCI and
588 * xHCI host controllers) have been resumed.
589 */
590
591 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
592 usb_enable_intel_xhci_ports(pdev);
593
594 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
595 xhci_ssic_port_unused_quirk(hcd, false);
596
597 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
598 xhci_pme_quirk(hcd);
599
600 retval = xhci_resume(xhci, hibernated);
601 return retval;
602 }
603
xhci_pci_shutdown(struct usb_hcd * hcd)604 static void xhci_pci_shutdown(struct usb_hcd *hcd)
605 {
606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
607 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
608
609 xhci_shutdown(hcd);
610
611 /* Yet another workaround for spurious wakeups at shutdown with HSW */
612 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
613 pci_set_power_state(pdev, PCI_D3hot);
614 }
615 #endif /* CONFIG_PM */
616
617 /*-------------------------------------------------------------------------*/
618
619 static const struct xhci_driver_data reneses_data = {
620 .quirks = XHCI_RENESAS_FW_QUIRK,
621 .firmware = "renesas_usb_fw.mem",
622 };
623
624 /* PCI driver selection metadata; PCI hotplugging uses this */
625 static const struct pci_device_id pci_ids[] = {
626 { PCI_DEVICE(0x1912, 0x0014),
627 .driver_data = (unsigned long)&reneses_data,
628 },
629 { PCI_DEVICE(0x1912, 0x0015),
630 .driver_data = (unsigned long)&reneses_data,
631 },
632 /* handle any USB 3.0 xHCI controller */
633 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
634 },
635 { /* end: all zeroes */ }
636 };
637 MODULE_DEVICE_TABLE(pci, pci_ids);
638
639 /*
640 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
641 * load firmware, so don't encumber the xhci-pci driver with it.
642 */
643 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
644 MODULE_FIRMWARE("renesas_usb_fw.mem");
645 #endif
646
647 /* pci driver glue; this is a "new style" PCI driver module */
648 static struct pci_driver xhci_pci_driver = {
649 .name = hcd_name,
650 .id_table = pci_ids,
651
652 .probe = xhci_pci_probe,
653 .remove = xhci_pci_remove,
654 /* suspend and resume implemented later */
655
656 .shutdown = usb_hcd_pci_shutdown,
657 #ifdef CONFIG_PM
658 .driver = {
659 .pm = &usb_hcd_pci_pm_ops
660 },
661 #endif
662 };
663
xhci_pci_init(void)664 static int __init xhci_pci_init(void)
665 {
666 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
667 #ifdef CONFIG_PM
668 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
669 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
670 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
671 #endif
672 return pci_register_driver(&xhci_pci_driver);
673 }
674 module_init(xhci_pci_init);
675
xhci_pci_exit(void)676 static void __exit xhci_pci_exit(void)
677 {
678 pci_unregister_driver(&xhci_pci_driver);
679 }
680 module_exit(xhci_pci_exit);
681
682 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
683 MODULE_LICENSE("GPL");
684