1 /* 2 * platform.h 3 * 4 * Register and variable declaration of the chip. 5 * 6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 */ 22 23 #ifndef __HI_CHIP_REGS_H__ 24 #define __HI_CHIP_REGS_H__ 25 26 #define _HI3516E_V200 0x003516e200LL 27 #define _HI3516EV200_MASK 0xFFFFFFFFFFLL 28 29 /* -------------------------------------------------------------------- */ 30 #define RAM_START_ADRS 0x04010500 31 #define STACK_TRAINING 0x0401A000 32 33 /* -------------------------------------------------------------------- */ 34 #define FMC_REG_BASE 0x10000000 35 36 /* -------------------------------------------------------------------- */ 37 #define REG_BASE_SF 0x10040000 38 39 /* -------------------------------------------------------------------- */ 40 #define EMMC_REG_BASE 0x10010000 41 #define SDIO1_REG_BASE 0x10020000 42 43 /* -------------------------------------------------------------------- */ 44 #define USB3_CTRL_REG_BASE 0x10030000 45 46 /* -------------------------------------------------------------------- */ 47 #define HIUSB_OHCI_BASE 0x10030000 48 49 /* -------------------------------------------------------------------- */ 50 #define DDRC0_REG_BASE 0x11330000 51 52 /* -------------------------------------------------------------------- */ 53 #define TIMER0_REG_BASE 0x12000000 54 #define TIMER1_REG_BASE 0x12000020 55 #define TIMER2_REG_BASE 0x12001000 56 #define TIMER3_REG_BASE 0x12001020 57 58 #define REG_TIMER_RELOAD 0x0 59 #define REG_TIMER_VALUE 0x4 60 #define REG_TIMER_CONTROL 0x8 61 62 #define CFG_TIMER_CLK 3000000 63 #define CFG_TIMERBASE TIMER0_REG_BASE 64 65 /* enable timer.32bit, periodic,mask irq, 1 divider. */ 66 #define CFG_TIMER_CTRL 0xC2 67 68 /* -------------------------------------------------------------------- */ 69 /* Clock and Reset Generator REG */ 70 /* -------------------------------------------------------------------- */ 71 #define CRG_REG_BASE 0x12010000 72 73 #define REG_CRG80 0x0140 74 #define REG_CRG81 0x0144 75 #define REG_CRG91 0x016c 76 #define REG_CRG110 0x01b8 77 78 /* USB 2.0 CRG Control register offset */ 79 #define REG_USB2_CTRL REG_CRG80 80 81 /* FMC CRG register offset */ 82 #define REG_FMC_CRG REG_CRG81 83 #define FMC_SRST (0x1 << 0) 84 #define FMC_CLK_ENABLE (0x1 << 1) 85 #define FMC_CLK_SEL_MASK (0x7 << 2) 86 #define FMC_CLK_SEL_SHIFT 0x2 87 /* SDR/DDR clock */ 88 #define FMC_CLK_24M 0x0 89 #define FMC_CLK_100M 0x1 90 #define FMC_CLK_150M 0x2 91 92 #define FMC_CLK_200M 0x3 93 94 /* Only DDR clock */ 95 #define FMC_CLK_300M 0x4 96 #define FMC_CLK_360M 0x5 97 98 #define fmc_clk_sel(_clk) \ 99 (((_clk) << FMC_CLK_SEL_SHIFT) & FMC_CLK_SEL_MASK) 100 #define get_fmc_clk_type(_reg) \ 101 (((_reg) & FMC_CLK_SEL_MASK) >> FMC_CLK_SEL_SHIFT) 102 103 /* Ethernet CRG register offset */ 104 #define REG_ETH_CRG REG_CRG91 105 #define REG_ETH_MAC_IF 0x8c 106 107 /* Uart CRG register offset */ 108 #define REG_UART_CRG REG_CRG110 109 #define uart_clk_sel(_clk) (((_clk) & 0x3) << 18) 110 #define UART_CLK_SEL_MASK (0x3 << 18) 111 #define UART_CLK_APB 0 112 #define UART_CLK_24M 1 113 #define UART_CLK_2M 2 114 115 /* SDIO0 CRG register offset */ 116 #define REG_SDIO0_CRG (CRG_REG_BASE + 0x238) 117 118 /* eMMC CRG register offset */ 119 #define REG_EMMC_CRG (CRG_REG_BASE + 0x1f4) 120 #define mmc_clk_sel(_clk) (((_clk) & 0x7) << 24) 121 #define MMC_CLK_SEL_MASK (0x7 << 24) 122 #define get_mmc_clk_type(_reg) (((_reg) >> 24) & 0x7) 123 124 /* -------------------------------------------------------------------- */ 125 /* System Control REG */ 126 /* -------------------------------------------------------------------- */ 127 #define SYS_CTRL_REG_BASE 0x12020000 128 #define REG_BASE_SCTL SYS_CTRL_REG_BASE 129 #define REG_SC_SYSSTAT 0x8c 130 #define spi_input_sle(x) (((x) >> 16) & 0x1) 131 132 /* System Control register offset */ 133 #define REG_SC_CTRL 0x0000 134 #define sc_ctrl_timer0_clk_sel(_clk) (((_clk) & 0x1) << 16) 135 #define TIMER0_CLK_SEL_MASK (0x1 << 16) 136 #define TIMER_CLK_3M 0 137 #define TIMER_CLK_BUS 1 138 #define SC_CTRL_REMAP_CLEAR (0x1 << 8) 139 140 /* System soft reset register offset */ 141 #define REG_SC_SYSRES 0x0004 142 143 /* System Status register offset */ 144 #define REG_SYSSTAT 0x008c 145 /* bit[7]=0: 3-Byte address mode; bit[7]=1: 4-Byte address mode */ 146 #define get_spi_nor_addr_mode(_reg) (((_reg) >> 7) & 0x1) 147 /* bit[6]=0; SPI nor flash; bit[6]=1: SPI nand flash */ 148 #define get_spi_device_type(_reg) (((_reg) >> 10) & 0x1) 149 /* bit[4]=0 SPI; bit[4]=1: EMMC */ 150 #define get_sys_boot_mode(_reg) (((_reg) >> 4) & 0x1) 151 #define BOOT_FROM_SPI 0 152 #define BOOT_FROM_SPI_NAND 1 153 #define BOOT_FROM_NAND 2 154 #define BOOT_FROM_EMMC 1 155 #define NF_BOOTBW_MASK (1 << 11) 156 157 158 #define REG_SC_GEN0 0x0138 159 #define REG_SC_GEN1 0x013c 160 #define REG_SC_GEN2 0x0140 161 #define REG_SC_GEN3 0x0144 162 #define REG_SC_GEN4 0x0148 163 #define REG_SC_GEN9 0x0154 164 165 /********** Communication Register and flag used by bootrom *************/ 166 #define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1) 167 #define START_MAGIC 0x444f574e 168 #define SELF_BOOT_TYPE_USBDEV 0x2 /* debug */ 169 170 /* -------------------------------------------------------------------- */ 171 /* Peripheral Control REG */ 172 /* -------------------------------------------------------------------- */ 173 #define MISC_REG_BASE 0x12028000 174 175 #define MISC_CTRL17 0x0044 176 #define MISC_CTRL18 0x48 177 #define MISC_CTRL7 0x001C 178 #define MISC_CTRL8 0x0020 179 #define MISC_CTRL9 0x0024 180 181 #define EMMC_ISO_EN (0x1 << 16) 182 #define RG_EMMC_LHEN_IN (0x3f << 17) 183 184 /* USB 2.0 MISC Control register offset */ 185 #define REG_USB2_CTRL0 MISC_CTRL7 186 /* base on needs #define REG_USB2_CTRL1 MISC_CTRL9 */ 187 188 /* FEPHY Control register offset */ 189 #define REG_FEPHY_CTRL0 MISC_CTRL8 190 #define REG_FEPHY_CTRL1 MISC_CTRL9 191 192 /* -------------------------------------------------------------------- */ 193 #define IO_CONFIG_REG_BASE 0x12050000 194 195 /* -------------------------------------------------------------------- */ 196 #define UART0_REG_BASE 0x12040000 197 #define UART1_REG_BASE 0x12041000 198 #define UART2_REG_BASE 0x12042000 199 200 /* -------------------------------------------------------------------- */ 201 #define GPIO0_REG_BASE 0x120B0000 202 #define GPIO1_REG_BASE 0x120B1000 203 #define GPIO2_REG_BASE 0x120B2000 204 #define GPIO3_REG_BASE 0x120B3000 205 #define GPIO4_REG_BASE 0x120B4000 206 #define GPIO5_REG_BASE 0x120B5000 207 #define GPIO6_REG_BASE 0x120B6000 208 #define GPIO7_REG_BASE 0x120B7000 209 #define GPIO8_REG_BASE 0x120B8000 210 #define GPIO9_REG_BASE 0x120B9000 211 212 #define FMC_MEM_BASE 0x14000000 213 #define FMC_TEXT_ADRS FMC_MEM_BASE 214 #define DDR_MEM_BASE 0x40000000 215 #define HW_DEC_INTR 86 216 /*----------------------------------------------------------------------- 217 * EMMC / SD 218 * ----------------------------------------------------------------------*/ 219 /* SDIO0 REG */ 220 #define SDIO0_BASE_REG 0x10010000 221 222 /* EMMC REG */ 223 #define EMMC_BASE_REG 0x10010000 224 225 #define REG_BASE_PERI_CTRL REG_BASE_SCTL 226 #define REG_BASE_IO_CONFIG IO_CONFIG_REG_BASE 227 228 #define MMC_IOMUX_START_ADDR 0xF8 229 #define MMC_IOMUX_END_ADDR 0x13C 230 #define MMC_IOMUX_CTRL_MASK (1<<0 | 1<<1) 231 #define MMC_IOMUX_CTRL (1<<1) 232 233 #define SYSCNT_REG_BASE 0x12050000 234 #define SYSCNT_ENABLE_REG 0x0 235 #define SYSCNT_FREQ_REG 0x20 236 #define SYSCNT_FREQ 50000000 237 238 #define REG_BASE_SYSCNT SYSCNT_REG_BASE 239 #define CNTCR 0x0 240 #define CNTFID0 0x20 241 242 /* ---------------------------------------------------------*/ 243 #define NUM_0 0 244 #define NUM_1 1 245 #define NUM_2 2 246 #define NUM_3 3 247 #define NUM_4 4 248 #define NUM_5 5 249 #define NUM_6 6 250 #define NUM_7 7 251 #define NUM_8 8 252 #define NUM_9 9 253 254 #endif /* End of __HI_CHIP_REGS_H__ */ 255 256