1 #ifndef __HI_CHIP_REGS_H__ 2 #define __HI_CHIP_REGS_H__ 3 4 /* -------------------------------------------------------------------- */ 5 /* Communication Register and flag used by bootrom */ 6 /* -------------------------------------------------------------------- */ 7 #define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1) 8 #define START_MAGIC (0x444f574e) 9 #define SELF_BOOT_TYPE_USBDEV 0x2 10 #define CP_STEP1_ADDR 0x04010500 11 #define PCIE_SLAVE_BOOT_CTL_REG 0x0134 12 #define DDR_INIT_DOWNLOAD_OK_FLAG 0xDCDFF001 /* step1:Ddrinit Code Download Finished Flag: DCDFF001 */ 13 #define DDR_INIT_EXCUTE_OK_FLAG 0xDCEFF002 /* step2:Ddrinit Code Excute Finished Flag: DCEFF002 */ 14 #define UBOOT_DOWNLOAD_OK_FLAG 0xBCDFF003 /* step3:Boot Code Download Finished Flag: BCDFF003 */ 15 16 /* -------------------------------------------------------------------- */ 17 /* System Control */ 18 /* -------------------------------------------------------------------- */ 19 #define SYS_CTRL_REG_BASE 0x11020000 20 #define REG_BASE_SCTL SYS_CTRL_REG_BASE 21 #define REG_SC_CTRL 0x0000 22 #define REG_SC_SYSRES 0x0004 23 #define REG_PERISTAT 0x0030 24 #define REG_SYSSTAT 0x0018 25 #define EMMC_BOOT_8BIT (0x1 << 11) 26 #define REG_PERI_EMMC_STAT 0x0404 27 #define mmc_boot_clk_sel(val) ((val) & 0x3) 28 #define MMC_BOOT_CLK_50M 0x2 29 #define EMMC_NORMAL_MODE (0x1 << 3) 30 #define get_spi_nor_addr_mode(_reg) (((_reg) >> 11) & 0x1) 31 #define get_spi_device_type(_reg) (((_reg) >> 2) & 0x1) 32 #define get_sys_boot_mode(_reg) (((_reg) >> 2) & 0x3) 33 #define BOOT_FROM_SPI 0 34 #define BOOT_FROM_SPI_NAND 1 35 #define BOOT_FROM_NAND 2 36 #define BOOT_FROM_EMMC 3 37 38 #define REG_SC_GEN0 0x0138 39 #define REG_SC_GEN1 0x013c 40 #define REG_SC_GEN2 0x0140 41 #define REG_SC_GEN3 0x0144 42 #define REG_SC_GEN4 0x0148 43 #define REG_SC_GEN9 0x0154 44 #define REG_SC_GEN20 0x0090 45 46 /* -------------------------------------------------------------------- */ 47 /* CPU SUBSYS */ 48 /* -------------------------------------------------------------------- */ 49 #define REG_CRG_CLUSTER0_CLK_RST 0x0190 /* CPU SUBSYS clock and reset control*/ 50 #define CLUSTER0_GLB_SRST_REQ (0x1 << 17) 51 52 #define REG_PERI_CPU_RVBARADDR_A53UP 0x11024004 53 #define REG_PERI_CPU_RVBARADDR_SOC 0x12030020 54 55 #define REG_CRG_CLUSTER1_CLK_RST 0x0194 56 #define CLUSTER1_GLB_SRST_REQ (0x1 << 9) 57 #define CLUSTER1_GLB_CKEN (0x1 << 8) 58 59 /* -------------------------------------------------------------------- */ 60 /* CRG */ 61 /* -------------------------------------------------------------------- */ 62 #define CRG_REG_BASE 0x11010000 63 64 /* -------------------------------------------------------------------- */ 65 /* Peripheral Control REG */ 66 /* -------------------------------------------------------------------- */ 67 #define MISC_REG_BASE 0x11024000 68 69 #define USB_CTRL6 0x194 70 #define U3_PORT_DISABLE (0x1 << 12) 71 72 /* -------------------------------------------------------------------- */ 73 /* IO configuration REG:mux and driver */ 74 /* -------------------------------------------------------------------- */ 75 #define AHB_IO_CONFIG_REG_BASE 0x11180000 76 #define IO_CONFIG_REG_BASE AHB_IO_CONFIG_REG_BASE 77 78 /* -------------------------------------------------------------------- */ 79 /* TIMER */ 80 /* -------------------------------------------------------------------- */ 81 #define TIMER0_REG_BASE 0x11000000 82 #define REG_TIMER_RELOAD 0x0 83 #define REG_TIMER_VALUE 0x4 84 #define REG_TIMER_CONTROL 0x8 85 #define CFG_TIMER_CLK (3000000) 86 #define CFG_TIMERBASE TIMER0_REG_BASE 87 /* enable timer.32bit, periodic,mask irq, 1 divider.*/ 88 #define CFG_TIMER_CTRL 0xC2 89 90 /* -------------------------------------------------------------------- */ 91 /* UART */ 92 /* -------------------------------------------------------------------- */ 93 #define UART0_REG_BASE 0x11040000 94 #define UART1_REG_BASE 0x11041000 95 #define UART2_REG_BASE 0x11042000 96 #define UART3_REG_BASE 0x11043000 97 98 #define UATR_IO_CFG_BASE 0x102f0000 99 #define UART0_RXD_IOCFG_OFST 0x20 100 #define UART0_TXD_IOCFG_OFST 0x24 101 /* -------------------------------------------------------------------- */ 102 /* DDRC */ 103 /* -------------------------------------------------------------------- */ 104 #define STACK_TRAINING 0x0401A000 105 #define DDRC0_REG_BASE 0x11130000 106 #define DDR_MEM_BASE 0x40000000 107 108 /* -------------------------------------------------------------------- */ 109 /* FMC */ 110 /* -------------------------------------------------------------------- */ 111 #define FMC_REG_BASE 0x10000000 112 #define FMC_MEM_BASE 0x0f000000 113 114 /* FMC CRG register offset */ 115 #define REG_FMC_CRG 0x3f40 116 117 #define fmc_clk_sel(_clk) (((_clk) & 0x7) << 12) 118 #define FMC_CLK_SEL_MASK (0x7 << 12) 119 #define get_fmc_clk_type(_reg) (((_reg) >> 12) & 0x7) 120 121 /* SDR/DDR clock */ 122 #define FMC_CLK_24M 0 123 #define FMC_CLK_100M 1 124 #define FMC_CLK_150M 3 125 #define FMC_CLK_200M 4 126 #define FMC_CLK_257M 5 127 /* Only DDR clock */ 128 #define FMC_CLK_300M 6 129 #define FMC_CLK_400M 7 130 131 #define FMC_CLK_ENABLE (0x1 << 4) 132 #define FMC_SOFT_RST_REQ (0x1 << 0) 133 134 /*--------------------------------------------------------------------- */ 135 /* EMMC / SD */ 136 /* -------------------------------------------------------------------- */ 137 138 /* eMMC CRG register offset */ 139 #define REG_EMMC_CRG (CRG_REG_BASE + 0x34c0) 140 #define mmc_clk_sel(_clk) (((_clk) & 0x7) << 24) 141 #define MMC_CLK_SEL_MASK (0x7 << 24) 142 #define GET_MMC_CLK_TYPE(_reg) (((_reg) >> 24) & 0x7) 143 #define REG_SAVE_HCS 0x11020300 144 145 /* EMMC REG*/ 146 #define EMMC_BASE_REG 0x10020000 147 #define NO_EMMC_PHY 1 148 149 #define NF_BOOTBW_MASK (1 << 11) 150 #define REG_BASE_PERI_CTRL REG_BASE_SCTL 151 #define REG_BASE_IO_CONFIG IO_CONFIG_REG_BASE 152 153 /* SDIO0 REG */ 154 #define REG_SDIO0_CRG REG_EMMC_CRG 155 #define SDIO0_BASE_REG EMMC_BASE_REG 156 157 /*--------------------------------------------------------------------- */ 158 /* HIGMAC */ 159 /* -------------------------------------------------------------------- */ 160 #define HIGMAC0_IOBASE 0x10290000 161 #define HIGMAC1_IOBASE 0x102A0000 162 163 /* Ethernet MAC0 MAC_IF CRG register offset */ 164 #define REG_ETH0_MACIF_CRG 0x37c0 165 /* Ethernet MAC0 MAC_If CRG register bit map*/ 166 #define BIT_MACIF0_RST BIT(0) 167 #define BIT_GMACIF0_CLK_EN BIT(4) 168 #define BIT_RMII0_CLKSEL_PAD BIT(12) 169 170 /* Ethernet MAC0 GSF CRG register offset */ 171 #define REG_ETH0_GSF_CRG 0x37c4 172 /* Ethernet MAC0 GSF CRG register bit map*/ 173 #define BIT_GMAC0_RST BIT(0) 174 #define BIT_GMAC0_CLK_EN BIT(4) 175 176 /* Ethernet MAC0 PHY CRG register offset */ 177 #define REG_ETH0_PHY_CRG 0x37cc 178 /* Ethernet MAC0 PHY CRG register bit map*/ 179 #define BIT_EXT_PHY0_RST BIT(0) 180 #define BIT_EXT_PHY0_CLK_SELECT BIT(12) 181 182 183 /* Ethernet MAC1 MAC_IF CRG register offset */ 184 #define REG_ETH1_MACIF_CRG 0x3800 185 /* Ethernet MAC1 MAC_If CRG register bit map*/ 186 #define BIT_MACIF1_RST BIT(0) 187 #define BIT_GMACIF1_CLK_EN BIT(4) 188 #define BIT_RMII1_CLKSEL_PAD BIT(12) 189 190 /* Ethernet MAC1 GSF CRG register offset */ 191 #define REG_ETH1_GSF_CRG 0x3804 192 /* Ethernet MAC1 GSF CRG register bit map*/ 193 #define BIT_GMAC1_RST BIT(0) 194 #define BIT_GMAC1_CLK_EN BIT(4) 195 196 /* Ethernet MAC1 PHY CRG register offset */ 197 #define REG_ETH1_PHY_CRG 0x380c 198 /* Ethernet MAC1 PHY CRG register bit map*/ 199 #define BIT_EXT_PHY1_RST BIT(0) 200 #define BIT_EXT_PHY1_CLK_SELECT BIT(12) 201 202 #define PHY0_CLK_25M 0 203 #define PHY0_CLK_50M BIT_EXT_PHY0_CLK_SELECT 204 #define PHY1_CLK_25M 0 205 #define PHY1_CLK_50M BIT_EXT_PHY1_CLK_SELECT 206 207 #define HIGMAC_MACIF0_CTRL (HIGMAC0_IOBASE + 0x300c) 208 #define HIGMAC_MACIF1_CTRL (HIGMAC1_IOBASE + 0x300c) 209 #define HIGMAC_DUAL_MAC_CRF_ACK_TH (HIGMAC0_IOBASE + 0x3004) 210 211 /* Configure higmac pinout parameters in software */ 212 #define CFG_NET_PINCTRL 213 214 /* MDIO0 pinctrl phyical addr */ 215 #define PHY_ADDR_MDCK0 0x017C70138 216 #define PHY_ADDR_MDIO0 0x017C7013C 217 /* MDIO1 pinctrl phyical addr */ 218 #define PHY_ADDR_MDCK1 0x017C701E0 219 #define PHY_ADDR_MDIO1 0x017C70200 220 221 /* PHY0 pinctrl phyical addr */ 222 #define PHY_ADDR_EPHY0_CLK 0x017C7011C 223 #define PHY_ADDR_EPHY0_RSTN 0x017C7014C 224 /* PHY1 pinctrl phyical addr */ 225 #define PHY_ADDR_EPHY1_CLK 0x017C701F0 226 #define PHY_ADDR_EPHY1_RSTN 0x017C701DC 227 228 /* RGMII0 pinctrl phyical addr */ 229 #define PHY_ADDR_RGMII0_TXCKOUT 0x017C7012C 230 #define PHY_ADDR_RGMII0_TXD0 0x017C70114 231 #define PHY_ADDR_RGMII0_TXD1 0x017C70118 232 #define PHY_ADDR_RGMII0_TXD2 0x017C70120 233 #define PHY_ADDR_RGMII0_TXD3 0x017C70124 234 #define PHY_ADDR_RGMII0_TXEN 0x017C70128 235 #define PHY_ADDR_RGMII0_RXCK 0x017C70154 236 #define PHY_ADDR_RGMII0_RXD0 0x017C70144 237 #define PHY_ADDR_RGMII0_RXD1 0x017C70140 238 #define PHY_ADDR_RGMII0_RXD2 0x017C70134 239 #define PHY_ADDR_RGMII0_RXD3 0x017C70130 240 #define PHY_ADDR_RGMII0_RXDV 0x017C70150 241 242 /* RGMII1 pinctrl phyical addr */ 243 #define PHY_ADDR_RGMII1_TXCKOUT 0x017C70218 244 #define PHY_ADDR_RGMII1_TXD0 0x017C7020C 245 #define PHY_ADDR_RGMII1_TXD1 0x017C70214 246 #define PHY_ADDR_RGMII1_TXD2 0x017C701F4 247 #define PHY_ADDR_RGMII1_TXD3 0x017C70208 248 #define PHY_ADDR_RGMII1_TXEN 0x017C70210 249 #define PHY_ADDR_RGMII1_RXCK 0x017C701EC 250 #define PHY_ADDR_RGMII1_RXD0 0x017C701E4 251 #define PHY_ADDR_RGMII1_RXD1 0x017C70204 252 #define PHY_ADDR_RGMII1_RXD2 0x017C701FC 253 #define PHY_ADDR_RGMII1_RXD3 0x017C701F8 254 #define PHY_ADDR_RGMII1_RXDV 0x017C701E8 255 256 /* RMII0 pinctrl phyical addr */ 257 #define PHY_ADDR_RMII0_CLK 0x017C7012C 258 #define PHY_ADDR_RMII0_TXD0 0x017C70114 259 #define PHY_ADDR_RMII0_TXD1 0x017C70118 260 #define PHY_ADDR_RMII0_TXEN 0x017C70128 261 #define PHY_ADDR_RMII0_RXD0 0x017C70144 262 #define PHY_ADDR_RMII0_RXD1 0x017C70140 263 #define PHY_ADDR_RMII0_RXDV 0x017C70150 264 265 /* RMII1 pinctrl phyical addr */ 266 #define PHY_ADDR_RMII1_CLK 0x017C70218 267 #define PHY_ADDR_RMII1_TXD0 0x017C7020C 268 #define PHY_ADDR_RMII1_TXD1 0x017C70214 269 #define PHY_ADDR_RMII1_TXEN 0x017C70210 270 #define PHY_ADDR_RMII1_RXD0 0x017C701E4 271 #define PHY_ADDR_RMII1_RXD1 0x017C70204 272 #define PHY_ADDR_RMII1_RXDV 0x017C701E8 273 274 /* MDIO0 config value */ 275 #define VALUE_MDCK0 0x1002 276 #define VALUE_MDIO0 0x1002 277 /* MDIO1 config value */ 278 #define VALUE_MDCK1 0x1022 279 #define VALUE_MDIO1 0x1032 280 281 /* PHY0 config value */ 282 #define VALUE_EPHY0_CLK 0x1012 283 #define VALUE_EPHY0_RSTN 0x1002 284 /* PHY1 config value */ 285 #define VALUE_EPHY1_CLK 0x1002 286 #define VALUE_EPHY1_RSTN 0x1002 287 288 /* RGMII0 config value */ 289 #define VALUE_RGMII0_TXCKOUT 0x1042 290 #define VALUE_RGMII0_TXD0 0x1052 291 #define VALUE_RGMII0_TXD1 0x1052 292 #define VALUE_RGMII0_TXD2 0x1052 293 #define VALUE_RGMII0_TXD3 0x1052 294 #define VALUE_RGMII0_TXEN 0x1052 295 #define VALUE_RGMII0_RXCK 0x1002 296 #define VALUE_RGMII0_RXD0 0x1002 297 #define VALUE_RGMII0_RXD1 0x1002 298 #define VALUE_RGMII0_RXD2 0x1002 299 #define VALUE_RGMII0_RXD3 0x1002 300 #define VALUE_RGMII0_RXDV 0x1002 301 302 /* RGMII1 config value */ 303 #define VALUE_RGMII1_TXCKOUT 0x1042 304 #define VALUE_RGMII1_TXD0 0x1052 305 #define VALUE_RGMII1_TXD1 0x1052 306 #define VALUE_RGMII1_TXD2 0x1052 307 #define VALUE_RGMII1_TXD3 0x1052 308 #define VALUE_RGMII1_TXEN 0x1052 309 #define VALUE_RGMII1_RXCK 0x1032 310 #define VALUE_RGMII1_RXD0 0x1032 311 #define VALUE_RGMII1_RXD1 0x1032 312 #define VALUE_RGMII1_RXD2 0x1032 313 #define VALUE_RGMII1_RXD3 0x1032 314 #define VALUE_RGMII1_RXDV 0x1032 315 316 /* RMII0 config value */ 317 #define VALUE_RMII0_CLK 0x1053 318 #define VALUE_RMII0_TXD0 0x1052 319 #define VALUE_RMII0_TXD1 0x1052 320 #define VALUE_RMII0_TXEN 0x1052 321 #define VALUE_RMII0_RXD0 0x1032 322 #define VALUE_RMII0_RXD1 0x1032 323 #define VALUE_RMII0_RXDV 0x1032 324 325 /* RMII1 config value */ 326 #define VALUE_RMII1_CLK 0x1053 327 #define VALUE_RMII1_TXD0 0x1052 328 #define VALUE_RMII1_TXD1 0x1052 329 #define VALUE_RMII1_TXEN 0x1052 330 #define VALUE_RMII1_RXD0 0x1032 331 #define VALUE_RMII1_RXD1 0x1032 332 #define VALUE_RMII1_RXDV 0x1032 333 334 /* -------------------------------------------------------------------- */ 335 /* USB */ 336 /* -------------------------------------------------------------------- */ 337 #define USB3_CTRL_REG_BASE 0x10300000 338 #define USB2_CTRL_REG_BASE 0x10340000 339 #define USB2_PHY2_BASE 0x10310000 340 #define USB2_PHY1_BASE 0x10350000 341 #define USB2_PHY0_BASE 0x10330000 342 #define USB_SYS_CTRL_BASE 0x11020444 343 #define USB_MISC_REG_BASE 0x110241c8 344 345 /* USB CRG register offset and config */ 346 #define PERI_CRG3632 0x38c0 347 #define USB2_0_UTMI_CKEN (0x1 << 8) 348 349 #define PERI_CRG3636 0x38d0 350 #define USB2_PHY0_REQ (0x1 << 0) 351 #define USB2_PHY0_TREQ (0x1 << 1) 352 #define USB2_PHY0_APB_SRST_REQ (0x1 << 2) 353 #define USB2_PHY0_XTAL_CKEN (0x1 << 4) 354 355 #define PERI_CRG3640 0x38e0 356 #define USB2_1_SRST_REQ (0x1 << 0) 357 #define USB2_1_BUS_CKEN (0x1 << 4) 358 #define USB2_1_REF_CKEN (0x1 << 5) 359 #define USB2_1_UTMI_CKEN (0x1 << 8) 360 361 #define PERI_CRG3644 0x38f0 362 #define USB2_PHY1_REQ (0x1 << 0) 363 #define USB2_PHY1_TREQ (0x1 << 1) 364 #define USB2_PHY1_APB_SRST_REQ (0x1 << 2) 365 #define USB2_PHY1_XTAL_CKEN (0x1 << 4) 366 367 #define PERI_CRG3664 0x3940 368 #define USB3_SRST_REQ (0x1 << 0) 369 #define USB3_BUS_CKEN (0x1 << 4) 370 #define USB3_REF_CKEN (0x1 << 5) 371 #define USB3_SUSPEND_CKEN (0x1 << 6) 372 #define USB3_UTMI_CKEN (0x1 << 8) 373 #define USB3_PIPE_CKEN (0x1 << 12) 374 375 #define PERI_CRG3672 0x3960 376 #define USB2_PHY2_REQ (0x1 << 0) 377 #define USB2_PHY2_TREQ (0x1 << 1) 378 #define USB2_PHY2_APB_SRST_REQ (0x1 << 2) 379 #define USB2_PHY2_XTAL_CKEN (0x1 << 4) 380 381 #define PERI_CRG3676 0x3970 382 #define COMBPHY0_SRST_REQ (0x1 << 0) 383 #define COMBPHY0_REF_CKEN (0x1 << 4) 384 385 #define USB2_CTRL0_CFG (CRG_REG_BASE + PERI_CRG3632) 386 #define USB2_PHY0_CFG (CRG_REG_BASE + PERI_CRG3636) 387 #define USB2_CTRL1_CFG (CRG_REG_BASE + PERI_CRG3640) 388 #define USB2_PHY1_CFG (CRG_REG_BASE + PERI_CRG3644) 389 #define USB3_PHY_CFG (CRG_REG_BASE + PERI_CRG3664) 390 #define USB2_PHY2_CFG (CRG_REG_BASE + PERI_CRG3672) 391 #define USB3_COMBPHY_CFG (CRG_REG_BASE + PERI_CRG3676) 392 393 /* USB PHY register offset and config */ 394 #define PHY_PLL_OFFSET 0x14 395 #define PHY_PLL_ENABLE (0x3 << 0) 396 397 #define U2_ANA_CFG0 0x0 398 #define HSTX_MBIAS_MASK (0xf << 0) 399 #define ana_cfg0_val(p) ((p) & (~HSTX_MBIAS_MASK)) 400 #define U2_2_HSTX_MBIAS (0x3 << 0) 401 #define U2_1_HSTX_MBIAS (0xb << 0) 402 #define U2_0_HSTX_MBIAS (0xb << 0) 403 404 #define U2_ANA_CFG2 0x8 405 #define VDISCREF_SEL_MASK (0x7 << 16) 406 #define ana_cfg2_val(p) ((p) & (~VDISCREF_SEL_MASK)) 407 #define U2_2_VDISCREF_SEL (0x2 << 16) 408 #define U2_1_VDISCREF_SEL (0x5 << 16) 409 #define U2_0_VDISCREF_SEL (0x5 << 16) 410 #define U2_TEST_TX (0x1 << 20) 411 412 #define U2_TRIM_VAL_MIN 0x09 413 #define U2_TRIM_VAL_MAX 0x1d 414 #define RT_TRIM_VAL_MASK 0x1f 415 #define usb2_2_trim_val(p) (((p) >> 10) & RT_TRIM_VAL_MASK) 416 #define usb2_1_trim_val(p) (((p) >> 5) & RT_TRIM_VAL_MASK) 417 #define usb2_0_trim_val(p) (((p) >> 0) & RT_TRIM_VAL_MASK) 418 419 #define usb2_rt_trim_clr(p) ((p) & (~(RT_TRIM_VAL_MASK << 8))) 420 #define usb2_rt_trim_set(p) ((p) << 8) 421 422 #define U2_ANA_CFG3 0xc 423 #define SLEW_RATE_OPT_MASK (0x3 << 20) 424 #define ana_cfg3_val(p) ((p) & (~SLEW_RATE_OPT_MASK)) 425 #define U2_2_SLEW_RATE_OPT (0x1 << 20) 426 #define U2_1_SLEW_RATE_OPT (0x1 << 20) 427 #define U2_0_SLEW_RATE_OPT (0x1 << 20) 428 429 #define U2_ANA_CFG4 0x10 430 #define VTXREF_SEL_MASK (0x7 << 4) 431 #define ana_cfg4_val(p) ((p) & (~VTXREF_SEL_MASK)) 432 #define U2_VTXREF_SEL (0x6 << 4) 433 #define U2_FLS_EDGE_MODE (0x1 << 13) 434 435 #define PI_CURRENT_TRIM_ENABLE 0x11100 436 #define PI_CURRENT_TRIM_VAL 0x11101 437 #define TX_SWING_COMP_ENABLE 0xc1200 438 #define TX_SWING_COMP_VAL 0xc1201 439 440 /* -------------------------------------------------------------------- */ 441 /* PCIE */ 442 /* -------------------------------------------------------------------- */ 443 #define SYS_SATA 0x8c 444 #define PCIE_MODE 12 445 446 #define PERI_CRG98 0x188 447 #define phy0_srs_req 0 448 #define phy0_srs_req_sel 1 449 #define phy1_srs_req 16 450 #define phy1_srs_req_sel 17 451 452 #define MISC_CTRL5 0x14 453 454 /* -------------------------------------------------------------------- */ 455 /* GZIP */ 456 /* -------------------------------------------------------------------- */ 457 #define HW_DEC_INTR (183) 458 459 /* --------------------------------------------------------- */ 460 #define NUM_0 0 461 #define NUM_1 1 462 #define NUM_2 2 463 #define NUM_3 3 464 #define NUM_4 4 465 #define NUM_5 5 466 #define NUM_6 6 467 #define NUM_7 7 468 #define NUM_8 8 469 #define NUM_9 9 470 471 #endif /* End of __HI_CHIP_REGS_H__ */ 472