1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017-2018 NXP
4 */
5 #include <common.h>
6 #include <dm.h>
7 #include <spl.h>
8 #include <fsl_esdhc.h>
9
10 #include <asm/io.h>
11 #include <asm/gpio.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sci/sci.h>
14 #include <asm/arch/imx8-pins.h>
15 #include <asm/arch/iomux.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
20 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
21 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
22 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
23
24 #define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
25 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
26 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
27 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
28
29 #define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
30 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
31 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
32 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
33
34 #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
35 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
36 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
37 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
38
39 #define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
40 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
41 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
42 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
43
44 #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
45 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
46 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
47 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
48
49 #define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
50 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
51 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
52 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
53
54 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
55 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
56 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
57 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
58 #ifdef CONFIG_FSL_ESDHC
59
60 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
61 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
62
63 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
64 {USDHC1_BASE_ADDR, 0, 8},
65 {USDHC2_BASE_ADDR, 0, 4},
66 {USDHC3_BASE_ADDR, 0, 4},
67 };
68
69 static iomux_cfg_t emmc0[] = {
70 SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
71 SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
72 SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
73 SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
74 SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
75 SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
76 SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
77 SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
78 SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
79 SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
80 SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
81 SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
82 };
83
84 static iomux_cfg_t usdhc2_sd[] = {
85 SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
86 SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
87 SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
88 SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
89 SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
90 SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
91 SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
92 SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
93 SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
94 };
95
board_mmc_init(bd_t * bis)96 int board_mmc_init(bd_t *bis)
97 {
98 int i, ret;
99
100 /*
101 * According to the board_mmc_init() the following map is done:
102 * (U-Boot device node) (Physical Port)
103 * mmc0 USDHC1
104 * mmc1 USDHC2
105 * mmc2 USDHC3
106 */
107 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
108 switch (i) {
109 case 0:
110 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
111 if (ret != SC_ERR_NONE)
112 return ret;
113
114 imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
115 init_clk_usdhc(0);
116 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
117 break;
118 case 1:
119 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
120 if (ret != SC_ERR_NONE)
121 return ret;
122 ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
123 if (ret != SC_ERR_NONE)
124 return ret;
125
126 imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
127 init_clk_usdhc(2);
128 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
129 gpio_request(USDHC2_CD_GPIO, "sd2_cd");
130 gpio_direction_input(USDHC2_CD_GPIO);
131 break;
132 default:
133 printf("Warning: you configured more USDHC controllers"
134 "(%d) than supported by the board\n", i + 1);
135 return 0;
136 }
137 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
138 if (ret) {
139 printf("Warning: failed to initialize mmc dev %d\n", i);
140 return ret;
141 }
142 }
143
144 return 0;
145 }
146
board_mmc_getcd(struct mmc * mmc)147 int board_mmc_getcd(struct mmc *mmc)
148 {
149 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
150 int ret = 0;
151
152 switch (cfg->esdhc_base) {
153 case USDHC1_BASE_ADDR:
154 ret = 1;
155 break;
156 case USDHC2_BASE_ADDR:
157 ret = !gpio_get_value(USDHC1_CD_GPIO);
158 break;
159 case USDHC3_BASE_ADDR:
160 ret = !gpio_get_value(USDHC2_CD_GPIO);
161 break;
162 }
163
164 return ret;
165 }
166
167 #endif /* CONFIG_FSL_ESDHC */
168
spl_board_init(void)169 void spl_board_init(void)
170 {
171 #if defined(CONFIG_SPL_SPI_SUPPORT)
172 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
173 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
174 puts("Warning: failed to initialize FSPI0\n");
175 }
176 }
177 #endif
178
179 puts("Normal Boot\n");
180 }
181
spl_board_prepare_for_boot(void)182 void spl_board_prepare_for_boot(void)
183 {
184 #if defined(CONFIG_SPL_SPI_SUPPORT)
185 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
186 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
187 puts("Warning: failed to turn off FSPI0\n");
188 }
189 }
190 #endif
191 }
192
193 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)194 int board_fit_config_name_match(const char *name)
195 {
196 /* Just empty function now - can't decide what to choose */
197 debug("%s: %s\n", __func__, name);
198
199 return 0;
200 }
201 #endif
202
board_init_f(ulong dummy)203 void board_init_f(ulong dummy)
204 {
205 /* Clear global data */
206 memset((void *)gd, 0, sizeof(gd_t));
207
208 arch_cpu_init();
209
210 board_early_init_f();
211
212 timer_init();
213
214 preloader_console_init();
215
216 /* Clear the BSS. */
217 memset(__bss_start, 0, __bss_end - __bss_start);
218
219 board_init_r(NULL, 0);
220 }
221