1 /*
2 * Copyright 2018-2019 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <spl.h>
9 #include <asm/io.h>
10 #include <asm/mach-imx/iomux-v3.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx8mn_pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/boot_mode.h>
15 #include <asm/arch/ddr.h>
16
17 #include <dm/uclass.h>
18 #include <dm/device.h>
19 #include <dm/uclass-internal.h>
20 #include <dm/device-internal.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
spl_board_boot_device(enum boot_device boot_dev_spl)24 int spl_board_boot_device(enum boot_device boot_dev_spl)
25 {
26 return BOOT_DEVICE_BOOTROM;
27 }
28
spl_dram_init(void)29 void spl_dram_init(void)
30 {
31 ddr_init(&dram_timing);
32 }
33
spl_board_init(void)34 void spl_board_init(void)
35 {
36 struct udevice *dev;
37 int ret;
38
39 puts("Normal Boot\n");
40
41 ret = uclass_get_device_by_name(UCLASS_CLK,
42 "clock-controller@30380000",
43 &dev);
44 if (ret < 0)
45 printf("Failed to find clock node. Check device tree\n");
46 }
47
48 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)49 int board_fit_config_name_match(const char *name)
50 {
51 /* Just empty function now - can't decide what to choose */
52 debug("%s: %s\n", __func__, name);
53
54 return 0;
55 }
56 #endif
57
58 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
59 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
60
61 static iomux_v3_cfg_t const uart_pads[] = {
62 IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
63 IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 };
65
66 static iomux_v3_cfg_t const wdog_pads[] = {
67 IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
68 };
69
board_early_init_f(void)70 int board_early_init_f(void)
71 {
72 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
73
74 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
75
76 set_wdog_reset(wdog);
77
78 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
79
80 init_uart_clk(1);
81
82 return 0;
83 }
84
board_init_f(ulong dummy)85 void board_init_f(ulong dummy)
86 {
87 int ret;
88
89 arch_cpu_init();
90
91 init_uart_clk(1);
92
93 board_early_init_f();
94
95 timer_init();
96
97 preloader_console_init();
98
99 /* Clear the BSS. */
100 memset(__bss_start, 0, __bss_end - __bss_start);
101
102 ret = spl_init();
103 if (ret) {
104 debug("spl_init() failed: %d\n", ret);
105 hang();
106 }
107
108 enable_tzc380();
109
110 /* DDR initialization */
111 spl_dram_init();
112
113 board_init_r(NULL, 0);
114 }
115
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])116 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
117 {
118 puts("resetting ...\n");
119
120 reset_cpu(WDOG1_BASE_ADDR);
121
122 return 0;
123 }
124