1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Prafulla Wadaskar <prafulla@marvell.com>
6 *
7 * (C) Copyright 2009
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
10 * (C) Copyright 2010
11 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 */
13
14 #include <common.h>
15 #include <env.h>
16 #include <i2c.h>
17 #include <init.h>
18 #include <nand.h>
19 #include <netdev.h>
20 #include <miiphy.h>
21 #include <spi.h>
22 #include <asm/io.h>
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/soc.h>
25 #include <asm/arch/mpp.h>
26
27 #include "../common/common.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /*
32 * BOCO FPGA definitions
33 */
34 #define BOCO 0x10
35 #define REG_CTRL_H 0x02
36 #define MASK_WRL_UNITRUN 0x01
37 #define MASK_RBX_PGY_PRESENT 0x40
38 #define REG_IRQ_CIRQ2 0x2d
39 #define MASK_RBI_DEFECT_16 0x01
40
41 /*
42 * PHY registers definitions
43 */
44 #define PHY_MARVELL_OUI 0x5043
45 #define PHY_MARVELL_88E1118_MODEL 0x0022
46 #define PHY_MARVELL_88E1118R_MODEL 0x0024
47
48 #define PHY_MARVELL_PAGE_REG 0x0016
49 #define PHY_MARVELL_DEFAULT_PAGE 0x0000
50
51 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
52 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
53
54 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
57 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
58
59 /* I/O pin to erase flash RGPP09 = MPP43 */
60 #define KM_FLASH_ERASE_ENABLE 43
61
62 /* Multi-Purpose Pins Functionality configuration */
63 static const u32 kwmpp_config[] = {
64 MPP0_NF_IO2,
65 MPP1_NF_IO3,
66 MPP2_NF_IO4,
67 MPP3_NF_IO5,
68 MPP4_NF_IO6,
69 MPP5_NF_IO7,
70 MPP6_SYSRST_OUTn,
71 #if defined(KM_PCIE_RESET_MPP7)
72 MPP7_GPO,
73 #else
74 MPP7_PEX_RST_OUTn,
75 #endif
76 #if defined(CONFIG_SYS_I2C_SOFT)
77 MPP8_GPIO, /* SDA */
78 MPP9_GPIO, /* SCL */
79 #endif
80 MPP10_UART0_TXD,
81 MPP11_UART0_RXD,
82 MPP12_GPO, /* Reserved */
83 MPP13_UART1_TXD,
84 MPP14_UART1_RXD,
85 MPP15_GPIO, /* Not used */
86 MPP16_GPIO, /* Not used */
87 MPP17_GPIO, /* Reserved */
88 MPP18_NF_IO0,
89 MPP19_NF_IO1,
90 MPP20_GPIO,
91 MPP21_GPIO,
92 MPP22_GPIO,
93 MPP23_GPIO,
94 MPP24_GPIO,
95 MPP25_GPIO,
96 MPP26_GPIO,
97 MPP27_GPIO,
98 MPP28_GPIO,
99 MPP29_GPIO,
100 MPP30_GPIO,
101 MPP31_GPIO,
102 MPP32_GPIO,
103 MPP33_GPIO,
104 MPP34_GPIO, /* CDL1 (input) */
105 MPP35_GPIO, /* CDL2 (input) */
106 MPP36_GPIO, /* MAIN_IRQ (input) */
107 MPP37_GPIO, /* BOARD_LED */
108 MPP38_GPIO, /* Piggy3 LED[1] */
109 MPP39_GPIO, /* Piggy3 LED[2] */
110 MPP40_GPIO, /* Piggy3 LED[3] */
111 MPP41_GPIO, /* Piggy3 LED[4] */
112 MPP42_GPIO, /* Piggy3 LED[5] */
113 MPP43_GPIO, /* Piggy3 LED[6] */
114 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
115 MPP45_GPIO, /* Piggy3 LED[8] */
116 MPP46_GPIO, /* Reserved */
117 MPP47_GPIO, /* Reserved */
118 MPP48_GPIO, /* Reserved */
119 MPP49_GPIO, /* SW_INTOUTn */
120 0
121 };
122
123 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
124
125 #if defined(CONFIG_KM_MGCOGE3UN)
126 /*
127 * Wait for startup OK from mgcoge3ne
128 */
startup_allowed(void)129 static int startup_allowed(void)
130 {
131 unsigned char buf;
132
133 /*
134 * Read CIRQ16 bit (bit 0)
135 */
136 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
137 printf("%s: Error reading Boco\n", __func__);
138 else
139 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
140 return 1;
141 return 0;
142 }
143 #endif
144
145 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
146 /*
147 * All boards with PIGGY4 connected via a simple switch have ethernet always
148 * present.
149 */
ethernet_present(void)150 int ethernet_present(void)
151 {
152 return 1;
153 }
154 #else
ethernet_present(void)155 int ethernet_present(void)
156 {
157 uchar buf;
158 int ret = 0;
159
160 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
161 printf("%s: Error reading Boco\n", __func__);
162 return -1;
163 }
164 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
165 ret = 1;
166
167 return ret;
168 }
169 #endif
170
initialize_unit_leds(void)171 static int initialize_unit_leds(void)
172 {
173 /*
174 * Init the unit LEDs per default they all are
175 * ok apart from bootstat
176 */
177 uchar buf;
178
179 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
180 printf("%s: Error reading Boco\n", __func__);
181 return -1;
182 }
183 buf |= MASK_WRL_UNITRUN;
184 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
185 printf("%s: Error writing Boco\n", __func__);
186 return -1;
187 }
188 return 0;
189 }
190
set_bootcount_addr(void)191 static void set_bootcount_addr(void)
192 {
193 uchar buf[32];
194 unsigned int bootcountaddr;
195 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
196 sprintf((char *)buf, "0x%x", bootcountaddr);
197 env_set("bootcountaddr", (char *)buf);
198 }
199
misc_init_r(void)200 int misc_init_r(void)
201 {
202 #if defined(CONFIG_KM_MGCOGE3UN)
203 char *wait_for_ne;
204 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
205 wait_for_ne = env_get("waitforne");
206
207 if ((wait_for_ne != NULL) && (dip_switch == 0)) {
208 if (strcmp(wait_for_ne, "true") == 0) {
209 int cnt = 0;
210 int abort = 0;
211 puts("NE go: ");
212 while (startup_allowed() == 0) {
213 if (tstc()) {
214 (void) getc(); /* consume input */
215 abort = 1;
216 break;
217 }
218 udelay(200000);
219 cnt++;
220 if (cnt == 5)
221 puts("wait\b\b\b\b");
222 if (cnt == 10) {
223 cnt = 0;
224 puts(" \b\b\b\b");
225 }
226 }
227 if (abort == 1)
228 printf("\nAbort waiting for ne\n");
229 else
230 puts("OK\n");
231 }
232 }
233 #endif
234
235 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
236
237 initialize_unit_leds();
238 set_km_env();
239 set_bootcount_addr();
240 return 0;
241 }
242
board_early_init_f(void)243 int board_early_init_f(void)
244 {
245 #if defined(CONFIG_SYS_I2C_SOFT)
246 u32 tmp;
247
248 /* set the 2 bitbang i2c pins as output gpios */
249 tmp = readl(MVEBU_GPIO0_BASE + 4);
250 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
251 #endif
252 /* adjust SDRAM size for bank 0 */
253 mvebu_sdram_size_adjust(0);
254 kirkwood_mpp_conf(kwmpp_config, NULL);
255 return 0;
256 }
257
board_init(void)258 int board_init(void)
259 {
260 /* address of boot parameters */
261 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
262
263 /*
264 * The KM_FLASH_GPIO_PIN switches between using a
265 * NAND or a SPI FLASH. Set this pin on start
266 * to NAND mode.
267 */
268 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
269 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
270
271 #if defined(CONFIG_SYS_I2C_SOFT)
272 /*
273 * Reinit the GPIO for I2C Bitbang driver so that the now
274 * available gpio framework is consistent. The calls to
275 * direction output in are not necessary, they are already done in
276 * board_early_init_f
277 */
278 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
279 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
280 #endif
281
282 #if defined(CONFIG_SYS_EEPROM_WREN)
283 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
284 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
285 #endif
286
287 #if defined(CONFIG_KM_FPGA_CONFIG)
288 trigger_fpga_config();
289 #endif
290
291 return 0;
292 }
293
board_late_init(void)294 int board_late_init(void)
295 {
296 #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
297 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
298
299 /* if pin 1 do full erase */
300 if (dip_switch != 0) {
301 /* start bootloader */
302 puts("DIP: Enabled\n");
303 env_set("actual_bank", "0");
304 }
305 #endif
306
307 #if defined(CONFIG_KM_FPGA_CONFIG)
308 wait_for_fpga_config();
309 fpga_reset();
310 toggle_eeprom_spi_bus();
311 #endif
312 return 0;
313 }
314
315 static const u32 spi_mpp_config[] = {
316 MPP1_SPI_MOSI,
317 MPP2_SPI_SCK,
318 MPP3_SPI_MISO,
319 0
320 };
321
322 static u32 spi_mpp_backup[4];
323
mvebu_board_spi_claim_bus(struct udevice * dev)324 int mvebu_board_spi_claim_bus(struct udevice *dev)
325 {
326 spi_mpp_backup[3] = 0;
327
328 /* set new spi mpp config and save current one */
329 kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
330
331 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
332
333 return 0;
334 }
335
mvebu_board_spi_release_bus(struct udevice * dev)336 int mvebu_board_spi_release_bus(struct udevice *dev)
337 {
338 /* restore saved mpp config */
339 kirkwood_mpp_conf(spi_mpp_backup, NULL);
340
341 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
342
343 return 0;
344 }
345
346 #if (defined(CONFIG_KM_PIGGY4_88E6061))
347
348 #define PHY_LED_SEL_REG 0x18
349 #define PHY_LED0_LINK (0x5)
350 #define PHY_LED1_ACT (0x8<<4)
351 #define PHY_LED2_INT (0xe<<8)
352 #define PHY_SPEC_CTRL_REG 0x1c
353 #define PHY_RGMII_CLK_STABLE (0x1<<10)
354 #define PHY_CLSA (0x1<<1)
355
356 /* Configure and enable MV88E3018 PHY */
reset_phy(void)357 void reset_phy(void)
358 {
359 char *name = "egiga0";
360 unsigned short reg;
361
362 if (miiphy_set_current_dev(name))
363 return;
364
365 /* RGMII clk transition on data stable */
366 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
367 printf("Error reading PHY spec ctrl reg\n");
368 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
369 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
370 printf("Error writing PHY spec ctrl reg\n");
371
372 /* leds setup */
373 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
374 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
375 printf("Error writing PHY LED reg\n");
376
377 /* reset the phy */
378 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
379 }
380 #elif defined(CONFIG_KM_PIGGY4_88E6352)
381
382 #include <mv88e6352.h>
383
384 #if defined(CONFIG_KM_NUSA)
385 struct mv88e_sw_reg extsw_conf[] = {
386 /*
387 * port 0, PIGGY4, autoneg
388 * first the fix for the 1000Mbits Autoneg, this is from
389 * a Marvell errata, the regs are undocumented
390 */
391 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
392 { PHY(0), PHY_STATUS, AN1000FIX },
393 { PHY(0), PHY_PAGE, 0 },
394 /* now the real port and phy configuration */
395 { PORT(0), PORT_PHY, NO_SPEED_FOR },
396 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
397 { PHY(0), PHY_1000_CTRL, NO_ADV },
398 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
399 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
400 FULL_DUPLEX },
401 /* port 1, unused */
402 { PORT(1), PORT_CTRL, PORT_DIS },
403 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
404 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
405 /* port 2, unused */
406 { PORT(2), PORT_CTRL, PORT_DIS },
407 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
408 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
409 /* port 3, unused */
410 { PORT(3), PORT_CTRL, PORT_DIS },
411 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
412 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
413 /* port 4, ICNEV, SerDes, SGMII */
414 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
415 { PORT(4), PORT_PHY, SPEED_1000_FOR },
416 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
417 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
418 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
419 /* port 5, CPU_RGMII */
420 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
421 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
422 FULL_DPX_FOR | SPEED_1000_FOR },
423 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
424 /* port 6, unused, this port has no phy */
425 { PORT(6), PORT_CTRL, PORT_DIS },
426 };
427 #else
428 struct mv88e_sw_reg extsw_conf[] = {};
429 #endif
430
reset_phy(void)431 void reset_phy(void)
432 {
433 #if defined(CONFIG_KM_MVEXTSW_ADDR)
434 char *name = "egiga0";
435
436 if (miiphy_set_current_dev(name))
437 return;
438
439 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
440 ARRAY_SIZE(extsw_conf));
441 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
442 #endif
443 }
444
445 #else
446 /* Configure and enable MV88E1118 PHY on the piggy*/
reset_phy(void)447 void reset_phy(void)
448 {
449 unsigned int oui;
450 unsigned char model, rev;
451
452 char *name = "egiga0";
453
454 if (miiphy_set_current_dev(name))
455 return;
456
457 /* reset the phy */
458 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
459
460 /* get PHY model */
461 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
462 return;
463
464 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
465 if ((oui == PHY_MARVELL_OUI) &&
466 (model == PHY_MARVELL_88E1118R_MODEL)) {
467 /* set page register to 3 */
468 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
469 PHY_MARVELL_PAGE_REG,
470 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
471 printf("Error writing PHY page reg\n");
472
473 /*
474 * leds setup as printed on PCB:
475 * LED2 (Link): 0x0 (On Link, Off No Link)
476 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
477 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
478 */
479 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
480 PHY_MARVELL_88E1118R_LED_CTRL_REG,
481 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
482 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
483 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
484 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
485 printf("Error writing PHY LED reg\n");
486
487 /* set page register back to 0 */
488 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
489 PHY_MARVELL_PAGE_REG,
490 PHY_MARVELL_DEFAULT_PAGE))
491 printf("Error writing PHY page reg\n");
492 }
493 }
494 #endif
495
496
497 #if defined(CONFIG_HUSH_INIT_VAR)
hush_init_var(void)498 int hush_init_var(void)
499 {
500 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
501 return 0;
502 }
503 #endif
504
505 #if defined(CONFIG_SYS_I2C_SOFT)
set_sda(int state)506 void set_sda(int state)
507 {
508 I2C_ACTIVE;
509 I2C_SDA(state);
510 }
511
set_scl(int state)512 void set_scl(int state)
513 {
514 I2C_SCL(state);
515 }
516
get_sda(void)517 int get_sda(void)
518 {
519 I2C_TRISTATE;
520 return I2C_READ;
521 }
522
get_scl(void)523 int get_scl(void)
524 {
525 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
526 }
527 #endif
528
529 #if defined(CONFIG_POST)
530
531 #define KM_POST_EN_L 44
532 #define POST_WORD_OFF 8
533
post_hotkeys_pressed(void)534 int post_hotkeys_pressed(void)
535 {
536 #if defined(CONFIG_KM_COGE5UN)
537 return kw_gpio_get_value(KM_POST_EN_L);
538 #else
539 return !kw_gpio_get_value(KM_POST_EN_L);
540 #endif
541 }
542
post_word_load(void)543 ulong post_word_load(void)
544 {
545 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
546 return in_le32(addr);
547
548 }
post_word_store(ulong value)549 void post_word_store(ulong value)
550 {
551 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
552 out_le32(addr, value);
553 }
554
arch_memory_test_prepare(u32 * vstart,u32 * size,phys_addr_t * phys_offset)555 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
556 {
557 *vstart = CONFIG_SYS_SDRAM_BASE;
558
559 /* we go up to relocation plus a 1 MB margin */
560 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
561
562 return 0;
563 }
564 #endif
565
566 #if defined(CONFIG_SYS_EEPROM_WREN)
eeprom_write_enable(unsigned dev_addr,int state)567 int eeprom_write_enable(unsigned dev_addr, int state)
568 {
569 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
570
571 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
572 }
573 #endif
574