1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/io.h>
9 #include <led.h>
10 #include <miiphy.h>
11
12 enum {
13 BOARD_TYPE_PCB110 = 0xAABBCE00,
14 BOARD_TYPE_PCB111,
15 BOARD_TYPE_PCB112,
16 };
17
board_early_init_r(void)18 int board_early_init_r(void)
19 {
20 /* Prepare SPI controller to be used in master mode */
21 writel(0, BASE_CFG + ICPU_SW_MODE);
22 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
23 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
24 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
25
26 /* Address of boot parameters */
27 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
28
29 /* LED setup */
30 if (IS_ENABLED(CONFIG_LED))
31 led_default_state();
32
33 return 0;
34 }
35
vcoreiii_gpio_set_alternate(int gpio,int mode)36 static void vcoreiii_gpio_set_alternate(int gpio, int mode)
37 {
38 u32 mask;
39 u32 val0, val1;
40 void __iomem *reg0, *reg1;
41
42 if (gpio < 32) {
43 mask = BIT(gpio);
44 reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
45 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
46 } else {
47 gpio -= 32;
48 mask = BIT(gpio);
49 reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
50 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
51 }
52 val0 = readl(reg0);
53 val1 = readl(reg1);
54 if (mode == 1) {
55 writel(val0 | mask, reg0);
56 writel(val1 & ~mask, reg1);
57 } else if (mode == 2) {
58 writel(val0 & ~mask, reg0);
59 writel(val1 | mask, reg1);
60 } else if (mode == 3) {
61 writel(val0 | mask, reg0);
62 writel(val1 | mask, reg1);
63 } else {
64 writel(val0 & ~mask, reg0);
65 writel(val1 & ~mask, reg1);
66 }
67 }
68
board_phy_config(struct phy_device * phydev)69 int board_phy_config(struct phy_device *phydev)
70 {
71 if (gd->board_type == BOARD_TYPE_PCB110 ||
72 gd->board_type == BOARD_TYPE_PCB112) {
73 phy_write(phydev, 0, 31, 0x10);
74 phy_write(phydev, 0, 18, 0x80F0);
75 while (phy_read(phydev, 0, 18) & 0x8000)
76 ;
77 phy_write(phydev, 0, 31, 0);
78 }
79 if (gd->board_type == BOARD_TYPE_PCB111) {
80 phy_write(phydev, 0, 31, 0x10);
81 phy_write(phydev, 0, 18, 0x80A0);
82 while (phy_read(phydev, 0, 18) & 0x8000)
83 ;
84 phy_write(phydev, 0, 14, 0x800);
85 phy_write(phydev, 0, 31, 0);
86 }
87
88 return 0;
89 }
90
board_debug_uart_init(void)91 void board_debug_uart_init(void)
92 {
93 /* too early for the pinctrl driver, so configure the UART pins here */
94 vcoreiii_gpio_set_alternate(10, 1);
95 vcoreiii_gpio_set_alternate(11, 1);
96 }
97
do_board_detect(void)98 static void do_board_detect(void)
99 {
100 int i;
101 u16 pval;
102
103 /* MIIM 1 + 2 MDC/MDIO */
104 for (i = 56; i < 60; i++)
105 vcoreiii_gpio_set_alternate(i, 1);
106
107 /* small delay for settling the pins */
108 mdelay(30);
109
110 if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
111 ((pval >> 4) & 0x3F) == 0x3c) {
112 gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
113 } else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
114 ((pval >> 4) & 0x3F) == 0x3c) {
115 gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
116 } else {
117 /* Fall-back */
118 gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
119 }
120 }
121
122 #if defined(CONFIG_MULTI_DTB_FIT)
board_fit_config_name_match(const char * name)123 int board_fit_config_name_match(const char *name)
124 {
125 if (gd->board_type == BOARD_TYPE_PCB110 &&
126 strcmp(name, "jr2_pcb110") == 0)
127 return 0;
128
129 if (gd->board_type == BOARD_TYPE_PCB111 &&
130 strcmp(name, "jr2_pcb111") == 0)
131 return 0;
132
133 if (gd->board_type == BOARD_TYPE_PCB112 &&
134 strcmp(name, "serval2_pcb112") == 0)
135 return 0;
136
137 return -1;
138 }
139 #endif
140
141 #if defined(CONFIG_DTB_RESELECT)
embedded_dtb_select(void)142 int embedded_dtb_select(void)
143 {
144 do_board_detect();
145 fdtdec_setup();
146
147 return 0;
148 }
149 #endif
150