1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * Description: SDHCI controller platform adaptation.
18 */
19
20 #define SDIO_DRV_DLL_SRST_REQ (0x1 << 29)
21 #define SDIO_CLK_EN (0x1 << 28)
22 #define SDIO_SRST_REQ (0x1 << 27)
23 #define SDIO_CLK_SEL (0x7 << 24)
24 #define SDIO_CLK_SEL_400K (0x1 << 24)
25
26 #define REG_EMMC_DRV_DLL_STATUS (CRG_REG_BASE + 0x210)
27 #define REG_SDIO0_DRV_DLL_STATUS REG_EMMC_DRV_DLL_STATUS
28 #define REG_SDIO1_DRV_DLL_STATUS (CRG_REG_BASE + 0x228)
29 #define SDIO_DRV_DLL_LOCK BIT(15)
30 #define SDIO_DRV_DLL_READY BIT(14)
31
32 #define REG_EMMC_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x208)
33 #define REG_SDIO0_SAMPL_DLL_STATUS REG_EMMC_SAMPL_DLL_STATUS
34 #define REG_SDIO1_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x224)
35 #define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
36
37 #define REG_EMMC_SAMPL_DLL_CTRL (CRG_REG_BASE + 0x1f4)
38 #define REG_SDIO0_SAMPL_DLL_CTRL REG_EMMC_SAMPL_DLL_CTRL
39 #define REG_SDIO1_SAMPL_DLL_CTRL (CRG_REG_BASE + 0x22c)
40 #define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
41
42 #define REG_EMMC_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x1f8)
43 #define REG_SDIO0_SAMPLB_DLL_CTRL REG_EMMC_SAMPLB_DLL_CTRL
44 #define REG_SDIO1_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x21c)
45 #define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
46 #define sdio_samplb_sel(phase) ((phase) << 0)
47
48 #define REG_EMMC_DRV_DLL_CTRL (CRG_REG_BASE + 0x1fc)
49 #define REG_SDIO0_DRV_DLL_CTRL REG_EMMC_DRV_DLL_CTRL
50 #define REG_SDIO1_DRV_DLL_CTRL (CRG_REG_BASE + 0x220)
51 #define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
52 #define sdio_drv_sel(phase) ((phase) << 24)
53
54 #define REG_EMMC_DS_DLL_CTRL (CRG_REG_BASE + 0x200)
55 #define EMMC_DS_DLL_MODE_SSEL BIT(13)
56 #define EMMC_DS_DLL_SSEL_MASK 0x7f
57
58 #define REG_EMMC_DS180_DLL_CTRL (CRG_REG_BASE + 0x204)
59 #define EMMC_DS180_DLL_BYPASS BIT(15)
60 #define REG_EMMC_DS180_DLL_STATUS (CRG_REG_BASE + 0x218)
61 #define EMMC_DS180_DLL_READY BIT(0)
62
63 #define IO_CFG_SR BIT(10)
64 #define IO_CFG_PULL_DOWN BIT(9)
65 #define IO_CFG_PULL_UP BIT(8)
66 #define IO_CFG_DRV_STR_MASK (0xf << 4)
67 #define io_cfg_drv_str_sel(str) ((str) << 4)
68
69 #define REG_IO_CFG_BASE 0x100C0000
70 /* EMMC_IOCFG */
71 #define IO_CFG_EMMC_DATA_LINE_COUNT 8
72 #define REG_CTRL_EMMC_CLK 0x0014
73 #define REG_CTRL_EMMC_CMD 0x0018
74 #define REG_CTRL_EMMC_DATA0 0x001c
75 #define REG_CTRL_EMMC_DATA1 0x0028
76 #define REG_CTRL_EMMC_DATA2 0x0024
77 #define REG_CTRL_EMMC_DATA3 0x0020
78 #define REG_CTRL_EMMC_DATA4 0x0030
79 #define REG_CTRL_EMMC_DATA5 0x0034
80 #define REG_CTRL_EMMC_DATA6 0x0038
81 #define REG_CTRL_EMMC_DATA7 0x003c
82 #define REG_CTRL_EMMC_DS 0x0058
83 #define REG_CTRL_EMMC_RST 0x005c
84 static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {
85 REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
86 REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3,
87 REG_CTRL_EMMC_DATA4, REG_CTRL_EMMC_DATA5,
88 REG_CTRL_EMMC_DATA6, REG_CTRL_EMMC_DATA7
89 };
90
91 #define IO_CFG_SDIO0_DATA_LINE_COUNT 4
92 #define REG_CTRL_SDIO0_CLK 0x0040
93 #define REG_CTRL_SDIO0_CMD 0x0044
94 #define REG_CTRL_SDIO0_DATA0 0x0048
95 #define REG_CTRL_SDIO0_DATA1 0x004C
96 #define REG_CTRL_SDIO0_DATA2 0x0050
97 #define REG_CTRL_SDIO0_DATA3 0x0054
98 static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {
99 REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
100 REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3
101 };
102
103 #define CLK_100K 100000
104 #define CLK_400K 400000
105 #define CLK_25M 25000000
106 #define CLK_50M 50000000
107 #define CLK_90M 90000000
108 #define CLK_112M 112000000
109 #define CLK_150M 150000000
110 #define CLK_198M 198000000
111
hisi_dll_reset_assert(struct sdhci_host * host)112 static void hisi_dll_reset_assert(struct sdhci_host *host)
113 {
114 uintptr_t crg_addr;
115 unsigned int reg;
116
117 crg_addr = REG_EMMC_CRG;
118 reg = readl(crg_addr);
119 reg |= SDIO_DRV_DLL_SRST_REQ;
120 writel(reg, crg_addr);
121 }
122
hisi_dll_reset_deassert(struct sdhci_host * host)123 static void hisi_dll_reset_deassert(struct sdhci_host *host)
124 {
125 uintptr_t crg_addr;
126 unsigned int reg;
127
128 crg_addr = REG_EMMC_CRG;
129 reg = readl(crg_addr);
130 reg &= ~SDIO_DRV_DLL_SRST_REQ;
131 writel(reg, crg_addr);
132 }
133
hisi_set_crg(struct sdhci_host * host,unsigned int clk)134 static void hisi_set_crg(struct sdhci_host *host, unsigned int clk)
135 {
136 uintptr_t crg_addr;
137 unsigned int sel, reg;
138 unsigned int clk_mux[] = {
139 CLK_100K, CLK_400K, CLK_25M, CLK_50M,
140 CLK_90M, CLK_112M, CLK_150M, CLK_198M
141 };
142
143 crg_addr = REG_EMMC_CRG;
144 reg = readl(crg_addr);
145 reg &= ~MMC_CLK_SEL_MASK;
146
147 if (clk <= MIN_FREQ) {
148 sel = 1;
149 } else {
150 for (sel = 0x6; sel > 0; sel--) {
151 if (clk >= clk_mux[sel])
152 break;
153 }
154 }
155
156 reg |= mmc_clk_sel(sel);
157 writel(reg, crg_addr);
158 }
159
hisi_wait_ds180_dll_ready(void)160 static void hisi_wait_ds180_dll_ready(void)
161 {
162 unsigned int reg;
163 unsigned int timeout = 20;
164
165 do {
166 reg = readl(REG_EMMC_DS180_DLL_STATUS);
167 if (reg & EMMC_DS180_DLL_READY)
168 return;
169
170 udelay(1000); /* delay 1000us */
171 timeout--;
172 } while (timeout > 0);
173
174 printf("DS180 DLL master not ready.\n");
175 }
176
hisi_mmc_priv_init(struct sdhci_host * host)177 static void hisi_mmc_priv_init(struct sdhci_host *host)
178 {
179 unsigned short ctrl;
180 unsigned int reg;
181
182 ctrl = sdhci_readw(host, SDHCI_MSHC_CTRL);
183 ctrl &= ~SDHCI_CMD_CONFLIT_CHECK;
184 sdhci_writew(host, ctrl, SDHCI_MSHC_CTRL);
185
186 reg = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
187 reg |= SDHCI_GM_WR_OSRC_LMT | SDHCI_GM_RD_OSRC_LMT;
188 reg &= ~SDHCI_UNDEFL_INCR_EN;
189 sdhci_writel(host, reg, SDHCI_AXI_MBIIU_CTRL);
190
191 reg = sdhci_readl(host, SDHCI_MULTI_CYCLE);
192 reg &= ~SDHCI_CMD_DLY_EN;
193 reg |= SDHCI_EDGE_DETECT_EN | SDHCI_DATA_DLY_EN;
194 sdhci_writel(host, reg, SDHCI_MULTI_CYCLE);
195 }
196
hisi_set_drv_str(unsigned int offset,unsigned int pull_up,unsigned int pull_down,unsigned int sr,unsigned int drv_str)197 static void hisi_set_drv_str(unsigned int offset, unsigned int pull_up,
198 unsigned int pull_down, unsigned int sr,
199 unsigned int drv_str)
200 {
201 unsigned int reg;
202 const uintptr_t crg_addr = REG_IO_CFG_BASE + offset;
203
204 reg = readl(crg_addr);
205 reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN |
206 IO_CFG_DRV_STR_MASK | IO_CFG_SR);
207 reg |= (pull_up ? IO_CFG_PULL_UP : 0);
208 reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
209 reg |= (sr ? IO_CFG_SR : 0);
210 reg |= io_cfg_drv_str_sel(drv_str);
211 writel(reg, crg_addr);
212 }
213
sd_hardware_init(void)214 static int sd_hardware_init(void)
215 {
216 unsigned int reg;
217
218 /* clk enable */
219 reg = readl(REG_EMMC_CRG);
220 reg |= SDIO_CLK_EN;
221 writel(reg, REG_EMMC_CRG);
222
223 /* reset assert */
224 reg = readl(REG_EMMC_CRG);
225 reg |= SDIO_SRST_REQ | SDIO_DRV_DLL_SRST_REQ;
226 writel(reg, REG_EMMC_CRG);
227 udelay(25); /* delay 25us */
228
229 /* reset deassert */
230 reg &= ~SDIO_SRST_REQ;
231 writel(reg, REG_EMMC_CRG);
232 udelay(1); /* delay 1us */
233
234 udelay(5000); /* delay 5000us */
235
236 return 0;
237 }
238
emmc_hardware_init(void)239 static int emmc_hardware_init(void)
240 {
241 unsigned int reg;
242
243 /* eMMC clk enable */
244 reg = readl(REG_EMMC_CRG);
245 reg |= SDIO_CLK_EN;
246 writel(reg, REG_EMMC_CRG);
247
248 /* eMMC reset assert */
249 reg = readl(REG_EMMC_CRG);
250 reg |= SDIO_SRST_REQ | SDIO_DRV_DLL_SRST_REQ;
251 writel(reg, REG_EMMC_CRG);
252 udelay(25); /* delay 25us */
253
254 /* select 400K clk */
255 reg = readl(REG_EMMC_CRG);
256 reg &= ~SDIO_CLK_SEL;
257 reg |= SDIO_CLK_SEL_400K;
258 writel(reg, REG_EMMC_CRG);
259 udelay(25); /* delay 25us */
260
261 /* eMMC reset deassert */
262 reg = readl(REG_EMMC_CRG);
263 reg &= ~SDIO_SRST_REQ;
264 writel(reg, REG_EMMC_CRG);
265 udelay(1); /* delay 1us */
266
267 return 0;
268 }
269
hisi_emmc_set_ioconfig(struct sdhci_host * host)270 static void hisi_emmc_set_ioconfig(struct sdhci_host *host)
271 {
272 int i;
273
274 switch (host->mmc->selected_mode) {
275 case MMC_HS_400:
276 case MMC_HS_400_ES:
277 hisi_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3); /* set drv level 3 */
278 hisi_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 0, 0x4); /* set drv level 4 */
279 for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
280 hisi_set_drv_str(io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
281
282 hisi_set_drv_str(REG_CTRL_EMMC_DS, 0, 1, 1, 0x3); /* set drv level 3 */
283 hisi_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
284 break;
285 case MMC_HS_200:
286 hisi_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2); /* set drv level 2 */
287 hisi_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4); /* set drv level 4 */
288 for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
289 hisi_set_drv_str(io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
290
291 hisi_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
292 break;
293 case MMC_HS:
294 case MMC_HS_52:
295 hisi_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4); /* set drv level 4 */
296 hisi_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
297 for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
298 hisi_set_drv_str(io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
299
300 hisi_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
301 break;
302 case MMC_LEGACY:
303 default:
304 hisi_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
305 hisi_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
306 for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
307 hisi_set_drv_str(io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
308
309 hisi_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
310 break;
311 }
312 }
313
hisi_sd_set_ioconfig(struct sdhci_host * host)314 static void hisi_sd_set_ioconfig(struct sdhci_host *host)
315 {
316 int i;
317
318 switch (host->mmc->selected_mode) {
319 case SD_HS:
320 hisi_set_drv_str(REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
321 hisi_set_drv_str(REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
322 for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
323 hisi_set_drv_str(io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
324 break;
325 case SD_LEGACY:
326 default:
327 hisi_set_drv_str(REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x7); /* set drv level 7 */
328 hisi_set_drv_str(REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
329 for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
330 hisi_set_drv_str(io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
331 break;
332 }
333 }
334
hisi_mmc_set_ioconfig(struct sdhci_host * host)335 static void hisi_mmc_set_ioconfig(struct sdhci_host *host)
336 {
337 unsigned int reg;
338
339 if (host->type == MMC_TYPE_MMC) {
340 reg = sdhci_readw(host, SDHCI_EMMC_CTRL);
341 reg |= SDHCI_CARD_IS_EMMC;
342 sdhci_writew(host, reg, SDHCI_EMMC_CTRL);
343
344 hisi_emmc_set_ioconfig(host);
345 } else {
346 hisi_sd_set_ioconfig(host);
347 }
348 sdhci_set_uhs_timing(host);
349 }
350
hisi_set_phase(struct sdhci_host * host)351 static void hisi_set_phase(struct sdhci_host *host)
352 {
353 unsigned int drv_phase, sample_phase;
354
355 if (host->mmc->selected_mode == MMC_HS_400_ES ||
356 host->mmc->selected_mode == MMC_HS_400) {
357 drv_phase = 10; /* 10 for 112.5 degree */
358 sample_phase = host->tuning_phase;
359 } else if (host->mmc->selected_mode == MMC_HS_200) {
360 drv_phase = 23; /* 23 for 258.75 degree */
361 sample_phase = host->tuning_phase;
362 } else if (host->mmc->selected_mode == MMC_HS ||
363 host->mmc->selected_mode == MMC_HS_52) {
364 drv_phase = 16; /* 16 for 180 degree */
365 sample_phase = 4; /* 4 for 45 degree */
366 } else if (host->mmc->selected_mode == SD_HS) {
367 drv_phase = 20; /* 20 for 225 degree */
368 sample_phase = 4; /* 4 for 45 degree */
369 } else if (host->mmc->selected_mode == MMC_LEGACY ||
370 host->mmc->selected_mode == SD_LEGACY) {
371 drv_phase = 16; /* 16 for 180 degree */
372 sample_phase = 0; /* 0 for degree */
373 } else {
374 drv_phase = 16; /* 16 for 180 degree */
375 sample_phase = 4; /* 4 for 45 degree */
376 }
377
378 hisi_set_drv_phase(host, drv_phase);
379 hisi_enable_sample(host);
380 hisi_set_sampl_phase(host, sample_phase);
381
382 udelay(25); /* delay 25us */
383 }
384
hisi_wait_drv_dll_lock(struct sdhci_host * host)385 static void hisi_wait_drv_dll_lock(struct sdhci_host *host)
386 {
387 unsigned int timeout = 20;
388 unsigned int reg;
389 uintptr_t reg_addr;
390
391 reg_addr = host->type == MMC_TYPE_MMC ?
392 REG_EMMC_DRV_DLL_STATUS : REG_SDIO0_DRV_DLL_STATUS;
393 do {
394 reg = readl(reg_addr);
395 if (reg & SDIO_DRV_DLL_LOCK)
396 return;
397
398 udelay(1000); /* delay 1000us */
399 timeout--;
400 } while (timeout > 0);
401
402 printf("sdhci-hisi: DRV DLL master not locked.\n");
403 }
404
hisi_enable_sampl_dll_slave(struct sdhci_host * host)405 static void hisi_enable_sampl_dll_slave(struct sdhci_host *host)
406 {
407 unsigned int reg;
408 uintptr_t reg_addr;
409
410 reg_addr = host->type == MMC_TYPE_MMC ?
411 REG_EMMC_SAMPL_DLL_CTRL : REG_SDIO0_SAMPL_DLL_CTRL;
412 reg = readl(reg_addr);
413 reg |= SDIO_SAMPL_DLL_SLAVE_EN;
414 writel(reg, reg_addr);
415 }
416
hisi_mmc_set_clk(struct sdhci_host * host,unsigned int clk)417 static int hisi_mmc_set_clk(struct sdhci_host *host, unsigned int clk)
418 {
419 hisi_dll_reset_assert(host);
420 udelay(25); /* delay 25us */
421 hisi_set_crg(host, clk);
422 hisi_set_phase(host);
423 udelay(25); /* delay 25us */
424
425 if (clk > MMC_HIGH_52_MAX_DTR) {
426 hisi_enable_sampl_dll_slave(host);
427 hisi_dll_reset_deassert(host);
428 }
429
430 hisi_enable_internal_clk(host);
431
432 if (clk > MMC_HIGH_52_MAX_DTR) {
433 hisi_wait_drv_dll_lock(host);
434 hisi_wait_sampl_dll_slave_ready(host);
435 hisi_wait_ds180_dll_ready();
436 }
437
438 hisi_enable_card_clk(host);
439 udelay(100); /* delay 100us */
440
441 return 0;
442 }