1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 *
6 * Ethernet driver for H3/A64/A83T based SoC's
7 *
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
10 *
11 */
12
13 #include <cpu_func.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
17 #include <common.h>
18 #include <clk.h>
19 #include <dm.h>
20 #include <fdt_support.h>
21 #include <linux/err.h>
22 #include <malloc.h>
23 #include <miiphy.h>
24 #include <net.h>
25 #include <reset.h>
26 #include <dt-bindings/pinctrl/sun4i-a10.h>
27 #ifdef CONFIG_DM_GPIO
28 #include <asm-generic/gpio.h>
29 #endif
30
31 #define MDIO_CMD_MII_BUSY BIT(0)
32 #define MDIO_CMD_MII_WRITE BIT(1)
33
34 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
35 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
36 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
37 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
38
39 #define CONFIG_TX_DESCR_NUM 32
40 #define CONFIG_RX_DESCR_NUM 32
41 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
42
43 /*
44 * The datasheet says that each descriptor can transfers up to 4096 bytes
45 * But later, the register documentation reduces that value to 2048,
46 * using 2048 cause strange behaviours and even BSP driver use 2047
47 */
48 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
49
50 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
51 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
52
53 #define H3_EPHY_DEFAULT_VALUE 0x58000
54 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
55 #define H3_EPHY_ADDR_SHIFT 20
56 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
57 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
58 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
59 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
60
61 #define SC_RMII_EN BIT(13)
62 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
63 #define SC_ETCS_MASK GENMASK(1, 0)
64 #define SC_ETCS_EXT_GMII 0x1
65 #define SC_ETCS_INT_GMII 0x2
66 #define SC_ETXDC_MASK GENMASK(12, 10)
67 #define SC_ETXDC_OFFSET 10
68 #define SC_ERXDC_MASK GENMASK(9, 5)
69 #define SC_ERXDC_OFFSET 5
70
71 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
72
73 #define AHB_GATE_OFFSET_EPHY 0
74
75 /* IO mux settings */
76 #define SUN8I_IOMUX_H3 2
77 #define SUN8I_IOMUX_R40 5
78 #define SUN8I_IOMUX 4
79
80 /* H3/A64 EMAC Register's offset */
81 #define EMAC_CTL0 0x00
82 #define EMAC_CTL1 0x04
83 #define EMAC_INT_STA 0x08
84 #define EMAC_INT_EN 0x0c
85 #define EMAC_TX_CTL0 0x10
86 #define EMAC_TX_CTL1 0x14
87 #define EMAC_TX_FLOW_CTL 0x1c
88 #define EMAC_TX_DMA_DESC 0x20
89 #define EMAC_RX_CTL0 0x24
90 #define EMAC_RX_CTL1 0x28
91 #define EMAC_RX_DMA_DESC 0x34
92 #define EMAC_MII_CMD 0x48
93 #define EMAC_MII_DATA 0x4c
94 #define EMAC_ADDR0_HIGH 0x50
95 #define EMAC_ADDR0_LOW 0x54
96 #define EMAC_TX_DMA_STA 0xb0
97 #define EMAC_TX_CUR_DESC 0xb4
98 #define EMAC_TX_CUR_BUF 0xb8
99 #define EMAC_RX_DMA_STA 0xc0
100 #define EMAC_RX_CUR_DESC 0xc4
101
102 DECLARE_GLOBAL_DATA_PTR;
103
104 enum emac_variant {
105 A83T_EMAC = 1,
106 H3_EMAC,
107 A64_EMAC,
108 R40_GMAC,
109 };
110
111 struct emac_dma_desc {
112 u32 status;
113 u32 st;
114 u32 buf_addr;
115 u32 next;
116 } __aligned(ARCH_DMA_MINALIGN);
117
118 struct emac_eth_dev {
119 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
120 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
121 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
122 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
123
124 u32 interface;
125 u32 phyaddr;
126 u32 link;
127 u32 speed;
128 u32 duplex;
129 u32 phy_configured;
130 u32 tx_currdescnum;
131 u32 rx_currdescnum;
132 u32 addr;
133 u32 tx_slot;
134 bool use_internal_phy;
135
136 enum emac_variant variant;
137 void *mac_reg;
138 phys_addr_t sysctl_reg;
139 struct phy_device *phydev;
140 struct mii_dev *bus;
141 struct clk tx_clk;
142 struct clk ephy_clk;
143 struct reset_ctl tx_rst;
144 struct reset_ctl ephy_rst;
145 #ifdef CONFIG_DM_GPIO
146 struct gpio_desc reset_gpio;
147 #endif
148 };
149
150
151 struct sun8i_eth_pdata {
152 struct eth_pdata eth_pdata;
153 u32 reset_delays[3];
154 int tx_delay_ps;
155 int rx_delay_ps;
156 };
157
158
sun8i_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)159 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
160 {
161 struct udevice *dev = bus->priv;
162 struct emac_eth_dev *priv = dev_get_priv(dev);
163 ulong start;
164 u32 miiaddr = 0;
165 int timeout = CONFIG_MDIO_TIMEOUT;
166
167 miiaddr &= ~MDIO_CMD_MII_WRITE;
168 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
169 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
170 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
171
172 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
173
174 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
175 MDIO_CMD_MII_PHY_ADDR_MASK;
176
177 miiaddr |= MDIO_CMD_MII_BUSY;
178
179 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
180
181 start = get_timer(0);
182 while (get_timer(start) < timeout) {
183 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
184 return readl(priv->mac_reg + EMAC_MII_DATA);
185 udelay(10);
186 };
187
188 return -1;
189 }
190
sun8i_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)191 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
192 u16 val)
193 {
194 struct udevice *dev = bus->priv;
195 struct emac_eth_dev *priv = dev_get_priv(dev);
196 ulong start;
197 u32 miiaddr = 0;
198 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
199
200 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
201 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
202 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
203
204 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
205 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
206 MDIO_CMD_MII_PHY_ADDR_MASK;
207
208 miiaddr |= MDIO_CMD_MII_WRITE;
209 miiaddr |= MDIO_CMD_MII_BUSY;
210
211 writel(val, priv->mac_reg + EMAC_MII_DATA);
212 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
213
214 start = get_timer(0);
215 while (get_timer(start) < timeout) {
216 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
217 MDIO_CMD_MII_BUSY)) {
218 ret = 0;
219 break;
220 }
221 udelay(10);
222 };
223
224 return ret;
225 }
226
_sun8i_write_hwaddr(struct emac_eth_dev * priv,u8 * mac_id)227 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
228 {
229 u32 macid_lo, macid_hi;
230
231 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
232 (mac_id[3] << 24);
233 macid_hi = mac_id[4] + (mac_id[5] << 8);
234
235 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
236 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
237
238 return 0;
239 }
240
sun8i_adjust_link(struct emac_eth_dev * priv,struct phy_device * phydev)241 static void sun8i_adjust_link(struct emac_eth_dev *priv,
242 struct phy_device *phydev)
243 {
244 u32 v;
245
246 v = readl(priv->mac_reg + EMAC_CTL0);
247
248 if (phydev->duplex)
249 v |= BIT(0);
250 else
251 v &= ~BIT(0);
252
253 v &= ~0x0C;
254
255 switch (phydev->speed) {
256 case 1000:
257 break;
258 case 100:
259 v |= BIT(2);
260 v |= BIT(3);
261 break;
262 case 10:
263 v |= BIT(3);
264 break;
265 }
266 writel(v, priv->mac_reg + EMAC_CTL0);
267 }
268
sun8i_emac_set_syscon_ephy(struct emac_eth_dev * priv,u32 * reg)269 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
270 {
271 if (priv->use_internal_phy) {
272 /* H3 based SoC's that has an Internal 100MBit PHY
273 * needs to be configured and powered up before use
274 */
275 *reg &= ~H3_EPHY_DEFAULT_MASK;
276 *reg |= H3_EPHY_DEFAULT_VALUE;
277 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
278 *reg &= ~H3_EPHY_SHUTDOWN;
279 *reg |= H3_EPHY_SELECT;
280 } else
281 /* This is to select External Gigabit PHY on
282 * the boards with H3 SoC.
283 */
284 *reg &= ~H3_EPHY_SELECT;
285
286 return 0;
287 }
288
sun8i_emac_set_syscon(struct sun8i_eth_pdata * pdata,struct emac_eth_dev * priv)289 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
290 struct emac_eth_dev *priv)
291 {
292 int ret;
293 u32 reg;
294
295 if (priv->variant == R40_GMAC) {
296 /* Select RGMII for R40 */
297 reg = readl(priv->sysctl_reg + 0x164);
298 reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
299 CCM_GMAC_CTRL_GPIT_RGMII |
300 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
301
302 writel(reg, priv->sysctl_reg + 0x164);
303 return 0;
304 }
305
306 reg = readl(priv->sysctl_reg + 0x30);
307
308 if (priv->variant == H3_EMAC) {
309 ret = sun8i_emac_set_syscon_ephy(priv, ®);
310 if (ret)
311 return ret;
312 }
313
314 reg &= ~(SC_ETCS_MASK | SC_EPIT);
315 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
316 reg &= ~SC_RMII_EN;
317
318 switch (priv->interface) {
319 case PHY_INTERFACE_MODE_MII:
320 /* default */
321 break;
322 case PHY_INTERFACE_MODE_RGMII:
323 reg |= SC_EPIT | SC_ETCS_INT_GMII;
324 break;
325 case PHY_INTERFACE_MODE_RMII:
326 if (priv->variant == H3_EMAC ||
327 priv->variant == A64_EMAC) {
328 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
329 break;
330 }
331 /* RMII not supported on A83T */
332 default:
333 debug("%s: Invalid PHY interface\n", __func__);
334 return -EINVAL;
335 }
336
337 if (pdata->tx_delay_ps)
338 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
339 & SC_ETXDC_MASK;
340
341 if (pdata->rx_delay_ps)
342 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
343 & SC_ERXDC_MASK;
344
345 writel(reg, priv->sysctl_reg + 0x30);
346
347 return 0;
348 }
349
sun8i_phy_init(struct emac_eth_dev * priv,void * dev)350 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
351 {
352 struct phy_device *phydev;
353
354 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
355 if (!phydev)
356 return -ENODEV;
357
358 phy_connect_dev(phydev, dev);
359
360 priv->phydev = phydev;
361 phy_config(priv->phydev);
362
363 return 0;
364 }
365
rx_descs_init(struct emac_eth_dev * priv)366 static void rx_descs_init(struct emac_eth_dev *priv)
367 {
368 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
369 char *rxbuffs = &priv->rxbuffer[0];
370 struct emac_dma_desc *desc_p;
371 u32 idx;
372
373 /* flush Rx buffers */
374 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
375 RX_TOTAL_BUFSIZE);
376
377 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
378 desc_p = &desc_table_p[idx];
379 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
380 ;
381 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
382 desc_p->st |= CONFIG_ETH_RXSIZE;
383 desc_p->status = BIT(31);
384 }
385
386 /* Correcting the last pointer of the chain */
387 desc_p->next = (uintptr_t)&desc_table_p[0];
388
389 flush_dcache_range((uintptr_t)priv->rx_chain,
390 (uintptr_t)priv->rx_chain +
391 sizeof(priv->rx_chain));
392
393 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
394 priv->rx_currdescnum = 0;
395 }
396
tx_descs_init(struct emac_eth_dev * priv)397 static void tx_descs_init(struct emac_eth_dev *priv)
398 {
399 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
400 char *txbuffs = &priv->txbuffer[0];
401 struct emac_dma_desc *desc_p;
402 u32 idx;
403
404 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
405 desc_p = &desc_table_p[idx];
406 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
407 ;
408 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
409 desc_p->status = (1 << 31);
410 desc_p->st = 0;
411 }
412
413 /* Correcting the last pointer of the chain */
414 desc_p->next = (uintptr_t)&desc_table_p[0];
415
416 /* Flush all Tx buffer descriptors */
417 flush_dcache_range((uintptr_t)priv->tx_chain,
418 (uintptr_t)priv->tx_chain +
419 sizeof(priv->tx_chain));
420
421 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
422 priv->tx_currdescnum = 0;
423 }
424
_sun8i_emac_eth_init(struct emac_eth_dev * priv,u8 * enetaddr)425 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
426 {
427 u32 reg, v;
428 int timeout = 100;
429
430 reg = readl((priv->mac_reg + EMAC_CTL1));
431
432 if (!(reg & 0x1)) {
433 /* Soft reset MAC */
434 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
435 do {
436 reg = readl(priv->mac_reg + EMAC_CTL1);
437 } while ((reg & 0x01) != 0 && (--timeout));
438 if (!timeout) {
439 printf("%s: Timeout\n", __func__);
440 return -1;
441 }
442 }
443
444 /* Rewrite mac address after reset */
445 _sun8i_write_hwaddr(priv, enetaddr);
446
447 v = readl(priv->mac_reg + EMAC_TX_CTL1);
448 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
449 v |= BIT(1);
450 writel(v, priv->mac_reg + EMAC_TX_CTL1);
451
452 v = readl(priv->mac_reg + EMAC_RX_CTL1);
453 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
454 * complete frame has been written to RX DMA FIFO
455 */
456 v |= BIT(1);
457 writel(v, priv->mac_reg + EMAC_RX_CTL1);
458
459 /* DMA */
460 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
461
462 /* Initialize rx/tx descriptors */
463 rx_descs_init(priv);
464 tx_descs_init(priv);
465
466 /* PHY Start Up */
467 phy_startup(priv->phydev);
468
469 sun8i_adjust_link(priv, priv->phydev);
470
471 /* Start RX DMA */
472 v = readl(priv->mac_reg + EMAC_RX_CTL1);
473 v |= BIT(30);
474 writel(v, priv->mac_reg + EMAC_RX_CTL1);
475 /* Start TX DMA */
476 v = readl(priv->mac_reg + EMAC_TX_CTL1);
477 v |= BIT(30);
478 writel(v, priv->mac_reg + EMAC_TX_CTL1);
479
480 /* Enable RX/TX */
481 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
482 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
483
484 return 0;
485 }
486
parse_phy_pins(struct udevice * dev)487 static int parse_phy_pins(struct udevice *dev)
488 {
489 struct emac_eth_dev *priv = dev_get_priv(dev);
490 int offset;
491 const char *pin_name;
492 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
493
494 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
495 "pinctrl-0");
496 if (offset < 0) {
497 printf("WARNING: emac: cannot find pinctrl-0 node\n");
498 return offset;
499 }
500
501 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
502 "drive-strength", ~0);
503 if (drive != ~0) {
504 if (drive <= 10)
505 drive = SUN4I_PINCTRL_10_MA;
506 else if (drive <= 20)
507 drive = SUN4I_PINCTRL_20_MA;
508 else if (drive <= 30)
509 drive = SUN4I_PINCTRL_30_MA;
510 else
511 drive = SUN4I_PINCTRL_40_MA;
512 }
513
514 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
515 pull = SUN4I_PINCTRL_PULL_UP;
516 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
517 pull = SUN4I_PINCTRL_PULL_DOWN;
518
519 for (i = 0; ; i++) {
520 int pin;
521
522 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
523 "pins", i, NULL);
524 if (!pin_name)
525 break;
526
527 pin = sunxi_name_to_gpio(pin_name);
528 if (pin < 0)
529 continue;
530
531 if (priv->variant == H3_EMAC)
532 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
533 else if (priv->variant == R40_GMAC)
534 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
535 else
536 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
537
538 if (drive != ~0)
539 sunxi_gpio_set_drv(pin, drive);
540 if (pull != ~0)
541 sunxi_gpio_set_pull(pin, pull);
542 }
543
544 if (!i) {
545 printf("WARNING: emac: cannot find pins property\n");
546 return -2;
547 }
548
549 return 0;
550 }
551
_sun8i_eth_recv(struct emac_eth_dev * priv,uchar ** packetp)552 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
553 {
554 u32 status, desc_num = priv->rx_currdescnum;
555 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
556 int length = -EAGAIN;
557 int good_packet = 1;
558 uintptr_t desc_start = (uintptr_t)desc_p;
559 uintptr_t desc_end = desc_start +
560 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
561
562 ulong data_start = (uintptr_t)desc_p->buf_addr;
563 ulong data_end;
564
565 /* Invalidate entire buffer descriptor */
566 invalidate_dcache_range(desc_start, desc_end);
567
568 status = desc_p->status;
569
570 /* Check for DMA own bit */
571 if (!(status & BIT(31))) {
572 length = (desc_p->status >> 16) & 0x3FFF;
573
574 if (length < 0x40) {
575 good_packet = 0;
576 debug("RX: Bad Packet (runt)\n");
577 }
578
579 data_end = data_start + length;
580 /* Invalidate received data */
581 invalidate_dcache_range(rounddown(data_start,
582 ARCH_DMA_MINALIGN),
583 roundup(data_end,
584 ARCH_DMA_MINALIGN));
585 if (good_packet) {
586 if (length > CONFIG_ETH_RXSIZE) {
587 printf("Received packet is too big (len=%d)\n",
588 length);
589 return -EMSGSIZE;
590 }
591 *packetp = (uchar *)(ulong)desc_p->buf_addr;
592 return length;
593 }
594 }
595
596 return length;
597 }
598
_sun8i_emac_eth_send(struct emac_eth_dev * priv,void * packet,int len)599 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
600 int len)
601 {
602 u32 v, desc_num = priv->tx_currdescnum;
603 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
604 uintptr_t desc_start = (uintptr_t)desc_p;
605 uintptr_t desc_end = desc_start +
606 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
607
608 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
609 uintptr_t data_end = data_start +
610 roundup(len, ARCH_DMA_MINALIGN);
611
612 /* Invalidate entire buffer descriptor */
613 invalidate_dcache_range(desc_start, desc_end);
614
615 desc_p->st = len;
616 /* Mandatory undocumented bit */
617 desc_p->st |= BIT(24);
618
619 memcpy((void *)data_start, packet, len);
620
621 /* Flush data to be sent */
622 flush_dcache_range(data_start, data_end);
623
624 /* frame end */
625 desc_p->st |= BIT(30);
626 desc_p->st |= BIT(31);
627
628 /*frame begin */
629 desc_p->st |= BIT(29);
630 desc_p->status = BIT(31);
631
632 /*Descriptors st and status field has changed, so FLUSH it */
633 flush_dcache_range(desc_start, desc_end);
634
635 /* Move to next Descriptor and wrap around */
636 if (++desc_num >= CONFIG_TX_DESCR_NUM)
637 desc_num = 0;
638 priv->tx_currdescnum = desc_num;
639
640 /* Start the DMA */
641 v = readl(priv->mac_reg + EMAC_TX_CTL1);
642 v |= BIT(31);/* mandatory */
643 v |= BIT(30);/* mandatory */
644 writel(v, priv->mac_reg + EMAC_TX_CTL1);
645
646 return 0;
647 }
648
sun8i_eth_write_hwaddr(struct udevice * dev)649 static int sun8i_eth_write_hwaddr(struct udevice *dev)
650 {
651 struct eth_pdata *pdata = dev_get_platdata(dev);
652 struct emac_eth_dev *priv = dev_get_priv(dev);
653
654 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
655 }
656
sun8i_emac_board_setup(struct emac_eth_dev * priv)657 static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
658 {
659 int ret;
660
661 ret = clk_enable(&priv->tx_clk);
662 if (ret) {
663 dev_err(dev, "failed to enable TX clock\n");
664 return ret;
665 }
666
667 if (reset_valid(&priv->tx_rst)) {
668 ret = reset_deassert(&priv->tx_rst);
669 if (ret) {
670 dev_err(dev, "failed to deassert TX reset\n");
671 goto err_tx_clk;
672 }
673 }
674
675 /* Only H3/H5 have clock controls for internal EPHY */
676 if (clk_valid(&priv->ephy_clk)) {
677 ret = clk_enable(&priv->ephy_clk);
678 if (ret) {
679 dev_err(dev, "failed to enable EPHY TX clock\n");
680 return ret;
681 }
682 }
683
684 if (reset_valid(&priv->ephy_rst)) {
685 ret = reset_deassert(&priv->ephy_rst);
686 if (ret) {
687 dev_err(dev, "failed to deassert EPHY TX clock\n");
688 return ret;
689 }
690 }
691
692 return 0;
693
694 err_tx_clk:
695 clk_disable(&priv->tx_clk);
696 return ret;
697 }
698
699 #if defined(CONFIG_DM_GPIO)
sun8i_mdio_reset(struct mii_dev * bus)700 static int sun8i_mdio_reset(struct mii_dev *bus)
701 {
702 struct udevice *dev = bus->priv;
703 struct emac_eth_dev *priv = dev_get_priv(dev);
704 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
705 int ret;
706
707 if (!dm_gpio_is_valid(&priv->reset_gpio))
708 return 0;
709
710 /* reset the phy */
711 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
712 if (ret)
713 return ret;
714
715 udelay(pdata->reset_delays[0]);
716
717 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
718 if (ret)
719 return ret;
720
721 udelay(pdata->reset_delays[1]);
722
723 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
724 if (ret)
725 return ret;
726
727 udelay(pdata->reset_delays[2]);
728
729 return 0;
730 }
731 #endif
732
sun8i_mdio_init(const char * name,struct udevice * priv)733 static int sun8i_mdio_init(const char *name, struct udevice *priv)
734 {
735 struct mii_dev *bus = mdio_alloc();
736
737 if (!bus) {
738 debug("Failed to allocate MDIO bus\n");
739 return -ENOMEM;
740 }
741
742 bus->read = sun8i_mdio_read;
743 bus->write = sun8i_mdio_write;
744 snprintf(bus->name, sizeof(bus->name), name);
745 bus->priv = (void *)priv;
746 #if defined(CONFIG_DM_GPIO)
747 bus->reset = sun8i_mdio_reset;
748 #endif
749
750 return mdio_register(bus);
751 }
752
sun8i_emac_eth_start(struct udevice * dev)753 static int sun8i_emac_eth_start(struct udevice *dev)
754 {
755 struct eth_pdata *pdata = dev_get_platdata(dev);
756
757 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
758 }
759
sun8i_emac_eth_send(struct udevice * dev,void * packet,int length)760 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
761 {
762 struct emac_eth_dev *priv = dev_get_priv(dev);
763
764 return _sun8i_emac_eth_send(priv, packet, length);
765 }
766
sun8i_emac_eth_recv(struct udevice * dev,int flags,uchar ** packetp)767 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
768 {
769 struct emac_eth_dev *priv = dev_get_priv(dev);
770
771 return _sun8i_eth_recv(priv, packetp);
772 }
773
_sun8i_free_pkt(struct emac_eth_dev * priv)774 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
775 {
776 u32 desc_num = priv->rx_currdescnum;
777 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
778 uintptr_t desc_start = (uintptr_t)desc_p;
779 uintptr_t desc_end = desc_start +
780 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
781
782 /* Make the current descriptor valid again */
783 desc_p->status |= BIT(31);
784
785 /* Flush Status field of descriptor */
786 flush_dcache_range(desc_start, desc_end);
787
788 /* Move to next desc and wrap-around condition. */
789 if (++desc_num >= CONFIG_RX_DESCR_NUM)
790 desc_num = 0;
791 priv->rx_currdescnum = desc_num;
792
793 return 0;
794 }
795
sun8i_eth_free_pkt(struct udevice * dev,uchar * packet,int length)796 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
797 int length)
798 {
799 struct emac_eth_dev *priv = dev_get_priv(dev);
800
801 return _sun8i_free_pkt(priv);
802 }
803
sun8i_emac_eth_stop(struct udevice * dev)804 static void sun8i_emac_eth_stop(struct udevice *dev)
805 {
806 struct emac_eth_dev *priv = dev_get_priv(dev);
807
808 /* Stop Rx/Tx transmitter */
809 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
810 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
811
812 /* Stop TX DMA */
813 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
814
815 phy_shutdown(priv->phydev);
816 }
817
sun8i_emac_eth_probe(struct udevice * dev)818 static int sun8i_emac_eth_probe(struct udevice *dev)
819 {
820 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
821 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
822 struct emac_eth_dev *priv = dev_get_priv(dev);
823 int ret;
824
825 priv->mac_reg = (void *)pdata->iobase;
826
827 ret = sun8i_emac_board_setup(priv);
828 if (ret)
829 return ret;
830
831 sun8i_emac_set_syscon(sun8i_pdata, priv);
832
833 sun8i_mdio_init(dev->name, dev);
834 priv->bus = miiphy_get_dev_by_name(dev->name);
835
836 return sun8i_phy_init(priv, dev);
837 }
838
839 static const struct eth_ops sun8i_emac_eth_ops = {
840 .start = sun8i_emac_eth_start,
841 .write_hwaddr = sun8i_eth_write_hwaddr,
842 .send = sun8i_emac_eth_send,
843 .recv = sun8i_emac_eth_recv,
844 .free_pkt = sun8i_eth_free_pkt,
845 .stop = sun8i_emac_eth_stop,
846 };
847
sun8i_get_ephy_nodes(struct emac_eth_dev * priv)848 static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
849 {
850 int emac_node, ephy_node, ret, ephy_handle;
851
852 emac_node = fdt_path_offset(gd->fdt_blob,
853 "/soc/ethernet@1c30000");
854 if (emac_node < 0) {
855 debug("failed to get emac node\n");
856 return emac_node;
857 }
858 ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
859 emac_node, "phy-handle");
860
861 /* look for mdio-mux node for internal PHY node */
862 ephy_node = fdt_path_offset(gd->fdt_blob,
863 "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
864 if (ephy_node < 0) {
865 debug("failed to get mdio-mux with internal PHY\n");
866 return ephy_node;
867 }
868
869 /* This is not the phy we are looking for */
870 if (ephy_node != ephy_handle)
871 return 0;
872
873 ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
874 "allwinner,sun8i-h3-mdio-internal");
875 if (ret < 0) {
876 debug("failed to find mdio-internal node\n");
877 return ret;
878 }
879
880 ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
881 &priv->ephy_clk);
882 if (ret) {
883 dev_err(dev, "failed to get EPHY TX clock\n");
884 return ret;
885 }
886
887 ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
888 &priv->ephy_rst);
889 if (ret) {
890 dev_err(dev, "failed to get EPHY TX reset\n");
891 return ret;
892 }
893
894 priv->use_internal_phy = true;
895
896 return 0;
897 }
898
sun8i_emac_eth_ofdata_to_platdata(struct udevice * dev)899 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
900 {
901 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
902 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
903 struct emac_eth_dev *priv = dev_get_priv(dev);
904 const char *phy_mode;
905 const fdt32_t *reg;
906 int node = dev_of_offset(dev);
907 int offset = 0;
908 #ifdef CONFIG_DM_GPIO
909 int reset_flags = GPIOD_IS_OUT;
910 #endif
911 int ret;
912
913 pdata->iobase = devfdt_get_addr(dev);
914 if (pdata->iobase == FDT_ADDR_T_NONE) {
915 debug("%s: Cannot find MAC base address\n", __func__);
916 return -EINVAL;
917 }
918
919 priv->variant = dev_get_driver_data(dev);
920
921 if (!priv->variant) {
922 printf("%s: Missing variant\n", __func__);
923 return -EINVAL;
924 }
925
926 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
927 if (ret) {
928 dev_err(dev, "failed to get TX clock\n");
929 return ret;
930 }
931
932 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
933 if (ret && ret != -ENOENT) {
934 dev_err(dev, "failed to get TX reset\n");
935 return ret;
936 }
937
938 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
939 if (offset < 0) {
940 debug("%s: cannot find syscon node\n", __func__);
941 return -EINVAL;
942 }
943
944 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
945 if (!reg) {
946 debug("%s: cannot find reg property in syscon node\n",
947 __func__);
948 return -EINVAL;
949 }
950 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
951 offset, reg);
952 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
953 debug("%s: Cannot find syscon base address\n", __func__);
954 return -EINVAL;
955 }
956
957 pdata->phy_interface = -1;
958 priv->phyaddr = -1;
959 priv->use_internal_phy = false;
960
961 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
962 if (offset < 0) {
963 debug("%s: Cannot find PHY address\n", __func__);
964 return -EINVAL;
965 }
966 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
967
968 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
969
970 if (phy_mode)
971 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
972 printf("phy interface%d\n", pdata->phy_interface);
973
974 if (pdata->phy_interface == -1) {
975 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
976 return -EINVAL;
977 }
978
979 if (priv->variant == H3_EMAC) {
980 ret = sun8i_get_ephy_nodes(priv);
981 if (ret)
982 return ret;
983 }
984
985 priv->interface = pdata->phy_interface;
986
987 if (!priv->use_internal_phy)
988 parse_phy_pins(dev);
989
990 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
991 "allwinner,tx-delay-ps", 0);
992 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
993 printf("%s: Invalid TX delay value %d\n", __func__,
994 sun8i_pdata->tx_delay_ps);
995
996 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
997 "allwinner,rx-delay-ps", 0);
998 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
999 printf("%s: Invalid RX delay value %d\n", __func__,
1000 sun8i_pdata->rx_delay_ps);
1001
1002 #ifdef CONFIG_DM_GPIO
1003 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
1004 "snps,reset-active-low"))
1005 reset_flags |= GPIOD_ACTIVE_LOW;
1006
1007 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
1008 &priv->reset_gpio, reset_flags);
1009
1010 if (ret == 0) {
1011 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
1012 "snps,reset-delays-us",
1013 sun8i_pdata->reset_delays, 3);
1014 } else if (ret == -ENOENT) {
1015 ret = 0;
1016 }
1017 #endif
1018
1019 return 0;
1020 }
1021
1022 static const struct udevice_id sun8i_emac_eth_ids[] = {
1023 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1024 {.compatible = "allwinner,sun50i-a64-emac",
1025 .data = (uintptr_t)A64_EMAC },
1026 {.compatible = "allwinner,sun8i-a83t-emac",
1027 .data = (uintptr_t)A83T_EMAC },
1028 {.compatible = "allwinner,sun8i-r40-gmac",
1029 .data = (uintptr_t)R40_GMAC },
1030 { }
1031 };
1032
1033 U_BOOT_DRIVER(eth_sun8i_emac) = {
1034 .name = "eth_sun8i_emac",
1035 .id = UCLASS_ETH,
1036 .of_match = sun8i_emac_eth_ids,
1037 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
1038 .probe = sun8i_emac_eth_probe,
1039 .ops = &sun8i_emac_eth_ops,
1040 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
1041 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
1042 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1043 };
1044