1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Watchdog driver for MediaTek SoCs
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <wdt.h>
12 #include <asm/io.h>
13
14 #define MTK_WDT_MODE 0x00
15 #define MTK_WDT_LENGTH 0x04
16 #define MTK_WDT_RESTART 0x08
17 #define MTK_WDT_STATUS 0x0c
18 #define MTK_WDT_INTERVAL 0x10
19 #define MTK_WDT_SWRST 0x14
20 #define MTK_WDT_REQ_MODE 0x30
21 #define MTK_WDT_DEBUG_CTL 0x40
22
23 #define WDT_MODE_KEY (0x22 << 24)
24 #define WDT_MODE_EN BIT(0)
25 #define WDT_MODE_EXTPOL BIT(1)
26 #define WDT_MODE_EXTEN BIT(2)
27 #define WDT_MODE_IRQ_EN BIT(3)
28 #define WDT_MODE_DUAL_EN BIT(6)
29
30 #define WDT_LENGTH_KEY 0x8
31 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
32
33 #define WDT_RESTART_KEY 0x1971
34 #define WDT_SWRST_KEY 0x1209
35
36 struct mtk_wdt_priv {
37 void __iomem *base;
38 };
39
mtk_wdt_reset(struct udevice * dev)40 static int mtk_wdt_reset(struct udevice *dev)
41 {
42 struct mtk_wdt_priv *priv = dev_get_priv(dev);
43
44 /* Reload watchdog duration */
45 writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
46
47 return 0;
48 }
49
mtk_wdt_stop(struct udevice * dev)50 static int mtk_wdt_stop(struct udevice *dev)
51 {
52 struct mtk_wdt_priv *priv = dev_get_priv(dev);
53
54 clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
55
56 return 0;
57 }
58
mtk_wdt_expire_now(struct udevice * dev,ulong flags)59 static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
60 {
61 struct mtk_wdt_priv *priv = dev_get_priv(dev);
62
63 /* Kick watchdog to prevent counter == 0 */
64 writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
65
66 /* Reset */
67 writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
68 hang();
69
70 return 0;
71 }
72
mtk_wdt_set_timeout(struct udevice * dev,u64 timeout_ms)73 static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
74 {
75 struct mtk_wdt_priv *priv = dev_get_priv(dev);
76 u64 timeout_us;
77 u32 timeout_cc;
78 u32 length;
79
80 /*
81 * One WDT_LENGTH count is 512 ticks of the wdt clock
82 * Clock runs at 32768 Hz
83 * e.g. 15.625 ms per count (nominal)
84 * We want the ceiling after dividing timeout_ms by 15.625 ms
85 * We add 15624 prior to the divide to implement the ceiling
86 * We prevent over-flow by clamping the timeout_ms value here
87 * as the maximum WDT_LENGTH counts is 1023 -> 15.984375 sec
88 * We also enforce a minimum of 1 count
89 * Many watchdog peripherals have a self-imposed count of 1
90 * that is added to the register counts.
91 * The MediaTek docs lack details to know if this is the case here.
92 * So we enforce a minimum of 1 to guarantee operation.
93 */
94 if (timeout_ms > 15984)
95 timeout_ms = 15984;
96
97 timeout_us = timeout_ms * 1000;
98 timeout_cc = (15624 + timeout_us) / 15625;
99 if (timeout_cc == 0)
100 timeout_cc = 1;
101
102 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
103 writel(length, priv->base + MTK_WDT_LENGTH);
104 }
105
mtk_wdt_start(struct udevice * dev,u64 timeout_ms,ulong flags)106 static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
107 {
108 struct mtk_wdt_priv *priv = dev_get_priv(dev);
109
110 mtk_wdt_set_timeout(dev, timeout_ms);
111
112 mtk_wdt_reset(dev);
113
114 /* Enable watchdog reset signal */
115 setbits_le32(priv->base + MTK_WDT_MODE,
116 WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
117
118 return 0;
119 }
120
mtk_wdt_probe(struct udevice * dev)121 static int mtk_wdt_probe(struct udevice *dev)
122 {
123 struct mtk_wdt_priv *priv = dev_get_priv(dev);
124
125 priv->base = dev_read_addr_ptr(dev);
126 if (!priv->base)
127 return -ENOENT;
128
129 /* Clear status */
130 clrsetbits_le32(priv->base + MTK_WDT_MODE,
131 WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
132
133 return mtk_wdt_stop(dev);
134 }
135
136 static const struct wdt_ops mtk_wdt_ops = {
137 .start = mtk_wdt_start,
138 .reset = mtk_wdt_reset,
139 .stop = mtk_wdt_stop,
140 .expire_now = mtk_wdt_expire_now,
141 };
142
143 static const struct udevice_id mtk_wdt_ids[] = {
144 { .compatible = "mediatek,wdt"},
145 {}
146 };
147
148 U_BOOT_DRIVER(mtk_wdt) = {
149 .name = "mtk_wdt",
150 .id = UCLASS_WDT,
151 .of_match = mtk_wdt_ids,
152 .priv_auto_alloc_size = sizeof(struct mtk_wdt_priv),
153 .probe = mtk_wdt_probe,
154 .ops = &mtk_wdt_ops,
155 .flags = DM_FLAG_PRE_RELOC,
156 };
157