Lines Matching full:error
41 LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (bad next gate)"; in RunDataIntegrityCheck()
42 LOG_COMPILER(ERROR) << "at: " << std::dec << gate; in RunDataIntegrityCheck()
55 … LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (out of bound access)"; in RunDataIntegrityCheck()
56 LOG_COMPILER(ERROR) << "at: " << std::dec << out; in RunDataIntegrityCheck()
64 … LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (corrupted in list)"; in RunDataIntegrityCheck()
65 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate); in RunDataIntegrityCheck()
69 … LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (invalid in address)"; in RunDataIntegrityCheck()
70 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate); in RunDataIntegrityCheck()
79 … LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (corrupted out list)"; in RunDataIntegrityCheck()
80 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate); in RunDataIntegrityCheck()
84 … LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (invalid out address)"; in RunDataIntegrityCheck()
85 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate); in RunDataIntegrityCheck()
92 … LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (corrupted out list)"; in RunDataIntegrityCheck()
93 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate); in RunDataIntegrityCheck()
97 … LOG_COMPILER(ERROR) << "[Verifier][Error] Circuit data is corrupted (invalid out address)"; in RunDataIntegrityCheck()
98 LOG_COMPILER(ERROR) << "id: " << std::dec << circuit->GetId(gate); in RunDataIntegrityCheck()
125 LOG_COMPILER(ERROR) << "[Verifier][Error] CFG is not sound"; in RunCFGSoundnessCheck()
126 LOG_COMPILER(ERROR) << "Proof:"; in RunCFGSoundnessCheck()
127 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(predGate) << ") is pred of " in RunCFGSoundnessCheck()
129 … LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(bbGate) << ") is reachable from entry"; in RunCFGSoundnessCheck()
130 … LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(predGate) << ") is unreachable from entry"; in RunCFGSoundnessCheck()
165 LOG_COMPILER(ERROR) << in RunCFGIsDAGCheck()
166 "[Verifier][Error] CFG without loop back edges is not a directed acyclic graph"; in RunCFGIsDAGCheck()
167 LOG_COMPILER(ERROR) << "Proof:"; in RunCFGIsDAGCheck()
168 LOG_COMPILER(ERROR) << "(id=" << gateAcc.GetId(*use) << ") is succ of " in RunCFGIsDAGCheck()
170 LOG_COMPILER(ERROR) << "(id=" << gateAcc.GetId(cur) << ") is reachable from " in RunCFGIsDAGCheck()
202 LOG_COMPILER(ERROR) << "[Verifier][Error] CFG is not reducible"; in RunCFGReducibilityCheck()
203 LOG_COMPILER(ERROR) << "Proof:"; in RunCFGReducibilityCheck()
204 … LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(*use) << ") is loop back succ of " in RunCFGReducibilityCheck()
206 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(*use) << ") does not dominate " in RunCFGReducibilityCheck()
241 … LOG_COMPILER(ERROR) << "[Verifier][Error] Fixed gates relationship is not consistent"; in RunFixedGatesRelationsCheck()
242 LOG_COMPILER(ERROR) << "Proof:"; in RunFixedGatesRelationsCheck()
243 LOG_COMPILER(ERROR) << "Fixed gate (id=" in RunFixedGatesRelationsCheck()
247 LOG_COMPILER(ERROR) << "BB_" << bbGatesAddrToIdx.at(circuit->GetIn(predGate, 0)) in RunFixedGatesRelationsCheck()
321 LOG_COMPILER(ERROR) << in RunFlowCyclesFind()
322 … "[Verifier][Error] Found a data or depend flow cycle without passing selectors"; in RunFlowCyclesFind()
323 LOG_COMPILER(ERROR) << "Proof:"; in RunFlowCyclesFind()
324 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(prev) << ") is prev of " in RunFlowCyclesFind()
326 LOG_COMPILER(ERROR) << "(id=" << circuit->GetId(prev) << ") is reachable from " in RunFlowCyclesFind()
346 LOG_COMPILER(ERROR) << "Path:"; in RunFlowCyclesFind()
403 …LOG_COMPILER(ERROR) << "[Verifier][Error] Bounds of gate (id=" << item.first << ") is not consiste… in RunSchedulingBoundsCheck()
404 LOG_COMPILER(ERROR) << "Proof:"; in RunSchedulingBoundsCheck()
405 LOG_COMPILER(ERROR) << "Upper bound is BB_" << upperBound.at(item.first); in RunSchedulingBoundsCheck()
406 LOG_COMPILER(ERROR) << "Lower bound is BB_" << lowerBound.at(item.first); in RunSchedulingBoundsCheck()
430 … LOG_COMPILER(ERROR) << "[Verifier][Fail] Circuit data integrity verifier failed, " << methodName; in Run()
440 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunStateGatesCheck failed"; in Run()
446 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunCFGSoundnessCheck failed"; in Run()
452 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunCFGIsDAGCheck failed"; in Run()
521 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunCFGReducibilityCheck failed"; in Run()
529 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunFixedGatesCheck failed"; in Run()
535 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunFixedGatesRelationsCheck failed"; in Run()
542 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunFlowCyclesFind failed"; in Run()
548 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunSchedulableGatesCheck failed"; in Run()
554 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunPrologGatesCheck failed"; in Run()
560 LOG_COMPILER(ERROR) << "[Verifier][Fail] RunSchedulingBoundsCheck failed"; in Run()