Lines Matching +full:fpga +full:- +full:based
2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
11 The Device Feature List (DFL) FPGA framework (and drivers according to
14 configure, enumerate, open and access FPGA accelerators on platforms which
16 enables system level management functions such as FPGA reconfiguration.
23 walk through these predefined data structures to enumerate FPGA features:
24 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
28 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
31 +----------+ | | Feature | | | Feature | | | Feature |
32 | Next_DFH |--+ +----------+ | +----------+ | +----------+
33 +----------+ | Next_DFH |--+ | Next_DFH |--+ | Next_DFH |--> NULL
34 | ID | +----------+ +----------+ +----------+
35 +----------+ | ID | | ID | | ID |
36 | Next_AFU |--+ +----------+ +----------+ +----------+
37 +----------+ | | Feature | | Feature | | Feature |
40 | Set | | +----------+ +----------+ +----------+
41 +----------+ | Header
42 +-->+----------+
45 +----------+
46 | Next_DFH |--> NULL
47 +----------+
49 +----------+
53 +----------+
55 FPGA Interface Unit (FIU) represents a standalone functional unit for the
56 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
59 Accelerated Function Unit (AFU) represents a FPGA programmable region and
74 and can be implemented in register regions of any FPGA device.
77 FIU - FME (FPGA Management Engine)
79 The FPGA Management Engine performs reconfiguration and other infrastructure
80 functions. Each FPGA device only has one FME.
82 User-space applications can acquire exclusive access to the FME using open(),
87 - Get driver API version (DFL_FPGA_GET_API_VERSION)
88 - Check for extensions (DFL_FPGA_CHECK_EXTENSION)
89 - Program bitstream (DFL_FPGA_FME_PORT_PR)
90 - Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN)
91 - Release port from PF (DFL_FPGA_FME_PORT_RELEASE)
92 - Get number of irqs of FME global error (DFL_FPGA_FME_ERR_GET_IRQ_NUM)
93 - Set interrupt trigger for FME error (DFL_FPGA_FME_ERR_SET_IRQ)
96 (/sys/class/fpga_region/regionX/dfl-fme.n/):
99 bitstream_id indicates version of the static FPGA region.
102 bitstream_metadata includes detailed information of static FPGA region,
106 one FPGA device may have more than one port, this sysfs interface indicates
107 how many ports the FPGA device has.
129 FIU - PORT
131 A port represents the interface between the static FPGA fabric and a partially
133 to the accelerator and exposes features such as reset and debug. Each FPGA
140 used for accelerator-specific control registers.
142 User-space applications can acquire exclusive access to an AFU attached to a
147 - Get driver API version (DFL_FPGA_GET_API_VERSION)
148 - Check for extensions (DFL_FPGA_CHECK_EXTENSION)
149 - Get port info (DFL_FPGA_PORT_GET_INFO)
150 - Get MMIO region info (DFL_FPGA_PORT_GET_REGION_INFO)
151 - Map DMA buffer (DFL_FPGA_PORT_DMA_MAP)
152 - Unmap DMA buffer (DFL_FPGA_PORT_DMA_UNMAP)
153 - Reset AFU (DFL_FPGA_PORT_RESET)
154 - Get number of irqs of port error (DFL_FPGA_PORT_ERR_GET_IRQ_NUM)
155 - Set interrupt trigger for port error (DFL_FPGA_PORT_ERR_SET_IRQ)
156 - Get number of irqs of UINT (DFL_FPGA_PORT_UINT_GET_IRQ_NUM)
157 - Set interrupt trigger for UINT (DFL_FPGA_PORT_UINT_SET_IRQ)
160 reset the FPGA Port and its AFU. Userspace can do Port
165 User-space applications can also mmap() accelerator MMIO regions.
168 (/sys/class/fpga_region/<regionX>/<dfl-port.m>/):
183 +----------+ +--------+ +--------+ +--------+
186 +----------+ +--------+ +--------+ +--------+
187 +-----------------------+
188 | FPGA Container Device | Device Feature List
189 | (FPGA Base Region) | Framework
190 +-----------------------+
191 ------------------------------------------------------------------
192 +----------------------------+
193 | FPGA DFL Device Module |
195 +----------------------------+
196 +------------------------+
197 | FPGA Hardware Device |
198 +------------------------+
201 (FPGA base region), discover feature devices and their private features from the
207 The FPGA DFL Device could be different hardwares, e.g. PCIe device, platform
212 (Please refer to drivers/fpga/dfl.c for detailed enumeration APIs).
214 The FPGA Management Engine (FME) driver is a platform driver which is loaded
216 provides the key features for FPGA management, including:
218 a) Expose static FPGA region information, e.g. version and metadata.
222 b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
223 bridges and FPGA regions during PR sub feature initialization. Once
225 common interface function from FPGA Region to complete the partial
228 Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
244 generated for the exact static FPGA region and targeted reconfigurable region
245 (port) of the FPGA, otherwise, the reconfiguration operation will fail and
248 the compat_id exposed by the target FPGA region. This check is usually done by
252 FPGA virtualization - PCIe SRIOV
254 This section describes the virtualization support on DFL based FPGA device to
256 (VM). This section only describes the PCIe based FPGA device with SRIOV support.
258 Features supported by the particular FPGA device are exposed through Device
263 +-------------------------------+ +-------------+
265 +-------------------------------+ +-------------+
268 +-----|------------|---------|--------------|-------+
270 | +-----+ +-------+ +-------+ +-------+ |
272 | +-----+ +-------+ +-------+ +-------+ |
275 | +-------+ +------+ +-------+ |
277 | +-------+ +------+ +-------+ |
279 | DFL based FPGA PCIe Device |
280 +---------------------------------------------------+
292 +-------++------++------+ |
294 | FPGA || FPGA || FPGA | |
296 +-------++------++------+ |
297 +-----------------------+ +--------+ | +--------+
300 +-----------------------+ +--------+ | +--------+
301 +-----------------------+ | +-----------------------+
302 | FPGA Container Device | | | FPGA Container Device |
303 | (FPGA Base Region) | | | (FPGA Base Region) |
304 +-----------------------+ | +-----------------------+
305 +------------------+ | +------------------+
306 | FPGA PCIE Module | | Virtual | FPGA PCIE Module |
307 +------------------+ Host | Machine +------------------+
308 -------------------------------------- | ------------------------------
309 +---------------+ | +---------------+
311 +---------------+ | +---------------+
313 FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device
316 * Finishes enumeration on both FPGA PCIe PF and VF device using common
349 This section introduces how applications enumerate the fpga device from
352 In the example below, two DFL based FPGA devices are installed in the host. Each
353 fpga device has one FME and two ports (AFUs).
355 FPGA regions are created under /sys/class/fpga_region/::
363 (e.g. "dfl-port.n" or "dfl-fme.m" is found), then it's the base
364 fpga region which represents the FPGA device.
368 /sys/class/fpga_region/region0/dfl-fme.0
369 /sys/class/fpga_region/region0/dfl-port.0
370 /sys/class/fpga_region/region0/dfl-port.1
373 /sys/class/fpga_region/region3/dfl-fme.1
374 /sys/class/fpga_region/region3/dfl-port.2
375 /sys/class/fpga_region/region3/dfl-port.3
380 /sys/class/fpga_region/<regionX>/<dfl-fme.n>/
381 /sys/class/fpga_region/<regionX>/<dfl-port.m>/
388 /sys/class/fpga_region/<regionX>/<dfl-fme.n>/dev
389 /sys/class/fpga_region/<regionX>/<dfl-port.n>/dev
395 supports several independent, system-wide, device counter sets in hardware to
398 FPGA cache hit/miss rate, transaction number, interface clock counter of AFU
399 and other FPGA performance events.
401 Different FPGA devices may have different counter sets, depending on hardware
402 implementation. E.g., some discrete FPGA cards don't have any cache. User could
413 category; "portid" is introduced to decide counters set to monitor on FPGA
431 $# perf stat -a -e dfl_fme0/fab_mmio_read/ <command>
433 $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0xff/ <command>
435 $# perf stat -a -e dfl_fme0/config=0xff2006/ <command>
443 $# perf stat -a -e dfl_fme0/fab_port_mmio_read,portid=0x0/ <command>
445 $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0x0/ <command>
447 $# perf stat -a -e dfl_fme0/config=0x2006/ <command>
454 $# perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,\
466 since they are system-wide counters on FPGA device.
476 an eventfd based interrupt handling mechanism for users to get notified when
501 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)