Lines Matching +full:tlb +full:- +full:split
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
8 * VALID marks a TLB entry exists and it will only happen if PRESENT
9 * - Utilise some unused free bits to confine PTE flags to 12 bits
10 * This is a must for 4k pg-sz
12 * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods
13 * -TLB Locking never really existed, except for initial specs
14 * -SILENT_xxx not needed for our port
15 * -Per my request, MMU V3 changes the layout of some of the bits
16 * to avoid a few shifts in TLB Miss handlers.
19 * -PGD entry no longer contains any flags. If empty it is 0, otherwise has
20 * Pg-Tbl ptr. Thus pmd_present(), pmd_valid(), pmd_set( ) become simpler
23 * -Switched form 8:11:13 split for page table lookup to 11:8:13
24 * -this speeds up page table allocation itself as we now have to memset 1K
26 * -TODO: Right now page table alloc is 8K and rest 7K is unused
36 #include <asm-generic/pgtable-nopmd.h>
43 * ARC700 MMU only deals with softare managed TLB entries.
45 * suited to that (uniqueness). Hence some are not implemented in the TLB and
46 * some have different value in TLB.
51 * (saves some bit shift ops in TLB Miss hdlrs)
64 #define _PAGE_PRESENT (1<<10) /* TLB entry is valid (H) */
77 #define _PAGE_WTHRU (1<<7) /* Page cache mode write-thru (H) */
81 #define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */
88 usable for shared TLB entries (H) */
123 * user vaddr space - visible in all addr spaces, but kernel mode only
124 * Thus Global, all-kernel-access, no-user-access, cached
131 /* Masks for actual TLB "PD"s */
149 * -Write implies Read: W => R
150 * -Execute implies Read: X => R
152 * 2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
158 #define __P010 PAGE_U_R /* Pvt-W => !W */
159 #define __P011 PAGE_U_R /* Pvt-W => !W */
162 #define __P110 PAGE_U_X_R /* Pvt-W => !W and X => R */
163 #define __P111 PAGE_U_X_R /* Pvt-W => !W */
178 * -------------------------------------------------------
179 * | | <------------ PGDIR_SHIFT ----------> |
181 * | BITS_FOR_PGD | BITS_FOR_PTE | <-- PAGE_SHIFT --> |
182 * -------------------------------------------------------
184 * | | --> off in page frame
185 * | ---> index into Page Table
186 * ----> index into Page Directory
191 * - PGDIR_SHIFT 21 -> 11:8:13 address split
192 * - PGDIR_SHIFT 24 -> 8:11:13 address split
210 #define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT)
211 #define BITS_FOR_PGD (32 - PGDIR_SHIFT)
214 #define PGDIR_MASK (~(PGDIR_SIZE-1))
320 * Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply
343 * We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that