Lines Matching +full:10 +full:base +full:- +full:te
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
14 AR_CLASS( .arch armv7-a )
15 M_CLASS( .arch armv7-m )
63 mov \rb, #0x80000000 @ physical base address
99 kputc #'-'
103 kputc #'-'
108 kputc #'-'
152 * in little-endian form.
171 sub ip, r2, ip, ror #2 @ be superseded by kaslr-seed
245 * Booting from Angel - need to enter SVC mode and disable
262 * be needed here - is there an Angel SWI call for this?
280 * different platforms - we have chosen 128MB to allow
300 * That means r4 < pc || r4 - 16k page directory > &_end.
379 /* preserve 64-bit alignment */
435 /* preserve 64-bit alignment */
451 stmfd sp!, {r0-r3, ip, lr}
481 * Get some pseudo-entropy from the low bits of the generic
489 mov r1, r4 @ pass base address
495 addne r4, r4, r0 @ add offset to base address
504 ldmfd sp!, {r0-r3, ip, lr}
515 * r4 - 16k page directory >= r10 -> OK
516 * r4 + image length <= address of wont_overwrite -> OK
535 * Bump to the next 256-byte boundary with the size of
539 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
546 /* Relocate the hyp vector base if necessary */
585 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
587 stmdb r9!, {r0 - r3, r10 - r12, lr}
725 .size LC0, . - LC0
728 LC1: .word .L_user_stack_end - LC1 @ sp
729 .word _edata - LC1 @ r6
730 .size LC1, . - LC1
733 .word _end - restart + 16384 + 1024*1024
736 .long (input_data_end - 4) - .
747 * dcache_line_size - get the minimum D-cache line size from the CTR register
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
800 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
801 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
805 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
806 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
815 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
816 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
825 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
865 orr r1, r1, #3 << 10 @ AP=11
870 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
883 orr r1, r1, #3 << 10
922 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
924 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
946 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
952 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
956 bic r6, r6, #1 << 31 @ 32-bit translation system
978 orr r0, r0, #0x1000 @ I-cache enable
989 mov r1, #-1
1020 * On v7-M the processor id is located in the V7M_SCB_CPUID
1022 * v7-M (if existant at all) we just return early here.
1025 * use cp15 registers that are not implemented on v7-M.
1043 * - CPU ID match
1044 * - CPU ID mask
1045 * - 'cache on' method instruction
1046 * - 'cache off' method instruction
1047 * - 'cache flush' method instruction
1095 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1198 .size proc_types, . - proc_types
1201 * If you get a "non-constant expression in ".if" statement"
1206 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1229 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1230 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1371 mov r2, r2, lsl r1 @ base dcache size *2
1410 .size phexbuf, . - phexbuf
1421 cmp r2, #10
1512 * Minimal implementation of CRC-16 that does not use a
1513 * lookup table and uses 32-bit wide loads, so it still
1514 * performs reasonably well with the D-cache off. Equivalent
1519 ldr r3, =0xa001 @ CRC-16 polynomial
1553 mov r4, r0 @ preserve image base
1564 @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1567 @ U-Boot might decide to enter the EFI stub in HYP mode
1587 ARM( bic r1, r1, #(1 << 30) ) @ clear HSCTLR.TE
1588 THUMB( orr r1, r1, #(1 << 30) ) @ set HSCTLR.TE
1591 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1600 1: mov r9, r4 @ preserve image base
1604 orr r4, r9, #1 @ restore image base and set LSB
1625 0: .long .L_user_stack_end - .