Lines Matching +full:0 +full:x00000031
19 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 bic r0, r0, #0x00001000 @ i-cache
45 bic r0, r0, #0x00000004 @ d-cache
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 mov ip, #0
57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
60 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
61 bic ip, ip, #0x00000005 @ .............c.p
62 bic ip, ip, #0x00001000 @ i-cache
63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
82 mov r0, #0
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
100 mov ip, #0
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
109 bcs 2b @ entries n to 0
111 bcs 1b @ segments 3 to 0
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
115 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
130 mov ip, #0
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
154 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
183 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
188 mcr p15, 0, r0, c7, c10, 4 @ drain WB
189 mov r0, #0
204 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
208 mov r0, #0
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c10, 4 @ drain WB
228 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
230 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
233 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
237 mcr p15, 0, r0, c7, c10, 4 @ drain WB
253 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
277 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
317 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
322 mcr p15, 0, r0, c7, c10, 4 @ drain WB
327 mov r0, #0
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
329 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
330 mcr p15, 0, r0, c7, c10, 4 @ drain WB
332 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
333 mcr p15, 0, r0, c6, c4, 0
334 mcr p15, 0, r0, c6, c5, 0
335 mcr p15, 0, r0, c6, c6, 0
336 mcr p15, 0, r0, c6, c7, 0
338 mov r0, #0x0000003F @ base = 0, size = 4GB
339 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
341 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
344 mcr p15, 0, r3, c6, c1, 0
346 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
349 mcr p15, 0, r3, c6, c2, 0
351 mov r0, #0x06
352 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
353 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
355 mov r0, #0x00 @ disable whole write buffer
357 mov r0, #0x02 @ region 1 write bufferred
359 mcr p15, 0, r0, c3, c0, 0
365 * region 0 (whole) rw -- : b0001
370 mov r0, #0x00000031
371 orr r0, r0, #0x00000200
372 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
373 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
375 mrc p15, 0, r0, c1, c0 @ get control register
376 orr r0, r0, #0x00001000 @ I-cache
377 orr r0, r0, #0x00000005 @ MPU/D-cache
379 orr r0, r0, #0x00004000 @ .1.. .... .... ....
401 .long 0x41009460
402 .long 0xff00fff0
403 .long 0
404 .long 0
411 .long 0
412 .long 0