Lines Matching full:tlb
3 * linux/arch/arm/mm/tlb-v6.S
7 * ARM architecture version 6 TLB handling functions.
8 * These assume a split I/D TLB.
23 * Invalidate a range of TLB entries in the specified address space.
46 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
48 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
50 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
61 * Invalidate a range of kernel TLB entries
75 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
76 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
78 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA