Lines Matching +full:12 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
29 #define CRn_shift 12
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
232 #define SYS_PAR_EL1_F BIT(0)
246 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
342 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
343 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
345 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
346 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
347 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
348 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
349 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
354 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
359 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
360 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
361 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
362 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
363 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
364 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
365 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
366 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
367 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
368 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
369 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
370 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
371 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
393 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
394 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
395 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
396 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
397 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
398 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
399 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
400 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
428 * n: 0-15
434 * n: 0-15
439 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
480 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
481 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
487 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
493 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
494 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
495 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
496 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
497 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
498 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
499 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
500 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
502 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
512 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
538 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
549 #define SCTLR_ELx_DSSBS (BIT(44))
550 #define SCTLR_ELx_ATA (BIT(43))
558 #define SCTLR_ELx_ITFSB (BIT(37))
559 #define SCTLR_ELx_ENIA (BIT(31))
560 #define SCTLR_ELx_ENIB (BIT(30))
561 #define SCTLR_ELx_ENDA (BIT(27))
562 #define SCTLR_ELx_EE (BIT(25))
563 #define SCTLR_ELx_IESB (BIT(21))
564 #define SCTLR_ELx_WXN (BIT(19))
565 #define SCTLR_ELx_ENDB (BIT(13))
566 #define SCTLR_ELx_I (BIT(12))
567 #define SCTLR_ELx_SA (BIT(3))
568 #define SCTLR_ELx_C (BIT(2))
569 #define SCTLR_ELx_A (BIT(1))
570 #define SCTLR_ELx_M (BIT(0))
576 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
577 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
578 (BIT(29)))
587 #define SCTLR_EL1_ATA0 (BIT(42))
595 #define SCTLR_EL1_BT1 (BIT(36))
596 #define SCTLR_EL1_BT0 (BIT(35))
597 #define SCTLR_EL1_UCI (BIT(26))
598 #define SCTLR_EL1_E0E (BIT(24))
599 #define SCTLR_EL1_SPAN (BIT(23))
600 #define SCTLR_EL1_NTWE (BIT(18))
601 #define SCTLR_EL1_NTWI (BIT(16))
602 #define SCTLR_EL1_UCT (BIT(15))
603 #define SCTLR_EL1_DZE (BIT(14))
604 #define SCTLR_EL1_UMA (BIT(9))
605 #define SCTLR_EL1_SED (BIT(8))
606 #define SCTLR_EL1_ITD (BIT(7))
607 #define SCTLR_EL1_CP15BEN (BIT(5))
608 #define SCTLR_EL1_SA0 (BIT(4))
610 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
611 (BIT(29)))
651 #define ID_AA64ISAR0_SHA2_SHIFT 12
669 #define ID_AA64ISAR1_JSCVT_SHIFT 12
718 #define ID_AA64PFR0_EL3_SHIFT 12
737 #define ID_AA64PFR1_RASFRAC_SHIFT 12
784 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
812 #define ID_AA64MMFR1_HPD_SHIFT 12
832 #define ID_AA64MMFR2_IESB_SHIFT 12
842 #define ID_AA64DFR0_BRPS_SHIFT 12
861 #define ID_ISAR4_SMC_SHIFT 12
871 #define ID_ISAR0_CMPBRANCH_SHIFT 12
878 #define ID_ISAR5_SHA2_SHIFT 12
886 #define ID_ISAR6_SB_SHIFT 12
895 #define ID_MMFR0_SHARELVL_SHIFT 12
904 #define ID_MMFR4_CNP_SHIFT 12
913 #define ID_PFR0_STATE3_SHIFT 12
921 #define ID_DFR0_COPTRC_SHIFT 12
933 #define MVFR0_FPTRAP_SHIFT 12
942 #define MVFR1_SIMDINT_SHIFT 12
951 #define ID_PFR1_VIRTUALIZATION_SHIFT 12
982 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
983 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
986 /* TCR EL1 Bit Definitions */
987 #define SYS_TCR_EL1_TCMA1 (BIT(58))
988 #define SYS_TCR_EL1_TCMA0 (BIT(57))
991 #define SYS_GCR_EL1_RRND (BIT(16))
1003 /* TFSR{,E0}_EL1 bit definitions */
1010 #define SYS_MPIDR_SAFE_VAL (BIT(31))
1014 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1034 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
1104 * set mask are set. Other bits are left as-is.