Lines Matching +full:reserved +full:- +full:cpu +full:- +full:vectors
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
29 #include <asm/asm-uaccess.h>
56 *-----------------
69 * skipped by the trampoline vectors, to trigger the cleanup.
89 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
91 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
92 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
114 * after panic() re-enables interrupts.
118 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
119 b.ne __bad_stack // no? -> bad stack pointer
138 * This macro corrupts x0-x3. It is the caller's duty to save/restore
273 /* Re-enable tag checking (TCO set on exception entry) */
283 * x20 - ICC_PMR_EL1
284 * x21 - aborted SP
285 * x22 - aborted PC
286 * x23 - aborted PSTATE
400 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
414 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
425 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
440 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
445 and x25, x25, #~(THREAD_SIZE - 1)
464 * The callee-saved regs (x19-x29) should be preserved between
466 * uses x20-x23 to store data for later use.
492 * Otherwise set res to non-0 value.
552 * Exception vectors.
557 SYM_CODE_START(vectors)
568 kernel_ventry 0, sync // Synchronous 64-bit EL0
569 kernel_ventry 0, irq // IRQ 64-bit EL0
570 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
571 kernel_ventry 0, error // Error 64-bit EL0
574 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
575 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
576 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
577 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
579 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
580 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
581 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
582 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
584 SYM_CODE_END(vectors)
773 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
790 /* 2MB boundary containing the vectors, so we nobble the walk cache */
791 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
856 * enter the full-fat kernel vectors.
863 tramp_data_read_var x30, vectors
865 prfm plil1strm, [x30, #(1b - \vector_start)]
871 ldr x30, =vectors
883 add x30, x30, #(1b - \vector_start + 4)
918 * Exception vectors trampoline.
948 .quad vectors
961 * Exception vectors for spectre mitigations on entry from EL1 when
998 * Register switch for AArch64. The callee-saved registers need to be saved
1009 stp x19, x20, [x8], #16 // store callee-saved registers
1017 ldp x19, x20, [x8], #16 // restore callee-saved registers
1081 * Use reg->interrupted_regs.addr_limit to remember whether to unmap
1120 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1121 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1152 * stack for this CPU.
1173 * We may have interrupted userspace, or a guest, or exit-from or
1174 * return-to either of these. We can't trust sp_el0, restore it.
1187 stp x29, x4, [sp, #-16]!