Lines Matching +full:mips +full:- +full:cpc
1 # SPDX-License-Identifier: GPL-2.0
2 config MIPS config
125 bool "Generic board-agnostic MIPS kernel"
212 Support for the Texas Instruments AR7 System-on-a-Chip
283 Build a generic DT-based kernel image that boots on select
284 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
376 This enables support for DEC's MIPS based workstations. For details
377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
378 DECstation porting pages on <http://decstation.unix-ag.org/>.
414 This a family of machines based on the MIPS R4030 chipset which was
416 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
417 Olivetti M700-10 workstations.
453 bool "Loongson 32-bit family of machines"
456 This enables support for the Loongson-1 family of machines.
458 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
463 bool "Loongson-2E/F family of machines"
466 This enables the support of early Loongson-2E/F family of machines.
469 bool "Loongson 64-bit family of machines"
504 This enables the support of Loongson-2/3 family of machines.
506 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
507 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
508 and Loongson-2F which will be removed), developed by the Institute
541 bool "MIPS Malta board"
595 This enables support for the MIPS Technologies Malta evaluation
603 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
790 bool "Sibyte BCM91120C-CRhine"
799 bool "Sibyte BCM91120x-Carmel"
808 bool "Sibyte BCM91125C-CRhone"
818 bool "Sibyte BCM91125E-Rhone"
827 bool "Sibyte BCM91250A-SWARM"
840 bool "Sibyte BCM91250C2-LittleSur"
852 bool "Sibyte BCM91250E-Sentosa"
862 bool "Sibyte BCM91480B-BigSur"
911 The SNI RM200/300/400 are MIPS-based machines manufactured by
1040 source "arch/mips/alchemy/Kconfig"
1041 source "arch/mips/ath25/Kconfig"
1042 source "arch/mips/ath79/Kconfig"
1043 source "arch/mips/bcm47xx/Kconfig"
1044 source "arch/mips/bcm63xx/Kconfig"
1045 source "arch/mips/bmips/Kconfig"
1046 source "arch/mips/generic/Kconfig"
1047 source "arch/mips/ingenic/Kconfig"
1048 source "arch/mips/jazz/Kconfig"
1049 source "arch/mips/lantiq/Kconfig"
1050 source "arch/mips/pic32/Kconfig"
1051 source "arch/mips/pistachio/Kconfig"
1052 source "arch/mips/ralink/Kconfig"
1053 source "arch/mips/sgi-ip27/Kconfig"
1054 source "arch/mips/sibyte/Kconfig"
1055 source "arch/mips/txx9/Kconfig"
1056 source "arch/mips/vr41xx/Kconfig"
1057 source "arch/mips/cavium-octeon/Kconfig"
1058 source "arch/mips/loongson2ef/Kconfig"
1059 source "arch/mips/loongson32/Kconfig"
1060 source "arch/mips/loongson64/Kconfig"
1061 source "arch/mips/netlogic/Kconfig"
1146 # MIPS allows mixing "slightly different" Cacheability and Coherency
1225 Some MIPS machines can be configured for either little or big endian
1367 bool "Loongson 64-bit CPU"
1390 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1392 Loongson-2E/2F is not covered here and will be removed in future.
1395 bool "New Loongson-3 CPU Enhancements"
1399 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1400 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1401 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1402 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1407 please say 'N' here. If you want a high-performance kernel to run on
1408 new Loongson-3 machines only, please say 'Y' here.
1411 bool "Old Loongson-3 LLSC Workarounds"
1415 Loongson-3 processors have the llsc issues which require workarounds.
1418 Newer Loongson-3 will fix these issues and no workarounds are needed.
1430 Loongson-3A R4 and newer have the CPUCFG instruction available for
1433 cores, back to Loongson-3A1000.
1442 The Loongson 2E processor implements the MIPS III instruction set
1454 The Loongson 2F processor implements the MIPS III instruction set
1457 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1467 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1477 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1489 MIPS32 architecture. Most modern embedded systems with a 32-bit
1490 MIPS processor are based on a MIPS32 processor. If you know the
1508 MIPS32 architecture. Most modern embedded systems with a 32-bit
1509 MIPS processor are based on a MIPS32 processor. If you know the
1524 MIPS32 architecture. New MIPS processors, starting with the Warrior
1540 MIPS32 architecture. New MIPS processors, starting with the Warrior
1554 MIPS64 architecture. Many modern embedded systems with a 64-bit
1555 MIPS processor are based on a MIPS64 processor. If you know the
1575 MIPS64 architecture. Many modern embedded systems with a 64-bit
1576 MIPS processor are based on a MIPS64 processor. If you know the
1593 MIPS64 architecture. This is a intermediate MIPS architecture
1611 MIPS64 architecture. New MIPS processors, starting with the Warrior
1616 bool "MIPS Warrior P5600"
1628 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1630 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1632 cache, IOCU/IOMMU (though might be unused depending on the system-
1633 specific IP core configuration), GIC, CPC, virtualisation module,
1644 Please make sure to pick the right CPU type. Linux/MIPS is not
1675 MIPS Technologies R4000-series processors other than 4300, including
1693 MIPS Technologies R5000-series processors other than the Nevada.
1702 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1712 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1723 MIPS Technologies R10000-series processors.
1854 64-bit addressing which in turn makes the PTEs 64-bit in size.
1873 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
2061 # CPU may reorder R->R, R->W, W->R, W->W
2069 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2168 actually benefits from 64-bit processing or if your machine has
2170 menu if your system does not support both 32-bit and 64-bit kernels.
2173 bool "32-bit kernel"
2177 Select this option if you want to build a 32-bit kernel.
2180 bool "64-bit kernel"
2183 Select this option if you want to build a 64-bit kernel.
2200 Set this to non-zero if building a guest kernel for KVM to skip RTC
2226 R3000-family processors this is the only available page size. Using
2246 all non-R3000 family processors. Note that you will need a suitable
2265 all non-R3000 family processor. Not that at the time of this
2302 # Support for a MIPS32 / MIPS64 style S-caches
2364 bool "MIPS MT SMP support (1 TC on each available VPE)"
2381 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2392 when dealing with MIPS MT enabled cores at a cost of slightly
2402 bool "Dynamic FPU affinity for FP-intensive threads"
2407 bool "MIPS R2-to-R6 emulator"
2412 Choose this option if you want to run non-R6 MIPS userland code.
2415 The only reason this is a build-time option is to save ~14K from the
2470 bool "MIPS CMP framework support (DEPRECATED)"
2486 bool "MIPS Coherent Processing System support"
2498 within a MIPS Coherent Processing System. When this option is
2540 this option will not work on a MIPS core without SmartMIPS core. If
2554 bool "Support for the MIPS SIMD Architecture"
2559 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2611 # CPU non-features
2646 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2698 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2700 # I-cache line worth of instructions being fetched may case spurious
2706 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2715 # - Highmem only makes sense for the 32-bit kernel.
2716 # - The current highmem code will only work properly on physically indexed
2723 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2746 This option must be set if a kernel might be executed on a MIPS16-
2748 words, it makes the kernel MIPS16-tolerant.
2765 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2838 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2839 EVA or 64-bit. The default is 16Mb.
2866 bool "Multi-Processing support"
2873 If you say N here, the kernel will run on uni- and multiprocessor
2882 See also the SMP-HOWTO available at
2888 bool "Support for hot-pluggable CPUs"
2925 int "Maximum number of CPUs (2-256)"
2935 kernel will support. The maximum supported value is 32 for 32-bit
2936 kernel and 64 for 64-bit kernels; the minimum value which makes
2940 This is purely to save memory - each supported CPU adds
3064 which are loaded in the main kernel with kexec-tools into
3079 passed to the panic-ed kernel).
3082 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
3085 When this is enabled, the kernel will support use of 64-bit floating
3087 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
3088 32-bit MIPS systems this support is at the cost of increasing the
3091 will require 64-bit floating point, you may wish to reduce the size
3133 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3222 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
3227 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3229 <http://www.linux-mips.org/wiki/DECstation>
3284 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3298 64-bit binaries using 32-bit quantities for addressing and certain
3299 data that would normally be 64-bit. They are used in special
3338 source "arch/mips/kvm/Kconfig"
3340 source "arch/mips/vdso/Kconfig"