15  * specific PCI code and MIPS common PCI code.	Should potentially put
26  * Each pci channel is a top-level PCI bus seem by CPU.	 A machine  with
32 	struct pci_bus *bus;  member
50 	/* Optional access methods for reading/writing the bus number
66 /* Do platform specific device initialization at pci_enable_device() time */
90 	hose->need_domain_info = need_domain_info;  in set_pci_need_domain_info()
97    already-configured bus numbers - to be used for buggy BIOSes
124 static inline int pci_proc_domain(struct pci_bus *bus)  in pci_proc_domain()  argument
126 	return pci_domain_nr(bus);  in pci_proc_domain()
129 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index  argument
131 static inline int pci_proc_domain(struct pci_bus *bus)  in pci_proc_domain()  argument
133 	struct pci_controller *hose = bus->sysdata;  in pci_proc_domain()
134 	return hose->need_domain_info;  in pci_proc_domain()
140 /* Do platform specific device initialization at pci_enable_device() time */
143 /* Chances are this interrupt is wired PC-style ...  */