Lines Matching +full:1 +full:c
39 * MMCR1[25] = pmc1combine[1]
41 * MMCR1[27] = pmc2combine[1]
43 * MMCR1[29] = pmc3combine[1]
45 * MMCR1[31] = pmc4combine[1]
61 * MMCR1[17] = cache_sel[1]
65 * MMCRA[63] = 1 (SAMPLE_ENABLE)
72 * MMCRA[SDAR_MODE] = sdar_mode[0:1]
240 return -1; in power10_bhrb_filter_map()
253 return -1; in power10_bhrb_filter_map()
261 return -1; in power10_bhrb_filter_map()
272 #define C(x) PERF_COUNT_HW_CACHE_##x macro
276 * 0 means not supported, -1 means nonsensical, other values
279 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
280 [C(L1D)] = {
281 [C(OP_READ)] = {
282 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
283 [C(RESULT_MISS)] = PM_LD_MISS_L1,
285 [C(OP_WRITE)] = {
286 [C(RESULT_ACCESS)] = 0,
287 [C(RESULT_MISS)] = PM_ST_MISS_L1,
289 [C(OP_PREFETCH)] = {
290 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
291 [C(RESULT_MISS)] = 0,
294 [C(L1I)] = {
295 [C(OP_READ)] = {
296 [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
297 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
299 [C(OP_WRITE)] = {
300 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
301 [C(RESULT_MISS)] = -1,
303 [C(OP_PREFETCH)] = {
304 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
305 [C(RESULT_MISS)] = 0,
308 [C(LL)] = {
309 [C(OP_READ)] = {
310 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
311 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
313 [C(OP_WRITE)] = {
314 [C(RESULT_ACCESS)] = -1,
315 [C(RESULT_MISS)] = -1,
317 [C(OP_PREFETCH)] = {
318 [C(RESULT_ACCESS)] = -1,
319 [C(RESULT_MISS)] = 0,
322 [C(DTLB)] = {
323 [C(OP_READ)] = {
324 [C(RESULT_ACCESS)] = 0,
325 [C(RESULT_MISS)] = PM_DTLB_MISS,
327 [C(OP_WRITE)] = {
328 [C(RESULT_ACCESS)] = -1,
329 [C(RESULT_MISS)] = -1,
331 [C(OP_PREFETCH)] = {
332 [C(RESULT_ACCESS)] = -1,
333 [C(RESULT_MISS)] = -1,
336 [C(ITLB)] = {
337 [C(OP_READ)] = {
338 [C(RESULT_ACCESS)] = 0,
339 [C(RESULT_MISS)] = PM_ITLB_MISS,
341 [C(OP_WRITE)] = {
342 [C(RESULT_ACCESS)] = -1,
343 [C(RESULT_MISS)] = -1,
345 [C(OP_PREFETCH)] = {
346 [C(RESULT_ACCESS)] = -1,
347 [C(RESULT_MISS)] = -1,
350 [C(BPU)] = {
351 [C(OP_READ)] = {
352 [C(RESULT_ACCESS)] = PM_BR_CMPL,
353 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
355 [C(OP_WRITE)] = {
356 [C(RESULT_ACCESS)] = -1,
357 [C(RESULT_MISS)] = -1,
359 [C(OP_PREFETCH)] = {
360 [C(RESULT_ACCESS)] = -1,
361 [C(RESULT_MISS)] = -1,
364 [C(NODE)] = {
365 [C(OP_READ)] = {
366 [C(RESULT_ACCESS)] = -1,
367 [C(RESULT_MISS)] = -1,
369 [C(OP_WRITE)] = {
370 [C(RESULT_ACCESS)] = -1,
371 [C(RESULT_MISS)] = -1,
373 [C(OP_PREFETCH)] = {
374 [C(RESULT_ACCESS)] = -1,
375 [C(RESULT_MISS)] = -1,
380 #undef C