Lines Matching +full:d +full:- +full:cache +full:- +full:sets

2  * arch/sh/mm/cache-sh7705.c
20 #include <asm/cache.h>
27  * The 32KB cache on the SH7705 suffers from the same synonym problem
35 	waysize = current_cpu_data.dcache.sets;  in cache_wback_all()
57 	} while (--ways);  in cache_wback_all()
61  * Write back the range of D-cache, and purge the I-cache.
70 	start = data->addr1;  in sh7705_flush_icache_range()
71 	end = data->addr2;  in sh7705_flush_icache_range()
73 	__flush_wback_region((void *)start, end - start);  in sh7705_flush_icache_range()
77  * Writeback&Invalidate the D-cache of the page
88 	 * tags in the cache for those with the same page number as this page  in __flush_dcache_page()
89 	 * (by masking off the lowest 2 bits of the 19-bit tag; these bits are  in __flush_dcache_page()
93 	 * Since 2 bits of the cache index are derived from the virtual page  in __flush_dcache_page()
94 	 * number, knowing this would reduce the number of cache entries to be  in __flush_dcache_page()
96 	 * potential cache aliasing, therefore the optimisation is probably not  in __flush_dcache_page()
103 	waysize = current_cpu_data.dcache.sets;  in __flush_dcache_page()
124 	} while (--ways);  in __flush_dcache_page()
131  * Write back & invalidate the D-cache of the page.
140 		clear_bit(PG_dcache_clean, &page->flags);  in sh7705_flush_dcache_page()
158  * Write back and invalidate I/D-caches for the page.
165 	unsigned long pfn = data->addr2;  in sh7705_flush_cache_page()
171  * This is called when a page-cache page is about to be mapped into a
173  * port to ensure d-cache/i-cache coherency if necessary.
175  * Not entirely sure why this is necessary on SH3 with 32K cache but