1 // SPDX-License-Identifier: GPL-2.0-only
20 #define DRV_NAME		"ahci-mtk"
47 	struct mtk_ahci_plat *plat = hpriv->plat_data;  in mtk_ahci_platform_resets()
50 	/* reset AXI bus and PHY part */  in mtk_ahci_platform_resets()
51 	plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");  in mtk_ahci_platform_resets()
52 	if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER)  in mtk_ahci_platform_resets()
53 		return PTR_ERR(plat->axi_rst);  in mtk_ahci_platform_resets()
55 	plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");  in mtk_ahci_platform_resets()
56 	if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER)  in mtk_ahci_platform_resets()
57 		return PTR_ERR(plat->sw_rst);  in mtk_ahci_platform_resets()
59 	plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");  in mtk_ahci_platform_resets()
60 	if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER)  in mtk_ahci_platform_resets()
61 		return PTR_ERR(plat->reg_rst);  in mtk_ahci_platform_resets()
63 	err = reset_control_assert(plat->axi_rst);  in mtk_ahci_platform_resets()
65 		dev_err(dev, "failed to assert AXI bus\n");  in mtk_ahci_platform_resets()
69 	err = reset_control_assert(plat->sw_rst);  in mtk_ahci_platform_resets()
75 	err = reset_control_assert(plat->reg_rst);  in mtk_ahci_platform_resets()
81 	err = reset_control_deassert(plat->reg_rst);  in mtk_ahci_platform_resets()
87 	err = reset_control_deassert(plat->sw_rst);  in mtk_ahci_platform_resets()
93 	err = reset_control_deassert(plat->axi_rst);  in mtk_ahci_platform_resets()
95 		dev_err(dev, "failed to deassert AXI bus\n");  in mtk_ahci_platform_resets()
105 	struct mtk_ahci_plat *plat = hpriv->plat_data;  in mtk_ahci_parse_property()
106 	struct device_node *np = dev->of_node;  in mtk_ahci_parse_property()
109 	if (of_find_property(np, "mediatek,phy-mode", NULL)) {  in mtk_ahci_parse_property()
110 		plat->mode = syscon_regmap_lookup_by_phandle(  in mtk_ahci_parse_property()
111 					np, "mediatek,phy-mode");  in mtk_ahci_parse_property()
112 		if (IS_ERR(plat->mode)) {  in mtk_ahci_parse_property()
113 			dev_err(dev, "missing phy-mode phandle\n");  in mtk_ahci_parse_property()
114 			return PTR_ERR(plat->mode);  in mtk_ahci_parse_property()
117 		regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,  in mtk_ahci_parse_property()
121 	of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);  in mtk_ahci_parse_property()
128 	struct device *dev = &pdev->dev;  in mtk_ahci_probe()
135 		return -ENOMEM;  in mtk_ahci_probe()
141 	hpriv->plat_data = plat;  in mtk_ahci_probe()
171 	{ .compatible = "mediatek,mtk-ahci", },