Lines Matching +full:clock +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0+
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
27 #include <linux/clk-provider.h>
37 #include <dt-bindings/clock/bcm2835.h>
44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
252 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
300 * with an external parent's name. This array is in the order that
320 * Real names of cprman clock parents looked up through
322 * parent_names[] arrays for clock registration.
336 writel(CM_PASSWORD | val, cprman->regs + reg); in cprman_write()
341 return readl(cprman->regs + reg); in cprman_read()
344 /* Does a cycle of measuring a clock through the TCNT clock, which may
354 spin_lock(&cprman->regs_lock); in bcm2835_measure_tcnt_mux()
371 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); in bcm2835_measure_tcnt_mux()
382 dev_err(cprman->dev, "timeout waiting for !BUSY\n"); in bcm2835_measure_tcnt_mux()
394 spin_unlock(&cprman->regs_lock); in bcm2835_measure_tcnt_mux()
405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); in bcm2835_debugfs_regset()
409 regset->regs = regs; in bcm2835_debugfs_regset()
410 regset->nregs = nregs; in bcm2835_debugfs_regset()
411 regset->base = cprman->regs + base; in bcm2835_debugfs_regset()
417 const char *name; member
433 * pre-divide-by-2.
469 const char *name; member
482 const char *name; member
508 const char *name; member
523 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_is_on()
524 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_is_on()
526 return cprman_read(cprman, data->a2w_ctrl_reg) & in bcm2835_pll_is_on()
534 * On BCM2711 there isn't a pre-divisor available in the PLL feedback in bcm2835_pll_get_prediv_mask()
535 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed in bcm2835_pll_get_prediv_mask()
538 if (cprman->soc & SOC_BCM2711) in bcm2835_pll_get_prediv_mask()
541 return data->ana->fb_prediv_mask; in bcm2835_pll_get_prediv_mask()
554 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); in bcm2835_pll_choose_ndiv_and_fdiv()
574 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_round_rate()
577 rate = clamp(rate, data->min_rate, data->max_rate); in bcm2835_pll_round_rate()
588 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_get_rate()
589 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_get_rate()
590 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); in bcm2835_pll_get_rate()
597 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; in bcm2835_pll_get_rate()
600 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & in bcm2835_pll_get_rate()
614 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_off()
615 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_off()
617 spin_lock(&cprman->regs_lock); in bcm2835_pll_off()
618 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); in bcm2835_pll_off()
619 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_off()
620 cprman_read(cprman, data->a2w_ctrl_reg) | in bcm2835_pll_off()
622 spin_unlock(&cprman->regs_lock); in bcm2835_pll_off()
628 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_on()
629 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_on()
632 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_on()
633 cprman_read(cprman, data->a2w_ctrl_reg) & in bcm2835_pll_on()
637 spin_lock(&cprman->regs_lock); in bcm2835_pll_on()
638 cprman_write(cprman, data->cm_ctrl_reg, in bcm2835_pll_on()
639 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); in bcm2835_pll_on()
640 spin_unlock(&cprman->regs_lock); in bcm2835_pll_on()
644 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { in bcm2835_pll_on()
646 dev_err(cprman->dev, "%s: couldn't lock PLL\n", in bcm2835_pll_on()
648 return -ETIMEDOUT; in bcm2835_pll_on()
654 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_on()
655 cprman_read(cprman, data->a2w_ctrl_reg) | in bcm2835_pll_on()
668 * ANA3-ANA0, in that order. This lets us write all 4 in bcm2835_pll_write_ana()
671 * 3 individually through their partial-write registers, each in bcm2835_pll_write_ana()
674 for (i = 3; i >= 0; i--) in bcm2835_pll_write_ana()
682 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_set_rate()
683 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_set_rate()
690 if (rate > data->max_fb_rate) { in bcm2835_pll_set_rate()
699 for (i = 3; i >= 0; i--) in bcm2835_pll_set_rate()
700 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); in bcm2835_pll_set_rate()
704 ana[0] &= ~data->ana->mask0; in bcm2835_pll_set_rate()
705 ana[0] |= data->ana->set0; in bcm2835_pll_set_rate()
706 ana[1] &= ~data->ana->mask1; in bcm2835_pll_set_rate()
707 ana[1] |= data->ana->set1; in bcm2835_pll_set_rate()
708 ana[3] &= ~data->ana->mask3; in bcm2835_pll_set_rate()
709 ana[3] |= data->ana->set3; in bcm2835_pll_set_rate()
721 /* Unmask the reference clock from the oscillator. */ in bcm2835_pll_set_rate()
722 spin_lock(&cprman->regs_lock); in bcm2835_pll_set_rate()
725 data->reference_enable_mask); in bcm2835_pll_set_rate()
726 spin_unlock(&cprman->regs_lock); in bcm2835_pll_set_rate()
729 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); in bcm2835_pll_set_rate()
732 cprman_write(cprman, data->frac_reg, fdiv); in bcm2835_pll_set_rate()
734 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); in bcm2835_pll_set_rate()
739 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); in bcm2835_pll_set_rate()
742 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); in bcm2835_pll_set_rate()
751 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_debug_init()
752 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_debug_init()
755 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); in bcm2835_pll_debug_init()
759 regs[0].name = "cm_ctrl"; in bcm2835_pll_debug_init()
760 regs[0].offset = data->cm_ctrl_reg; in bcm2835_pll_debug_init()
761 regs[1].name = "a2w_ctrl"; in bcm2835_pll_debug_init()
762 regs[1].offset = data->a2w_ctrl_reg; in bcm2835_pll_debug_init()
763 regs[2].name = "frac"; in bcm2835_pll_debug_init()
764 regs[2].offset = data->frac_reg; in bcm2835_pll_debug_init()
765 regs[3].name = "ana0"; in bcm2835_pll_debug_init()
766 regs[3].offset = data->ana_reg_base + 0 * 4; in bcm2835_pll_debug_init()
767 regs[4].name = "ana1"; in bcm2835_pll_debug_init()
768 regs[4].offset = data->ana_reg_base + 1 * 4; in bcm2835_pll_debug_init()
769 regs[5].name = "ana2"; in bcm2835_pll_debug_init()
770 regs[5].offset = data->ana_reg_base + 2 * 4; in bcm2835_pll_debug_init()
771 regs[6].name = "ana3"; in bcm2835_pll_debug_init()
772 regs[6].offset = data->ana_reg_base + 3 * 4; in bcm2835_pll_debug_init()
802 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_is_on()
803 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_is_on()
805 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); in bcm2835_pll_divider_is_on()
824 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_off()
825 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_off()
827 spin_lock(&cprman->regs_lock); in bcm2835_pll_divider_off()
828 cprman_write(cprman, data->cm_reg, in bcm2835_pll_divider_off()
829 (cprman_read(cprman, data->cm_reg) & in bcm2835_pll_divider_off()
830 ~data->load_mask) | data->hold_mask); in bcm2835_pll_divider_off()
831 cprman_write(cprman, data->a2w_reg, in bcm2835_pll_divider_off()
832 cprman_read(cprman, data->a2w_reg) | in bcm2835_pll_divider_off()
834 spin_unlock(&cprman->regs_lock); in bcm2835_pll_divider_off()
840 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_on()
841 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_on()
843 spin_lock(&cprman->regs_lock); in bcm2835_pll_divider_on()
844 cprman_write(cprman, data->a2w_reg, in bcm2835_pll_divider_on()
845 cprman_read(cprman, data->a2w_reg) & in bcm2835_pll_divider_on()
848 cprman_write(cprman, data->cm_reg, in bcm2835_pll_divider_on()
849 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); in bcm2835_pll_divider_on()
850 spin_unlock(&cprman->regs_lock); in bcm2835_pll_divider_on()
860 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_set_rate()
861 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_set_rate()
870 cprman_write(cprman, data->a2w_reg, div); in bcm2835_pll_divider_set_rate()
871 cm = cprman_read(cprman, data->cm_reg); in bcm2835_pll_divider_set_rate()
872 cprman_write(cprman, data->cm_reg, cm | data->load_mask); in bcm2835_pll_divider_set_rate()
873 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); in bcm2835_pll_divider_set_rate()
882 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_debug_init()
883 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_debug_init()
886 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); in bcm2835_pll_divider_debug_init()
890 regs[0].name = "cm"; in bcm2835_pll_divider_debug_init()
891 regs[0].offset = data->cm_reg; in bcm2835_pll_divider_debug_init()
892 regs[1].name = "a2w"; in bcm2835_pll_divider_debug_init()
893 regs[1].offset = data->a2w_reg; in bcm2835_pll_divider_debug_init()
909 * The CM dividers do fixed-point division, so we can't use the
911 * fake it by having some fixed shifts preceding it in the clock tree,
912 * because we'd run out of bits in a 32-bit unsigned long).
927 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_is_on() local
928 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_is_on()
929 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_is_on()
931 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; in bcm2835_clock_is_on()
938 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_choose_div() local
939 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_choose_div()
941 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; in bcm2835_clock_choose_div()
950 /* different clamping limits apply for a mash clock */ in bcm2835_clock_choose_div()
951 if (data->is_mash_clock) { in bcm2835_clock_choose_div()
955 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; in bcm2835_clock_choose_div()
960 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, in bcm2835_clock_choose_div()
961 CM_DIV_FRAC_BITS - data->frac_bits); in bcm2835_clock_choose_div()
971 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, in bcm2835_clock_rate_from_divisor() argument
975 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_rate_from_divisor()
978 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_rate_from_divisor()
983 * the bits are populated in any given clock. in bcm2835_clock_rate_from_divisor()
985 div >>= CM_DIV_FRAC_BITS - data->frac_bits; in bcm2835_clock_rate_from_divisor()
986 div &= (1 << (data->int_bits + data->frac_bits)) - 1; in bcm2835_clock_rate_from_divisor()
991 temp = (u64)parent_rate << data->frac_bits; in bcm2835_clock_rate_from_divisor()
1001 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_get_rate() local
1002 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_get_rate()
1003 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_get_rate()
1006 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_get_rate()
1009 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1011 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); in bcm2835_clock_get_rate()
1014 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) in bcm2835_clock_wait_busy() argument
1016 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_wait_busy()
1017 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_wait_busy()
1020 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { in bcm2835_clock_wait_busy()
1022 dev_err(cprman->dev, "%s: couldn't lock PLL\n", in bcm2835_clock_wait_busy()
1023 clk_hw_get_name(&clock->hw)); in bcm2835_clock_wait_busy()
1032 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_off() local
1033 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_off()
1034 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_off()
1036 spin_lock(&cprman->regs_lock); in bcm2835_clock_off()
1037 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_off()
1038 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); in bcm2835_clock_off()
1039 spin_unlock(&cprman->regs_lock); in bcm2835_clock_off()
1042 bcm2835_clock_wait_busy(clock); in bcm2835_clock_off()
1047 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_on() local
1048 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_on()
1049 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_on()
1051 spin_lock(&cprman->regs_lock); in bcm2835_clock_on()
1052 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_on()
1053 cprman_read(cprman, data->ctl_reg) | in bcm2835_clock_on()
1056 spin_unlock(&cprman->regs_lock); in bcm2835_clock_on()
1058 /* Debug code to measure the clock once it's turned on to see in bcm2835_clock_on()
1061 if (data->tcnt_mux && false) { in bcm2835_clock_on()
1062 dev_info(cprman->dev, in bcm2835_clock_on()
1064 data->name, in bcm2835_clock_on()
1066 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); in bcm2835_clock_on()
1075 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_set_rate() local
1076 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_set_rate()
1077 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_set_rate()
1081 spin_lock(&cprman->regs_lock); in bcm2835_clock_set_rate()
1086 * In principle it is recommended to stop/start the clock first, in bcm2835_clock_set_rate()
1088 * clock this requirement should be take care of by the in bcm2835_clock_set_rate()
1089 * clk-framework. in bcm2835_clock_set_rate()
1091 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; in bcm2835_clock_set_rate()
1093 cprman_write(cprman, data->ctl_reg, ctl); in bcm2835_clock_set_rate()
1095 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1097 spin_unlock(&cprman->regs_lock); in bcm2835_clock_set_rate()
1118 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_choose_div_and_prate() local
1119 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_choose_div_and_prate()
1120 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_choose_div_and_prate()
1127 if (!(BIT(parent_idx) & data->set_rate_parent)) { in bcm2835_clock_choose_div_and_prate()
1131 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div); in bcm2835_clock_choose_div_and_prate()
1133 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) { in bcm2835_clock_choose_div_and_prate()
1137 high = bcm2835_clock_rate_from_divisor(clock, *prate, in bcm2835_clock_choose_div_and_prate()
1140 low = bcm2835_clock_rate_from_divisor(clock, *prate, in bcm2835_clock_choose_div_and_prate()
1147 return *avgrate - max(*avgrate - low, high - *avgrate); in bcm2835_clock_choose_div_and_prate()
1152 if (data->frac_bits) in bcm2835_clock_choose_div_and_prate()
1153 dev_warn(cprman->dev, in bcm2835_clock_choose_div_and_prate()
1156 /* clamp to min divider of 2 if we're dealing with a mash clock */ in bcm2835_clock_choose_div_and_prate()
1157 mindiv = data->is_mash_clock ? 2 : 1; in bcm2835_clock_choose_div_and_prate()
1158 maxdiv = BIT(data->int_bits) - 1; in bcm2835_clock_choose_div_and_prate()
1195 * Select parent clock that results in the closest but lower rate in bcm2835_clock_determine_rate()
1203 * Don't choose a PLLC-derived clock as our parent in bcm2835_clock_determine_rate()
1206 * over-temp or under-voltage conditions, without in bcm2835_clock_determine_rate()
1207 * prior notification to our clock consumer. in bcm2835_clock_determine_rate()
1212 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, in bcm2835_clock_determine_rate()
1215 if (abs(req->rate - rate) < abs(req->rate - best_rate)) { in bcm2835_clock_determine_rate()
1224 return -EINVAL; in bcm2835_clock_determine_rate()
1226 req->best_parent_hw = best_parent; in bcm2835_clock_determine_rate()
1227 req->best_parent_rate = best_prate; in bcm2835_clock_determine_rate()
1229 req->rate = best_avgrate; in bcm2835_clock_determine_rate()
1236 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_set_parent() local
1237 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_set_parent()
1238 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_set_parent()
1241 cprman_write(cprman, data->ctl_reg, src); in bcm2835_clock_set_parent()
1247 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_get_parent() local
1248 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_get_parent()
1249 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_get_parent()
1250 u32 src = cprman_read(cprman, data->ctl_reg); in bcm2835_clock_get_parent()
1257 .name = "ctl",
1261 .name = "div",
1269 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_debug_init() local
1270 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_debug_init()
1271 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_debug_init()
1273 bcm2835_debugfs_regset(cprman, data->ctl_reg, in bcm2835_clock_debug_init()
1297 * The VPU clock can never be disabled (it doesn't have an ENABLE
1298 * bit), so it gets its own set of clock ops.
1321 init.parent_names = &cprman->real_parent_names[0]; in bcm2835_register_pll()
1323 init.name = pll_data->name; in bcm2835_register_pll()
1325 init.flags = pll_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_pll()
1331 pll->cprman = cprman; in bcm2835_register_pll()
1332 pll->data = pll_data; in bcm2835_register_pll()
1333 pll->hw.init = &init; in bcm2835_register_pll()
1335 ret = devm_clk_hw_register(cprman->dev, &pll->hw); in bcm2835_register_pll()
1340 return &pll->hw; in bcm2835_register_pll()
1353 if (divider_data->fixed_divider != 1) { in bcm2835_register_pll_divider()
1354 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, in bcm2835_register_pll_divider()
1355 "%s_prediv", divider_data->name); in bcm2835_register_pll_divider()
1359 divider_name = divider_data->name; in bcm2835_register_pll_divider()
1364 init.parent_names = ÷r_data->source_pll; in bcm2835_register_pll_divider()
1366 init.name = divider_name; in bcm2835_register_pll_divider()
1368 init.flags = divider_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_pll_divider()
1370 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); in bcm2835_register_pll_divider()
1374 divider->div.reg = cprman->regs + divider_data->a2w_reg; in bcm2835_register_pll_divider()
1375 divider->div.shift = A2W_PLL_DIV_SHIFT; in bcm2835_register_pll_divider()
1376 divider->div.width = A2W_PLL_DIV_BITS; in bcm2835_register_pll_divider()
1377 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; in bcm2835_register_pll_divider()
1378 divider->div.lock = &cprman->regs_lock; in bcm2835_register_pll_divider()
1379 divider->div.hw.init = &init; in bcm2835_register_pll_divider()
1380 divider->div.table = NULL; in bcm2835_register_pll_divider()
1382 divider->cprman = cprman; in bcm2835_register_pll_divider()
1383 divider->data = divider_data; in bcm2835_register_pll_divider()
1385 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); in bcm2835_register_pll_divider()
1393 if (divider_data->fixed_divider != 1) { in bcm2835_register_pll_divider()
1394 return clk_hw_register_fixed_factor(cprman->dev, in bcm2835_register_pll_divider()
1395 divider_data->name, in bcm2835_register_pll_divider()
1399 divider_data->fixed_divider); in bcm2835_register_pll_divider()
1402 return ÷r->div.hw; in bcm2835_register_pll_divider()
1409 struct bcm2835_clock *clock; in bcm2835_register_clock() local
1417 * actual clock-output-name of the parent. in bcm2835_register_clock()
1419 for (i = 0; i < clock_data->num_mux_parents; i++) { in bcm2835_register_clock()
1420 parents[i] = clock_data->parents[i]; in bcm2835_register_clock()
1426 parents[i] = cprman->real_parent_names[ret]; in bcm2835_register_clock()
1431 init.num_parents = clock_data->num_mux_parents; in bcm2835_register_clock()
1432 init.name = clock_data->name; in bcm2835_register_clock()
1433 init.flags = clock_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_clock()
1439 if (clock_data->set_rate_parent) in bcm2835_register_clock()
1442 if (clock_data->is_vpu_clock) { in bcm2835_register_clock()
1448 /* If the clock wasn't actually enabled at boot, it's not in bcm2835_register_clock()
1451 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) in bcm2835_register_clock()
1455 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); in bcm2835_register_clock()
1456 if (!clock) in bcm2835_register_clock()
1459 clock->cprman = cprman; in bcm2835_register_clock()
1460 clock->data = clock_data; in bcm2835_register_clock()
1461 clock->hw.init = &init; in bcm2835_register_clock()
1463 ret = devm_clk_hw_register(cprman->dev, &clock->hw); in bcm2835_register_clock()
1466 return &clock->hw; in bcm2835_register_clock()
1474 return clk_hw_register_gate(cprman->dev, gate_data->name, in bcm2835_register_gate()
1475 gate_data->parent, in bcm2835_register_gate()
1477 cprman->regs + gate_data->ctl_reg, in bcm2835_register_gate()
1478 CM_GATE_BIT, 0, &cprman->regs_lock); in bcm2835_register_gate()
1488 /* assignment helper macros for different clock types */
1544 * Restrict clock sources for the PCM peripheral to the oscillator and
1553 "-",
1555 "-",
1556 "-",
1557 "-",
1558 "-",
1560 "-",
1641 * (Compact Camera Port 2) transmitter clock.
1648 .name = "plla",
1663 .name = "plla_core",
1673 .name = "plla_per",
1683 .name = "plla_dsi0",
1692 .name = "plla_ccp2",
1701 /* PLLB is used for the ARM's clock. */
1704 .name = "pllb",
1720 .name = "pllb_arm",
1730 * PLLC is the core PLL, used to drive the core VPU clock.
1737 .name = "pllc",
1752 .name = "pllc_core0",
1762 .name = "pllc_core1",
1772 .name = "pllc_core2",
1782 .name = "pllc_per",
1799 .name = "plld",
1814 .name = "plld_core",
1829 .name = "plld_per",
1839 .name = "plld_dsi0",
1848 .name = "plld_dsi1",
1857 * PLLH is used to supply the pixel clock or the AUX clock for the
1879 .name = "pllh_rcal",
1889 .name = "pllh_aux",
1899 .name = "pllh_pix",
1912 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1915 .name = "otp",
1922 * Used for a 1Mhz clock for the system clocksource, and also used
1927 .name = "timer",
1933 * Clock for the temperature sensor.
1938 .name = "tsens",
1945 .name = "tec",
1954 .name = "h264",
1962 .name = "isp",
1970 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1975 .name = "sdram",
1983 .name = "v3d",
1990 * VPU clock. This doesn't have an enable bit, since it drives
1997 .name = "vpu",
2009 .name = "aveo",
2017 .name = "cam0",
2025 .name = "cam1",
2033 .name = "dft",
2040 .name = "dpi",
2047 /* Arasan EMMC clock */
2050 .name = "emmc",
2057 /* EMMC2 clock (only available for BCM2711) */
2060 .name = "emmc2",
2070 .name = "gp0",
2079 .name = "gp1",
2089 .name = "gp2",
2099 .name = "hsm",
2107 .name = "pcm",
2117 .name = "pwm",
2126 .name = "slim",
2135 .name = "smi",
2143 .name = "uart",
2150 /* TV encoder clock. Only operating frequency is 108Mhz. */
2153 .name = "vec",
2168 .name = "dsi0e",
2176 .name = "dsi1e",
2184 .name = "dsi0p",
2192 .name = "dsi1p",
2205 * non-stop vpu clock.
2209 .name = "peri_image",
2215 * Permanently take a reference on the parent of the SDRAM clock.
2219 * periodically switches the SDRAM to using our CM clock to do PVT
2235 struct device *dev = &pdev->dev; in bcm2835_clk_probe()
2244 pdata = of_device_get_match_data(&pdev->dev); in bcm2835_clk_probe()
2246 return -ENODEV; in bcm2835_clk_probe()
2252 return -ENOMEM; in bcm2835_clk_probe()
2254 spin_lock_init(&cprman->regs_lock); in bcm2835_clk_probe()
2255 cprman->dev = dev; in bcm2835_clk_probe()
2256 cprman->regs = devm_platform_ioremap_resource(pdev, 0); in bcm2835_clk_probe()
2257 if (IS_ERR(cprman->regs)) in bcm2835_clk_probe()
2258 return PTR_ERR(cprman->regs); in bcm2835_clk_probe()
2260 memcpy(cprman->real_parent_names, cprman_parent_names, in bcm2835_clk_probe()
2262 of_clk_parent_fill(dev->of_node, cprman->real_parent_names, in bcm2835_clk_probe()
2272 if (!cprman->real_parent_names[0]) in bcm2835_clk_probe()
2273 return -ENODEV; in bcm2835_clk_probe()
2277 cprman->onecell.num = asize; in bcm2835_clk_probe()
2278 cprman->soc = pdata->soc; in bcm2835_clk_probe()
2279 hws = cprman->onecell.hws; in bcm2835_clk_probe()
2283 if (desc->clk_register && desc->data && in bcm2835_clk_probe()
2284 (desc->supported & pdata->soc)) { in bcm2835_clk_probe()
2285 hws[i] = desc->clk_register(cprman, desc->data); in bcm2835_clk_probe()
2289 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); in bcm2835_clk_probe()
2293 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, in bcm2835_clk_probe()
2294 &cprman->onecell); in bcm2835_clk_probe()
2306 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2307 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2314 .name = "bcm2835-clk",
2323 MODULE_DESCRIPTION("BCM2835 clock driver");