Lines Matching +full:8 +full:- +full:channel
16 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/bcm-nsp.h>
22 #include "clk-iproc.h"
43 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
58 .channel = BCM_NSP_GENPLL_PHY_CLK,
61 .mdiv = REG_VAL(0x18, 16, 8),
64 .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
67 .mdiv = REG_VAL(0x18, 8, 8),
70 .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
72 .enable = ENABLE_VAL(0x4, 14, 8, 20),
73 .mdiv = REG_VAL(0x18, 0, 8),
76 .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
79 .mdiv = REG_VAL(0x1c, 16, 8),
82 .channel = BCM_NSP_GENPLL_SATA1_CLK,
85 .mdiv = REG_VAL(0x1c, 8, 8),
88 .channel = BCM_NSP_GENPLL_SATA2_CLK,
91 .mdiv = REG_VAL(0x1c, 0, 8),
100 CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
107 .ndiv_int = REG_VAL(0x4, 20, 8),
115 .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
118 .mdiv = REG_VAL(0x8, 24, 8),
121 .channel = BCM_NSP_LCPLL0_SDIO_CLK,
124 .mdiv = REG_VAL(0x8, 16, 8),
127 .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
129 .enable = ENABLE_VAL(0x0, 8, 5, 11),
130 .mdiv = REG_VAL(0x8, 8, 8),
139 CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);