Lines Matching +full:1 +full:- +full:9

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
37 	.aon = AON_VAL(0x0, 5, 1, 0),
44 	.status = REG_VAL(0x30, 12, 1),
52 		.mdiv = REG_VAL(0x18, 0, 9),
57 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
58 		.mdiv = REG_VAL(0x18, 10, 9),
64 		.mdiv = REG_VAL(0x18, 20, 9),
69 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
70 		.mdiv = REG_VAL(0x1c, 0, 9),
76 		.mdiv = REG_VAL(0x1c, 10, 9),
82 		.mdiv = REG_VAL(0x1c, 20, 9),
88 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll0_clk_init()
97 	.aon = AON_VAL(0x0, 1, 13, 12),
104 	.status = REG_VAL(0x30, 12, 1),
112 		.mdiv = REG_VAL(0x18, 0, 9),
117 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
118 		.mdiv = REG_VAL(0x18, 10, 9),
124 		.mdiv = REG_VAL(0x18, 20, 9),
129 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
130 		.mdiv = REG_VAL(0x1c, 0, 9),
136 		.mdiv = REG_VAL(0x1c, 10, 9),
141 		.mdiv = REG_VAL(0x1c, 20, 9),
147 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll2_clk_init()
156 	.aon = AON_VAL(0x0, 1, 19, 18),
163 	.status = REG_VAL(0x30, 12, 1),
171 		.mdiv = REG_VAL(0x18, 0, 9),
176 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
177 		.mdiv = REG_VAL(0x18, 10, 9),
186 CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
191 	.aon = AON_VAL(0x0, 1, 25, 24),
198 	.status = REG_VAL(0x30, 12, 1),
206 		.mdiv = REG_VAL(0x18, 0, 9),
211 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
212 		.mdiv = REG_VAL(0x18, 10, 9),
218 		.mdiv = REG_VAL(0x18, 20, 9),
223 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
224 		.mdiv = REG_VAL(0x1c, 0, 9),
230 		.mdiv = REG_VAL(0x1c, 10, 9),
236 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll4_clk_init()
245 	.aon = AON_VAL(0x0, 1, 1, 0),
252 	.status = REG_VAL(0x30, 12, 1),
259 		.mdiv = REG_VAL(0x18, 0, 9),
263 		.enable = ENABLE_VAL(0x4, 7, 1, 12),
264 		.mdiv = REG_VAL(0x18, 10, 9),
269 		.mdiv = REG_VAL(0x18, 20, 9),
275 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll5_clk_init()
288 	.status = REG_VAL(0x38, 12, 1),
295 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
296 		.mdiv = REG_VAL(0x14, 0, 9),
302 		.mdiv = REG_VAL(0x14, 10, 9),
307 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
308 		.mdiv = REG_VAL(0x14, 20, 9),
314 		.mdiv = REG_VAL(0x18, 0, 9),
320 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll0_clk_init()
333 	.status = REG_VAL(0x38, 12, 1),
340 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
341 		.mdiv = REG_VAL(0x14, 0, 9),
347 		.mdiv = REG_VAL(0x14, 10, 9),
352 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
353 		.mdiv = REG_VAL(0x14, 20, 9),
359 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll1_clk_init()
372 	.status = REG_VAL(0x38, 12, 1),
379 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
380 		.mdiv = REG_VAL(0x14, 0, 9),
386 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll_pcie_clk_init()
393 	{ .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
394 	{ .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
395 	{ .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
396 	{ .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
397 	{ .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
398 	{ .compatible = "brcm,sr-lcpll1", .data = sr_lcpll1_clk_init },
399 	{ .compatible = "brcm,sr-lcpll-pcie", .data = sr_lcpll_pcie_clk_init },
407 	probe_func = of_device_get_match_data(&pdev->dev);  in sr_clk_probe()
409 		return -ENODEV;  in sr_clk_probe()
416 		.name = "sr-clk",