Lines Matching +full:pll +full:- +full:periph

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright 2013-2014 Freescale Semiconductor, Inc.
13 #include <dt-bindings/clock/imx6sl-clock.h>
36 static const char *ocram_sels[]		= { "periph", "ocram_alt_sels", };
118  * as there is sleep function in PLL wait function), so here we just slow
122  * 396MHz   ->   132MHz;
123  * 792MHz   ->   158.4MHz;
124  * 996MHz   ->   142.3MHz;
192 	clk_hw_data->num = IMX6SL_CLK_END;  in imx6sl_clocks_init()
193 	hws = clk_hw_data->hws;  in imx6sl_clocks_init()
201 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");  in imx6sl_clocks_init()
233 	clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk);  in imx6sl_clocks_init()
234 	clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk);  in imx6sl_clocks_init()
235 	clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk);  in imx6sl_clocks_init()
236 	clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk);  in imx6sl_clocks_init()
237 	clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk);  in imx6sl_clocks_init()
238 	clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk);  in imx6sl_clocks_init()
239 	clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk);  in imx6sl_clocks_init()
256 	 * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be  in imx6sl_clocks_init()
324 …hws[IMX6SL_CLK_PERIPH]  = imx_clk_hw_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  p…  in imx6sl_clocks_init()
363 …hws[IMX6SL_CLK_AHB]       = imx_clk_hw_busy_divider("ahb",       "periph",  base + 0x14, 10, 3,   …  in imx6sl_clocks_init()
422 	ret = clk_set_rate(hws[IMX6SL_CLK_AHB]->clk, 132000000);  in imx6sl_clocks_init()
428 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY1_GATE]->clk);  in imx6sl_clocks_init()
429 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY2_GATE]->clk);  in imx6sl_clocks_init()
432 	/* Audio-related clocks configuration */  in imx6sl_clocks_init()
433 	clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk);  in imx6sl_clocks_init()
436 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk,  in imx6sl_clocks_init()
437 			hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6sl_clocks_init()
439 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,  in imx6sl_clocks_init()
440 		       hws[IMX6SL_CLK_PLL2_PFD2]->clk);  in imx6sl_clocks_init()
444 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);