Lines Matching +full:clock +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
11 #include <linux/clk-provider.h>
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
38 * Retrieves the state of the clock gate bit described by info. The
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
55 * @val: non-zero to gate a clock, otherwise zero
57 * Sets the given gate bit in order to gate or ungate a clock.
59 * The caller must hold cgu->lock.
65 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
67 if (val ^ info->clear_to_gate) in ingenic_cgu_gate_set()
68 clkgr |= BIT(info->bit); in ingenic_cgu_gate_set()
70 clkgr &= ~BIT(info->bit); in ingenic_cgu_gate_set()
72 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate()
90 BUG_ON(clk_info->type != CGU_CLK_PLL); in ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()
96 m += pll_info->m_offset; in ingenic_pll_recalc_rate()
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()
98 n += pll_info->n_offset; in ingenic_pll_recalc_rate()
99 od_enc = ctl >> pll_info->od_shift; in ingenic_pll_recalc_rate()
100 od_enc &= GENMASK(pll_info->od_bits - 1, 0); in ingenic_pll_recalc_rate()
102 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
104 bypass = !pll_info->no_bypass_bit && in ingenic_pll_recalc_rate()
105 !!(ctl & BIT(pll_info->bypass_bit)); in ingenic_pll_recalc_rate()
110 for (od = 0; od < pll_info->od_max; od++) { in ingenic_pll_recalc_rate()
111 if (pll_info->od_encoding[od] == od_enc) in ingenic_pll_recalc_rate()
114 BUG_ON(od == pll_info->od_max); in ingenic_pll_recalc_rate()
117 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_recalc_rate()
129 pll_info = &clk_info->pll; in ingenic_pll_calc()
137 n = min_t(unsigned, n, 1 << clk_info->pll.n_bits); in ingenic_pll_calc()
138 n = max_t(unsigned, n, pll_info->n_offset); in ingenic_pll_calc()
141 m = min_t(unsigned, m, 1 << clk_info->pll.m_bits); in ingenic_pll_calc()
142 m = max_t(unsigned, m, pll_info->m_offset); in ingenic_pll_calc()
151 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_calc()
170 return readl_poll_timeout(cgu->base + pll_info->reg, ctl, in ingenic_pll_check_stable()
171 ctl & BIT(pll_info->stable_bit), in ingenic_pll_check_stable()
180 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_set_rate()
182 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate()
191 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n", in ingenic_pll_set_rate()
192 clk_info->name, req_rate, rate); in ingenic_pll_set_rate()
194 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_set_rate()
195 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_set_rate()
197 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); in ingenic_pll_set_rate()
198 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; in ingenic_pll_set_rate()
200 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); in ingenic_pll_set_rate()
201 ctl |= (n - pll_info->n_offset) << pll_info->n_shift; in ingenic_pll_set_rate()
203 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); in ingenic_pll_set_rate()
204 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; in ingenic_pll_set_rate()
206 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_set_rate()
209 if (ctl & BIT(pll_info->enable_bit)) in ingenic_pll_set_rate()
212 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_set_rate()
220 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_enable()
222 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable()
227 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_enable()
228 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
230 ctl &= ~BIT(pll_info->bypass_bit); in ingenic_pll_enable()
232 writel(ctl, cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
234 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_enable()
236 ctl |= BIT(pll_info->enable_bit); in ingenic_pll_enable()
238 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_enable()
241 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_enable()
249 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_disable()
251 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable()
255 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_disable()
256 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_disable()
258 ctl &= ~BIT(pll_info->enable_bit); in ingenic_pll_disable()
260 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_disable()
261 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_disable()
267 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_is_enabled()
269 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled()
272 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_is_enabled()
274 return !!(ctl & BIT(pll_info->enable_bit)); in ingenic_pll_is_enabled()
288 * Operations for all non-PLL clocks
295 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_get_parent()
299 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
300 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_get_parent()
301 hw_idx = (reg >> clk_info->mux.shift) & in ingenic_clk_get_parent()
302 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
306 * over any -1's in the parents array. in ingenic_clk_get_parent()
309 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
321 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_parent()
326 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
329 * 1 for any -1 in the parents array preceding the given in ingenic_clk_set_parent()
331 * clk_info->parents which does not equal -1. in ingenic_clk_set_parent()
334 num_poss = 1 << clk_info->mux.bits; in ingenic_clk_set_parent()
336 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
346 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
347 mask <<= clk_info->mux.shift; in ingenic_clk_set_parent()
349 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_parent()
352 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
354 reg |= hw_idx << clk_info->mux.shift; in ingenic_clk_set_parent()
355 writel(reg, cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
357 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_parent()
361 return idx ? -EINVAL : 0; in ingenic_clk_set_parent()
369 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_recalc_rate()
371 u32 div_reg, div; in ingenic_clk_recalc_rate() local
373 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
374 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
375 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
376 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
378 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
379 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
381 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
383 rate /= div; in ingenic_clk_recalc_rate()
384 } else if (clk_info->type & CGU_CLK_FIXDIV) { in ingenic_clk_recalc_rate()
385 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
393 unsigned int div) in ingenic_clk_calc_hw_div() argument
395 unsigned int i, best_i = 0, best = (unsigned int)-1; in ingenic_clk_calc_hw_div()
397 for (i = 0; i < (1 << clk_info->div.bits) in ingenic_clk_calc_hw_div()
398 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
399 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
400 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
401 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
404 if (div == best) in ingenic_clk_calc_hw_div()
416 unsigned int div, hw_div; in ingenic_clk_calc_div() local
419 div = DIV_ROUND_UP(parent_rate, req_rate); in ingenic_clk_calc_div()
421 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
422 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_calc_div()
424 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
428 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
429 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
436 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
437 div *= clk_info->div.div; in ingenic_clk_calc_div()
439 return div; in ingenic_clk_calc_div()
448 unsigned int div = 1; in ingenic_clk_round_rate() local
450 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
451 div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate); in ingenic_clk_round_rate()
452 else if (clk_info->type & CGU_CLK_FIXDIV) in ingenic_clk_round_rate()
453 div = clk_info->fixdiv.div; in ingenic_clk_round_rate()
457 return DIV_ROUND_UP(*parent_rate, div); in ingenic_clk_round_rate()
465 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, in ingenic_clk_check_stable()
466 !(reg & BIT(clk_info->div.busy_bit)), in ingenic_clk_check_stable()
476 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_rate()
478 unsigned int hw_div, div; in ingenic_clk_set_rate() local
482 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
483 div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate); in ingenic_clk_set_rate()
484 rate = DIV_ROUND_UP(parent_rate, div); in ingenic_clk_set_rate()
487 return -EINVAL; in ingenic_clk_set_rate()
489 if (clk_info->div.div_table) in ingenic_clk_set_rate()
490 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_set_rate()
492 hw_div = ((div / clk_info->div.div) - 1); in ingenic_clk_set_rate()
494 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_rate()
495 reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
498 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
499 reg &= ~(mask << clk_info->div.shift); in ingenic_clk_set_rate()
500 reg |= hw_div << clk_info->div.shift; in ingenic_clk_set_rate()
503 if (clk_info->div.stop_bit != -1) in ingenic_clk_set_rate()
504 reg &= ~BIT(clk_info->div.stop_bit); in ingenic_clk_set_rate()
507 if (clk_info->div.ce_bit != -1) in ingenic_clk_set_rate()
508 reg |= BIT(clk_info->div.ce_bit); in ingenic_clk_set_rate()
511 writel(reg, cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
514 if (clk_info->div.busy_bit != -1) in ingenic_clk_set_rate()
517 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_rate()
521 return -EINVAL; in ingenic_clk_set_rate()
528 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_enable()
531 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()
532 /* ungate the clock */ in ingenic_clk_enable()
533 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_enable()
534 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
535 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_enable()
537 if (clk_info->gate.delay_us) in ingenic_clk_enable()
538 udelay(clk_info->gate.delay_us); in ingenic_clk_enable()
548 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_disable()
551 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()
552 /* gate the clock */ in ingenic_clk_disable()
553 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_disable()
554 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
555 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_disable()
563 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_is_enabled()
566 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()
567 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
591 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; in ingenic_register_clock()
597 int err = -EINVAL; in ingenic_register_clock()
599 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
601 if (clk_info->type == CGU_CLK_EXT) { in ingenic_register_clock()
602 clk = of_clk_get_by_name(cgu->np, clk_info->name); in ingenic_register_clock()
604 pr_err("%s: no external clock '%s' provided\n", in ingenic_register_clock()
605 __func__, clk_info->name); in ingenic_register_clock()
606 err = -ENODEV; in ingenic_register_clock()
609 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
614 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
618 if (!clk_info->type) { in ingenic_register_clock()
619 pr_err("%s: no clock type specified for '%s'\n", __func__, in ingenic_register_clock()
620 clk_info->name); in ingenic_register_clock()
626 err = -ENOMEM; in ingenic_register_clock()
630 ingenic_clk->hw.init = &clk_init; in ingenic_register_clock()
631 ingenic_clk->cgu = cgu; in ingenic_register_clock()
632 ingenic_clk->idx = idx; in ingenic_register_clock()
634 clk_init.name = clk_info->name; in ingenic_register_clock()
638 caps = clk_info->type; in ingenic_register_clock()
643 /* pass rate changes to the parent clock */ in ingenic_register_clock()
651 num_possible = 1 << clk_info->mux.bits; in ingenic_register_clock()
653 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
656 if (clk_info->parents[i] == -1) in ingenic_register_clock()
659 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
668 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
670 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
675 clk_init.ops = clk_info->custom.clk_ops; in ingenic_register_clock()
680 pr_err("%s: custom clock may not be combined with type 0x%x\n", in ingenic_register_clock()
709 pr_err("%s: unknown clock type 0x%x\n", __func__, caps); in ingenic_register_clock()
713 clk = clk_register(NULL, &ingenic_clk->hw); in ingenic_register_clock()
715 pr_err("%s: failed to register clock '%s'\n", __func__, in ingenic_register_clock()
716 clk_info->name); in ingenic_register_clock()
721 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
725 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
742 cgu->base = of_iomap(np, 0); in ingenic_cgu_new()
743 if (!cgu->base) { in ingenic_cgu_new()
748 cgu->np = np; in ingenic_cgu_new()
749 cgu->clock_info = clock_info; in ingenic_cgu_new()
750 cgu->clocks.clk_num = num_clocks; in ingenic_cgu_new()
752 spin_lock_init(&cgu->lock); in ingenic_cgu_new()
767 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), in ingenic_cgu_register_clocks()
769 if (!cgu->clocks.clks) { in ingenic_cgu_register_clocks()
770 err = -ENOMEM; in ingenic_cgu_register_clocks()
774 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
780 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get, in ingenic_cgu_register_clocks()
781 &cgu->clocks); in ingenic_cgu_register_clocks()
788 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
789 if (!cgu->clocks.clks[i]) in ingenic_cgu_register_clocks()
791 if (cgu->clock_info[i].type & CGU_CLK_EXT) in ingenic_cgu_register_clocks()
792 clk_put(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
794 clk_unregister(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
796 kfree(cgu->clocks.clks); in ingenic_cgu_register_clocks()